RDMA/nes: Fix SFP+ PHY initialization
SFP+ PHY initialization has very long delays, incorrect settings for direct attach copper cables, and inconsistent link detection. Adjust delays to the minimum required by the PHY. Worst case is now less than 4 seconds. Add new register settings for direct attach cables. Change link detection logic to use two new registers for more consistent link state detection. Reorganize code to shorten line length. Signed-off-by: Chien Tung <chien.tin.tung@intel.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
This commit is contained in:
Chien Tung
Roland Dreier
Родитель
5962c2c803
Коммит
1b9493248c
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@ -757,6 +757,10 @@ static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count,
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((port_count > 2) &&
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(nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G))) {
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/* init serdes 1 */
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if (nesadapter->phy_type[0] == NES_PHY_TYPE_ARGUS) {
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x00000000);
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x00000000);
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}
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000FF);
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if (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G) {
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serdes_common_control = nes_read_indexed(nesdev,
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@ -1259,203 +1263,155 @@ int nes_init_phy(struct nes_device *nesdev)
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{
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struct nes_adapter *nesadapter = nesdev->nesadapter;
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u32 counter = 0;
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u32 sds_common_control0;
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u32 sds;
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u32 mac_index = nesdev->mac_index;
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u32 tx_config = 0;
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u16 phy_data;
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u32 temp_phy_data = 0;
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u32 temp_phy_data2 = 0;
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u32 i = 0;
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u8 phy_type = nesadapter->phy_type[mac_index];
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u8 phy_index = nesadapter->phy_index[mac_index];
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if ((nesadapter->OneG_Mode) &&
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(nesadapter->phy_type[mac_index] != NES_PHY_TYPE_PUMA_1G)) {
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(phy_type != NES_PHY_TYPE_PUMA_1G)) {
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nes_debug(NES_DBG_PHY, "1G PHY, mac_index = %d.\n", mac_index);
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if (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_1G) {
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printk(PFX "%s: Programming mdc config for 1G\n", __func__);
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if (phy_type == NES_PHY_TYPE_1G) {
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tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
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tx_config &= 0xFFFFFFE3;
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tx_config |= 0x04;
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nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
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}
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nes_read_1G_phy_reg(nesdev, 1, nesadapter->phy_index[mac_index], &phy_data);
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nes_debug(NES_DBG_PHY, "Phy data from register 1 phy address %u = 0x%X.\n",
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nesadapter->phy_index[mac_index], phy_data);
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nes_write_1G_phy_reg(nesdev, 23, nesadapter->phy_index[mac_index], 0xb000);
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nes_read_1G_phy_reg(nesdev, 1, phy_index, &phy_data);
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nes_write_1G_phy_reg(nesdev, 23, phy_index, 0xb000);
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/* Reset the PHY */
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nes_write_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], 0x8000);
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nes_write_1G_phy_reg(nesdev, 0, phy_index, 0x8000);
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udelay(100);
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counter = 0;
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do {
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nes_read_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], &phy_data);
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nes_debug(NES_DBG_PHY, "Phy data from register 0 = 0x%X.\n", phy_data);
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if (counter++ > 100) break;
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nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
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if (counter++ > 100)
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break;
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} while (phy_data & 0x8000);
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/* Setting no phy loopback */
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phy_data &= 0xbfff;
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phy_data |= 0x1140;
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nes_write_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], phy_data);
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nes_read_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], &phy_data);
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nes_debug(NES_DBG_PHY, "Phy data from register 0 = 0x%X.\n", phy_data);
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nes_read_1G_phy_reg(nesdev, 0x17, nesadapter->phy_index[mac_index], &phy_data);
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nes_debug(NES_DBG_PHY, "Phy data from register 0x17 = 0x%X.\n", phy_data);
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nes_read_1G_phy_reg(nesdev, 0x1e, nesadapter->phy_index[mac_index], &phy_data);
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nes_debug(NES_DBG_PHY, "Phy data from register 0x1e = 0x%X.\n", phy_data);
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nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data);
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nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
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nes_read_1G_phy_reg(nesdev, 0x17, phy_index, &phy_data);
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nes_read_1G_phy_reg(nesdev, 0x1e, phy_index, &phy_data);
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/* Setting the interrupt mask */
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nes_read_1G_phy_reg(nesdev, 0x19, nesadapter->phy_index[mac_index], &phy_data);
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nes_debug(NES_DBG_PHY, "Phy data from register 0x19 = 0x%X.\n", phy_data);
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nes_write_1G_phy_reg(nesdev, 0x19, nesadapter->phy_index[mac_index], 0xffee);
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nes_read_1G_phy_reg(nesdev, 0x19, nesadapter->phy_index[mac_index], &phy_data);
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nes_debug(NES_DBG_PHY, "Phy data from register 0x19 = 0x%X.\n", phy_data);
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nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data);
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nes_write_1G_phy_reg(nesdev, 0x19, phy_index, 0xffee);
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nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data);
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/* turning on flow control */
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nes_read_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index], &phy_data);
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nes_debug(NES_DBG_PHY, "Phy data from register 0x4 = 0x%X.\n", phy_data);
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nes_write_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index],
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(phy_data & ~(0x03E0)) | 0xc00);
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/* nes_write_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index],
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phy_data | 0xc00); */
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nes_read_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index], &phy_data);
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nes_debug(NES_DBG_PHY, "Phy data from register 0x4 = 0x%X.\n", phy_data);
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nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data);
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nes_write_1G_phy_reg(nesdev, 4, phy_index, (phy_data & ~(0x03E0)) | 0xc00);
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nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data);
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nes_read_1G_phy_reg(nesdev, 9, nesadapter->phy_index[mac_index], &phy_data);
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nes_debug(NES_DBG_PHY, "Phy data from register 0x9 = 0x%X.\n", phy_data);
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/* Clear Half duplex */
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nes_write_1G_phy_reg(nesdev, 9, nesadapter->phy_index[mac_index],
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phy_data & ~(0x0100));
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nes_read_1G_phy_reg(nesdev, 9, nesadapter->phy_index[mac_index], &phy_data);
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nes_debug(NES_DBG_PHY, "Phy data from register 0x9 = 0x%X.\n", phy_data);
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nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data);
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nes_write_1G_phy_reg(nesdev, 9, phy_index, phy_data & ~(0x0100));
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nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data);
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nes_read_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], &phy_data);
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nes_write_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], phy_data | 0x0300);
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} else {
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if ((nesadapter->phy_type[mac_index] == NES_PHY_TYPE_IRIS) ||
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(nesadapter->phy_type[mac_index] == NES_PHY_TYPE_ARGUS)) {
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/* setup 10G MDIO operation */
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tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
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tx_config &= 0xFFFFFFE3;
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tx_config |= 0x15;
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nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
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}
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if ((nesadapter->phy_type[mac_index] == NES_PHY_TYPE_ARGUS)) {
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nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7ee);
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nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
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nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data | 0x0300);
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temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
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mdelay(10);
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nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7ee);
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temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
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return 0;
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}
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/*
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* if firmware is already running (like from a
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* driver un-load/load, don't do anything.
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*/
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if (temp_phy_data == temp_phy_data2) {
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/* configure QT2505 AMCC PHY */
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nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0x0000, 0x8000);
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nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc300, 0x0000);
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nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc302, 0x0044);
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nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc318, 0x0052);
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nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc319, 0x0008);
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nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc31a, 0x0098);
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nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0x0026, 0x0E00);
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nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0x0027, 0x0001);
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nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0x0028, 0xA528);
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if ((phy_type == NES_PHY_TYPE_IRIS) ||
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(phy_type == NES_PHY_TYPE_ARGUS)) {
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/* setup 10G MDIO operation */
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tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
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tx_config &= 0xFFFFFFE3;
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tx_config |= 0x15;
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nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
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}
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if ((phy_type == NES_PHY_TYPE_ARGUS)) {
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/* Check firmware heartbeat */
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nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
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temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
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udelay(1500);
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nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
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temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
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/*
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* remove micro from reset; chip boots from ROM,
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* uploads EEPROM f/w image, uC executes f/w
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*/
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nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc300, 0x0002);
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if (temp_phy_data != temp_phy_data2)
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return 0;
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/*
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* wait for heart beat to start to
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* know loading is done
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*/
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counter = 0;
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do {
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nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7ee);
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temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
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if (counter++ > 1000) {
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nes_debug(NES_DBG_PHY, "AMCC PHY- breaking from heartbeat check <this is bad!!!> \n");
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break;
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}
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mdelay(100);
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nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7ee);
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temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
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} while ((temp_phy_data2 == temp_phy_data));
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/* no heartbeat, configure the PHY */
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nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0x0000, 0x8000);
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nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0000);
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nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x000C);
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nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A);
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nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052);
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nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0008);
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nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0098);
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nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00);
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nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0001);
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/*
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* wait for tracking to start to know
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* f/w is good to go
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*/
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counter = 0;
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do {
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nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7fd);
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temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
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if (counter++ > 1000) {
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nes_debug(NES_DBG_PHY, "AMCC PHY- breaking from status check <this is bad!!!> \n");
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break;
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}
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mdelay(1000);
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/*
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* nes_debug(NES_DBG_PHY, "AMCC PHY- phy_status not ready yet = 0x%02X\n",
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* temp_phy_data);
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*/
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} while (((temp_phy_data & 0xff) != 0x50) && ((temp_phy_data & 0xff) != 0x70));
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/* setup LEDs */
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nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x0007);
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nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x000A);
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nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0009);
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/* set LOS Control invert RXLOSB_I_PADINV */
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nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xd003, 0x0000);
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/* set LOS Control to mask of RXLOSB_I */
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nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc314, 0x0042);
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/* set LED1 to input mode (LED1 and LED2 share same LED) */
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nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xd006, 0x0007);
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/* set LED2 to RX link_status and activity */
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nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xd007, 0x000A);
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/* set LED3 to RX link_status */
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nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xd008, 0x0009);
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nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0028, 0xA528);
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/*
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* reset the res-calibration on t2
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* serdes; ensures it is stable after
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* the amcc phy is stable
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*/
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/* Bring PHY out of reset */
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nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0002);
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sds_common_control0 = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0);
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sds_common_control0 |= 0x1;
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds_common_control0);
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/* release the res-calibration reset */
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sds_common_control0 &= 0xfffffffe;
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nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds_common_control0);
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i = 0;
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while (((nes_read32(nesdev->regs + NES_SOFTWARE_RESET) & 0x00000040) != 0x00000040)
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&& (i++ < 5000)) {
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/* mdelay(1); */
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}
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/*
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* wait for link train done before moving on,
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* or will get an interupt storm
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*/
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counter = 0;
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do {
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temp_phy_data = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 +
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(0x200 * (nesdev->mac_index & 1)));
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if (counter++ > 1000) {
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nes_debug(NES_DBG_PHY, "AMCC PHY- breaking from link train wait <this is bad, link didnt train!!!>\n");
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break;
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}
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mdelay(1);
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} while (((temp_phy_data & 0x0f1f0000) != 0x0f0f0000));
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/* Check for heartbeat */
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counter = 0;
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mdelay(690);
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nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
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temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
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do {
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if (counter++ > 150) {
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nes_debug(NES_DBG_PHY, "No PHY heartbeat\n");
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break;
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}
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}
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mdelay(1);
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nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
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temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
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} while ((temp_phy_data2 == temp_phy_data));
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/* wait for tracking */
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counter = 0;
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do {
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nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7fd);
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temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
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if (counter++ > 300) {
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nes_debug(NES_DBG_PHY, "PHY did not track\n");
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break;
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}
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mdelay(10);
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} while (((temp_phy_data & 0xff) != 0x50) && ((temp_phy_data & 0xff) != 0x70));
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/* setup signal integrity */
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nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd003, 0x0000);
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nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00D, 0x00FE);
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nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00E, 0x0032);
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||||
nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00F, 0x0002);
|
||||
nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc314, 0x0063);
|
||||
|
||||
/* reset serdes */
|
||||
sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 +
|
||||
mac_index * 0x200);
|
||||
sds |= 0x1;
|
||||
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 +
|
||||
mac_index * 0x200, sds);
|
||||
sds &= 0xfffffffe;
|
||||
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 +
|
||||
mac_index * 0x200, sds);
|
||||
|
||||
counter = 0;
|
||||
while (((nes_read32(nesdev->regs + NES_SOFTWARE_RESET) & 0x00000040) != 0x00000040)
|
||||
&& (counter++ < 5000))
|
||||
;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -2483,19 +2439,18 @@ static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
|
|||
nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9004);
|
||||
nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9005);
|
||||
/* check link status */
|
||||
nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 1);
|
||||
nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9003);
|
||||
temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
|
||||
u32temp = 100;
|
||||
do {
|
||||
nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 1);
|
||||
|
||||
phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
|
||||
if ((phy_data == temp_phy_data) || (!(--u32temp)))
|
||||
break;
|
||||
temp_phy_data = phy_data;
|
||||
} while (1);
|
||||
nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
|
||||
nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
|
||||
nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
|
||||
phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
|
||||
|
||||
phy_data = (!temp_phy_data && (phy_data == 0x8000)) ? 0x4 : 0x0;
|
||||
|
||||
nes_debug(NES_DBG_PHY, "%s: Phy data = 0x%04X, link was %s.\n",
|
||||
__func__, phy_data, nesadapter->mac_link_down ? "DOWN" : "UP");
|
||||
__func__, phy_data, nesadapter->mac_link_down[mac_index] ? "DOWN" : "UP");
|
||||
break;
|
||||
|
||||
case NES_PHY_TYPE_PUMA_1G:
|
||||
|
|
|
|||
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