From 1ba4c322caaecfb68c1e175599398caef946a525 Mon Sep 17 00:00:00 2001 From: Minda Chen Date: Tue, 26 Aug 2014 10:50:42 +0800 Subject: [PATCH] mmc: sdhci-sirf: fix 8bit width enable by overwriting set_bus_width the implementation of CSR SDHCI controller is a modified version of the one described in the 1.0 specification, and not a normal 3.0 controller. and 8bit-width enable bit of CSR MMC hosts is 3, while stardard hosts use bit 5. this patch fixes the functionality of 8bit transfer in mmc controllers and improve performance for mmc0 a lot. Signed-off-by: Minda Chen Signed-off-by: Barry Song Reviewed-by: Romain Izard Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-sirf.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-sirf.c b/drivers/mmc/host/sdhci-sirf.c index e15dc891ba01..68a39718a171 100644 --- a/drivers/mmc/host/sdhci-sirf.c +++ b/drivers/mmc/host/sdhci-sirf.c @@ -15,6 +15,8 @@ #include #include "sdhci-pltfm.h" +#define SDHCI_SIRF_8BITBUS BIT(3) + struct sdhci_sirf_priv { struct clk *clk; int gpio_cd; @@ -27,10 +29,30 @@ static unsigned int sdhci_sirf_get_max_clk(struct sdhci_host *host) return clk_get_rate(priv->clk); } +static void sdhci_sirf_set_bus_width(struct sdhci_host *host, int width) +{ + u8 ctrl; + + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + ctrl &= ~(SDHCI_CTRL_4BITBUS | SDHCI_SIRF_8BITBUS); + + /* + * CSR atlas7 and prima2 SD host version is not 3.0 + * 8bit-width enable bit of CSR SD hosts is 3, + * while stardard hosts use bit 5 + */ + if (width == MMC_BUS_WIDTH_8) + ctrl |= SDHCI_SIRF_8BITBUS; + else if (width == MMC_BUS_WIDTH_4) + ctrl |= SDHCI_CTRL_4BITBUS; + + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); +} + static struct sdhci_ops sdhci_sirf_ops = { .set_clock = sdhci_set_clock, .get_max_clock = sdhci_sirf_get_max_clk, - .set_bus_width = sdhci_set_bus_width, + .set_bus_width = sdhci_sirf_set_bus_width, .reset = sdhci_reset, .set_uhs_signaling = sdhci_set_uhs_signaling, };