[IA64] Reschedule fsys_bubble_down().
Improvements come from eliminating srlz.i, not scheduling AR/CR-reads
too early (while there are others still pending), scheduling the
backing-store switch as well as possible, splitting the BBB bundle
into a MIB/MBB pair.
Why is it safe to eliminate the srlz.i? Observe
that we used to clear bits ~PSR_PRESERVED_BITS in PSR.L. Since
PSR_PRESERVED_BITS==PSR.{UP,MFL,MFH,PK,DT,PP,SP,RT,IC}, we
ended up clearing PSR.{BE,AC,I,DFL,DFH,DI,DB,SI,TB}. However,
PSR.BE : already is turned off in __kernel_syscall_via_epc()
PSR.AC : don't care (kernel normally turns PSR.AC on)
PSR.I : already turned off by the time fsys_bubble_down gets invoked
PSR.DFL: always 0 (kernel never turns it on)
PSR.DFH: don't care --- kernel never touches f32-f127 on its own
initiative
PSR.DI : always 0 (kernel never turns it on)
PSR.SI : always 0 (kernel never turns it on)
PSR.DB : don't care --- kernel never enables kernel-level breakpoints
PSR.TB : must be 0 already; if it wasn't zero on entry to
__kernel_syscall_via_epc, the branch to fsys_bubble_down
will trigger a taken branch; the taken-trap-handler then
converts the syscall into a break-based system-call.
In other words: all the bits we're clearying are either 0 already or
are don't cares! Thus, we don't have to write PSR.L at all and we
don't have to do a srlz.i either.
Good for another ~20 cycle improvement for EPC-based heavy-weight
syscalls.
Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
David Mosberger-Tang
Tony Luck
Родитель
21bc4f9b34
Коммит
1ba7be7d69
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@ -549,9 +549,6 @@ GLOBAL_ENTRY(fsys_bubble_down)
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* - r27: ar.rsc
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* - r29: psr
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*/
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# define PSR_PRESERVED_BITS (IA64_PSR_UP | IA64_PSR_MFL | IA64_PSR_MFH | IA64_PSR_PK \
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| IA64_PSR_DT | IA64_PSR_PP | IA64_PSR_SP | IA64_PSR_RT \
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| IA64_PSR_IC)
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/*
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* Reading psr.l gives us only bits 0-31, psr.it, and psr.mc. The rest we have
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* to synthesize.
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@ -560,62 +557,58 @@ GLOBAL_ENTRY(fsys_bubble_down)
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| IA64_PSR_BN | IA64_PSR_I)
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invala
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movl r8=PSR_ONE_BITS
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movl r14=ia64_ret_from_syscall
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mov r25=ar.unat // save ar.unat (5 cyc)
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movl r9=PSR_PRESERVED_BITS
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mov ar.rsc=0 // set enforced lazy mode, pl 0, little-endian, loadrs=0
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nop.m 0
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movl r28=__kernel_syscall_via_break
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;;
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mov r23=ar.bspstore // save ar.bspstore (12 cyc)
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mov r31=pr // save pr (2 cyc)
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mov r20=r1 // save caller's gp in r20
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;;
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mov r2=r16 // copy current task addr to addl-addressable register
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and r9=r9,r29
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mov r19=b6 // save b6 (2 cyc)
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;;
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mov psr.l=r9 // slam the door (17 cyc to srlz.i)
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or r29=r8,r29 // construct cr.ipsr value to save
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addl r22=IA64_RBS_OFFSET,r2 // compute base of RBS
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;;
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// GAS reports a spurious RAW hazard on the read of ar.rnat because it thinks
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// we may be reading ar.itc after writing to psr.l. Avoid that message with
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// this directive:
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dv_serialize_data
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mov.m r24=ar.rnat // read ar.rnat (5 cyc lat)
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lfetch.fault.excl.nt1 [r22]
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adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r2
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// ensure previous insn group is issued before we stall for srlz.i:
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;;
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srlz.i // ensure new psr.l has been established
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/////////////////////////////////////////////////////////////////////////////
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////////// from this point on, execution is not interruptible anymore
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/////////////////////////////////////////////////////////////////////////////
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addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r2 // compute base of memory stack
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cmp.ne pKStk,pUStk=r0,r0 // set pKStk <- 0, pUStk <- 1
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mov r2=r16 // copy current task addr to addl-addressable register
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adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
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mov r31=pr // save pr (2 cyc)
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;;
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st1 [r16]=r0 // clear current->thread.on_ustack flag
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mov ar.bspstore=r22 // switch to kernel RBS
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mov b6=r18 // copy syscall entry-point to b6 (7 cyc)
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addl r22=IA64_RBS_OFFSET,r2 // compute base of RBS
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add r3=TI_FLAGS+IA64_TASK_SIZE,r2
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;;
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ld4 r3=[r3] // r2 = current_thread_info()->flags
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lfetch.fault.excl.nt1 [r22]
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nop.i 0
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;;
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mov ar.rsc=0 // set enforced lazy mode, pl 0, little-endian, loadrs=0
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nop.m 0
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nop.i 0
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;;
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mov r23=ar.bspstore // save ar.bspstore (12 cyc)
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mov.m r24=ar.rnat // read ar.rnat (5 cyc lat)
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nop.i 0
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;;
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mov ar.bspstore=r22 // switch to kernel RBS
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movl r8=PSR_ONE_BITS // X
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;;
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mov r25=ar.unat // save ar.unat (5 cyc)
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mov r19=b6 // save b6 (2 cyc)
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mov r20=r1 // save caller's gp in r20
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;;
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or r29=r8,r29 // construct cr.ipsr value to save
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mov b6=r18 // copy syscall entry-point to b6 (7 cyc)
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addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r2 // compute base of memory stack
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mov r18=ar.bsp // save (kernel) ar.bsp (12 cyc)
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mov ar.rsc=0x3 // set eager mode, pl 0, little-endian, loadrs=0
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cmp.ne pKStk,pUStk=r0,r0 // set pKStk <- 0, pUStk <- 1
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br.call.sptk.many b7=ia64_syscall_setup
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;;
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mov ar.rsc=0x3 // set eager mode, pl 0, little-endian, loadrs=0
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mov rp=r14 // set the real return addr
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nop.i 0
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;;
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ssm psr.i
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movl r2=ia64_ret_from_syscall
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;;
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mov rp=r2 // set the real return addr
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tbit.z p8,p0=r3,TIF_SYSCALL_TRACE
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;;
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(p10) br.cond.spnt.many ia64_ret_from_syscall // p10==true means out registers are more than 8
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nop.m 0
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(p8) br.call.sptk.many b6=b6 // ignore this return addr
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br.cond.sptk ia64_trace_syscall
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br.cond.spnt ia64_trace_syscall
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END(fsys_bubble_down)
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.rodata
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