[POWERPC] Add PMC type to cputable
Add cputable entries for which type of PMC implementation the processor has. I've only filled in the current 64-bit processors, the unfilled default value will have same behaviour as before so it can be done over time as needed. Also tidy up the dummy_perf implementation a bit, aggregating it into one function with ifdefs instead of several. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
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@ -86,6 +86,7 @@ static struct cpu_spec cpu_specs[] = {
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.num_pmcs = 8,
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.pmc_type = PPC_PMC_IBM,
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.oprofile_cpu_type = "ppc64/power3",
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.oprofile_type = PPC_OPROFILE_RS64,
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.platform = "power3",
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@ -99,6 +100,7 @@ static struct cpu_spec cpu_specs[] = {
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.num_pmcs = 8,
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.pmc_type = PPC_PMC_IBM,
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.oprofile_cpu_type = "ppc64/power3",
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.oprofile_type = PPC_OPROFILE_RS64,
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.platform = "power3",
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@ -112,6 +114,7 @@ static struct cpu_spec cpu_specs[] = {
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.num_pmcs = 8,
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.pmc_type = PPC_PMC_IBM,
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.oprofile_cpu_type = "ppc64/rs64",
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.oprofile_type = PPC_OPROFILE_RS64,
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.platform = "rs64",
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@ -125,6 +128,7 @@ static struct cpu_spec cpu_specs[] = {
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.num_pmcs = 8,
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.pmc_type = PPC_PMC_IBM,
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.oprofile_cpu_type = "ppc64/rs64",
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.oprofile_type = PPC_OPROFILE_RS64,
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.platform = "rs64",
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@ -138,6 +142,7 @@ static struct cpu_spec cpu_specs[] = {
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.num_pmcs = 8,
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.pmc_type = PPC_PMC_IBM,
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.oprofile_cpu_type = "ppc64/rs64",
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.oprofile_type = PPC_OPROFILE_RS64,
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.platform = "rs64",
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@ -151,6 +156,7 @@ static struct cpu_spec cpu_specs[] = {
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.num_pmcs = 8,
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.pmc_type = PPC_PMC_IBM,
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.oprofile_cpu_type = "ppc64/rs64",
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.oprofile_type = PPC_OPROFILE_RS64,
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.platform = "rs64",
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@ -164,6 +170,7 @@ static struct cpu_spec cpu_specs[] = {
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.num_pmcs = 8,
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.pmc_type = PPC_PMC_IBM,
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.oprofile_cpu_type = "ppc64/power4",
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.oprofile_type = PPC_OPROFILE_POWER4,
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.platform = "power4",
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@ -177,6 +184,7 @@ static struct cpu_spec cpu_specs[] = {
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.num_pmcs = 8,
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.pmc_type = PPC_PMC_IBM,
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.oprofile_cpu_type = "ppc64/power4",
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.oprofile_type = PPC_OPROFILE_POWER4,
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.platform = "power4",
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@ -191,6 +199,7 @@ static struct cpu_spec cpu_specs[] = {
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.num_pmcs = 8,
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.pmc_type = PPC_PMC_IBM,
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.cpu_setup = __setup_cpu_ppc970,
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.cpu_restore = __restore_cpu_ppc970,
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.oprofile_cpu_type = "ppc64/970",
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@ -207,6 +216,7 @@ static struct cpu_spec cpu_specs[] = {
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.num_pmcs = 8,
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.pmc_type = PPC_PMC_IBM,
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.cpu_setup = __setup_cpu_ppc970,
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.cpu_restore = __restore_cpu_ppc970,
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.oprofile_cpu_type = "ppc64/970",
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@ -239,6 +249,7 @@ static struct cpu_spec cpu_specs[] = {
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.num_pmcs = 8,
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.pmc_type = PPC_PMC_IBM,
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.cpu_setup = __setup_cpu_ppc970,
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.oprofile_cpu_type = "ppc64/970",
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.oprofile_type = PPC_OPROFILE_POWER4,
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@ -253,6 +264,7 @@ static struct cpu_spec cpu_specs[] = {
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.num_pmcs = 6,
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.pmc_type = PPC_PMC_IBM,
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.oprofile_cpu_type = "ppc64/power5",
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.oprofile_type = PPC_OPROFILE_POWER4,
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/* SIHV / SIPR bits are implemented on POWER4+ (GQ)
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@ -271,6 +283,7 @@ static struct cpu_spec cpu_specs[] = {
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.num_pmcs = 6,
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.pmc_type = PPC_PMC_IBM,
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.oprofile_cpu_type = "ppc64/power5+",
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.oprofile_type = PPC_OPROFILE_POWER4,
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.oprofile_mmcra_sihv = MMCRA_SIHV,
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@ -321,6 +334,7 @@ static struct cpu_spec cpu_specs[] = {
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.num_pmcs = 6,
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.pmc_type = PPC_PMC_IBM,
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.oprofile_cpu_type = "ppc64/power6",
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.oprofile_type = PPC_OPROFILE_POWER4,
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.oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
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@ -340,6 +354,7 @@ static struct cpu_spec cpu_specs[] = {
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.num_pmcs = 4,
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.pmc_type = PPC_PMC_IBM,
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.oprofile_cpu_type = "ppc64/cell-be",
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.oprofile_type = PPC_OPROFILE_CELL,
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.platform = "ppc-cell-be",
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@ -353,6 +368,7 @@ static struct cpu_spec cpu_specs[] = {
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.icache_bsize = 64,
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.dcache_bsize = 64,
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.num_pmcs = 6,
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.pmc_type = PPC_PMC_PA6T,
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.platform = "pa6t",
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},
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{ /* default match */
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@ -364,6 +380,7 @@ static struct cpu_spec cpu_specs[] = {
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.num_pmcs = 6,
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.pmc_type = PPC_PMC_IBM,
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.platform = "power4",
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}
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#endif /* CONFIG_PPC64 */
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@ -19,38 +19,21 @@
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#include <asm/processor.h>
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#include <asm/pmc.h>
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#ifndef MMCR0_PMA0
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#define MMCR0_PMA0 0
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#endif
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static void dummy_perf(struct pt_regs *regs)
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{
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#if defined(CONFIG_FSL_BOOKE) && !defined(CONFIG_E200)
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static void dummy_perf(struct pt_regs *regs)
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{
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unsigned int pmgc0 = mfpmr(PMRN_PMGC0);
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pmgc0 &= ~PMGC0_PMIE;
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mtpmr(PMRN_PMGC0, pmgc0);
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}
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mtpmr(PMRN_PMGC0, mfpmr(PMRN_PMGC0) & ~PMGC0_PMIE);
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#elif defined(CONFIG_PPC64) || defined(CONFIG_6xx)
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#ifndef MMCR0_PMAO
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#define MMCR0_PMAO 0
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#endif
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/* Ensure exceptions are disabled */
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static void dummy_perf(struct pt_regs *regs)
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{
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unsigned int mmcr0 = mfspr(SPRN_MMCR0);
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mmcr0 &= ~(MMCR0_PMXE|MMCR0_PMAO);
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mtspr(SPRN_MMCR0, mmcr0);
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}
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mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~(MMCR0_PMXE|MMCR0_PMA0));
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#else
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/* Ensure exceptions are disabled */
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static void dummy_perf(struct pt_regs *regs)
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{
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unsigned int mmcr0 = mfspr(SPRN_MMCR0);
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mmcr0 &= ~(MMCR0_PMXE);
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mtspr(SPRN_MMCR0, mmcr0);
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}
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mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~MMCR0_PMXE);
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#endif
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}
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static DEFINE_SPINLOCK(pmc_owner_lock);
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static void *pmc_owner_caller; /* mostly for debugging */
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@ -50,6 +50,12 @@ enum powerpc_oprofile_type {
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PPC_OPROFILE_CELL = 5,
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};
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enum powerpc_pmc_type {
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PPC_PMC_DEFAULT = 0,
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PPC_PMC_IBM = 1,
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PPC_PMC_PA6T = 2,
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};
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struct cpu_spec {
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/* CPU is matched via (PVR & pvr_mask) == pvr_value */
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unsigned int pvr_mask;
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@ -65,6 +71,7 @@ struct cpu_spec {
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/* number of performance monitor counters */
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unsigned int num_pmcs;
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enum powerpc_pmc_type pmc_type;
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/* this is called to initialize various CPU bits like L1 cache,
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* BHT, SPD, etc... from head.S before branching to identify_machine
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