dt-bindings: Add common bindings for ARM and RISC-V idle states
The RISC-V CPU idle states will be described in under the /cpus/idle-states DT node in the same way as ARM CPU idle states. This patch adds common bindings documentation for both ARM and RISC-V idle states. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Guo Ren <guoren@kernel.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Anup Patel
Palmer Dabbelt
Родитель
6abf32f1d9
Коммит
1bd524f7e8
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@ -81,4 +81,4 @@ Example:
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};
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};
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[1]. Documentation/devicetree/bindings/arm/idle-states.yaml
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[1]. Documentation/devicetree/bindings/cpu/idle-states.yaml
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@ -101,7 +101,7 @@ properties:
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bindings in [1]) must specify this property.
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[1] Kernel documentation - ARM idle states bindings
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Documentation/devicetree/bindings/arm/idle-states.yaml
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Documentation/devicetree/bindings/cpu/idle-states.yaml
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patternProperties:
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"^power-domain-":
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@ -1,25 +1,30 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/idle-states.yaml#
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$id: http://devicetree.org/schemas/cpu/idle-states.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM idle states binding description
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title: Idle states binding description
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maintainers:
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- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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- Anup Patel <anup@brainfault.org>
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description: |+
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==========================================
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1 - Introduction
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==========================================
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ARM systems contain HW capable of managing power consumption dynamically,
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where cores can be put in different low-power states (ranging from simple wfi
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to power gating) according to OS PM policies. The CPU states representing the
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range of dynamic idle states that a processor can enter at run-time, can be
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specified through device tree bindings representing the parameters required to
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enter/exit specific idle states on a given processor.
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ARM and RISC-V systems contain HW capable of managing power consumption
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dynamically, where cores can be put in different low-power states (ranging
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from simple wfi to power gating) according to OS PM policies. The CPU states
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representing the range of dynamic idle states that a processor can enter at
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run-time, can be specified through device tree bindings representing the
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parameters required to enter/exit specific idle states on a given processor.
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==========================================
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2 - ARM idle states
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==========================================
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According to the Server Base System Architecture document (SBSA, [3]), the
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power states an ARM CPU can be put into are identified by the following list:
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@ -43,8 +48,23 @@ description: |+
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The device tree binding definition for ARM idle states is the subject of this
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document.
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==========================================
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3 - RISC-V idle states
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==========================================
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On RISC-V systems, the HARTs (or CPUs) [6] can be put in platform specific
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suspend (or idle) states (ranging from simple WFI, power gating, etc). The
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RISC-V SBI v0.3 (or higher) [7] hart state management extension provides a
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standard mechanism for OS to request HART state transitions.
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The platform specific suspend (or idle) states of a hart can be either
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retentive or non-rententive in nature. A retentive suspend state will
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preserve HART registers and CSR values for all privilege modes whereas
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a non-retentive suspend state will not preserve HART registers and CSR
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values.
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===========================================
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2 - idle-states definitions
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4 - idle-states definitions
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===========================================
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Idle states are characterized for a specific system through a set of
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@ -211,10 +231,10 @@ description: |+
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properties specification that is the subject of the following sections.
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===========================================
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3 - idle-states node
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5 - idle-states node
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===========================================
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ARM processor idle states are defined within the idle-states node, which is
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The processor idle states are defined within the idle-states node, which is
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a direct child of the cpus node [1] and provides a container where the
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processor idle states, defined as device tree nodes, are listed.
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@ -223,7 +243,7 @@ description: |+
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just supports idle_standby, an idle-states node is not required.
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===========================================
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4 - References
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6 - References
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===========================================
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[1] ARM Linux Kernel documentation - CPUs bindings
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@ -238,9 +258,15 @@ description: |+
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[4] ARM Architecture Reference Manuals
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http://infocenter.arm.com/help/index.jsp
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[6] ARM Linux Kernel documentation - Booting AArch64 Linux
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[5] ARM Linux Kernel documentation - Booting AArch64 Linux
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Documentation/arm64/booting.rst
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[6] RISC-V Linux Kernel documentation - CPUs bindings
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Documentation/devicetree/bindings/riscv/cpus.yaml
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[7] RISC-V Supervisor Binary Interface (SBI)
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http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc
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properties:
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$nodename:
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const: idle-states
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@ -253,7 +279,7 @@ properties:
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On ARM 32-bit systems this property is optional
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This assumes that the "enable-method" property is set to "psci" in the cpu
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node[6] that is responsible for setting up CPU idle management in the OS
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node[5] that is responsible for setting up CPU idle management in the OS
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implementation.
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const: psci
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@ -265,8 +291,8 @@ patternProperties:
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as follows.
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The idle state entered by executing the wfi instruction (idle_standby
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SBSA,[3][4]) is considered standard on all ARM platforms and therefore
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must not be listed.
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SBSA,[3][4]) is considered standard on all ARM and RISC-V platforms and
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therefore must not be listed.
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In addition to the properties listed above, a state node may require
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additional properties specific to the entry-method defined in the
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@ -275,7 +301,27 @@ patternProperties:
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properties:
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compatible:
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const: arm,idle-state
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enum:
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- arm,idle-state
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- riscv,idle-state
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arm,psci-suspend-param:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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power_state parameter to pass to the ARM PSCI suspend call.
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Device tree nodes that require usage of PSCI CPU_SUSPEND function
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(i.e. idle states node with entry-method property is set to "psci")
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must specify this property.
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riscv,sbi-suspend-param:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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suspend_type parameter to pass to the RISC-V SBI HSM suspend call.
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This property is required in idle state nodes of device tree meant
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for RISC-V systems. For more details on the suspend_type parameter
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refer the SBI specifiation v0.3 (or higher) [7].
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local-timer-stop:
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description:
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@ -317,6 +363,8 @@ patternProperties:
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description:
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A string used as a descriptive name for the idle state.
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additionalProperties: false
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required:
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- compatible
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- entry-latency-us
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@ -658,4 +706,150 @@ examples:
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};
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};
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- |
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// Example 3 (RISC-V 64-bit, 4-cpu systems, two clusters):
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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cpu@0 {
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device_type = "cpu";
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compatible = "riscv";
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reg = <0x0>;
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv48";
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cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
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&CLUSTER_RET_0 &CLUSTER_NONRET_0>;
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cpu_intc0: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "riscv";
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reg = <0x1>;
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv48";
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cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
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&CLUSTER_RET_0 &CLUSTER_NONRET_0>;
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cpu_intc1: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@10 {
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device_type = "cpu";
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compatible = "riscv";
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reg = <0x10>;
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv48";
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cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
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&CLUSTER_RET_1 &CLUSTER_NONRET_1>;
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cpu_intc10: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@11 {
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device_type = "cpu";
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compatible = "riscv";
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reg = <0x11>;
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv48";
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cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
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&CLUSTER_RET_1 &CLUSTER_NONRET_1>;
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cpu_intc11: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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idle-states {
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CPU_RET_0_0: cpu-retentive-0-0 {
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compatible = "riscv,idle-state";
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riscv,sbi-suspend-param = <0x10000000>;
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entry-latency-us = <20>;
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exit-latency-us = <40>;
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min-residency-us = <80>;
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};
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CPU_NONRET_0_0: cpu-nonretentive-0-0 {
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compatible = "riscv,idle-state";
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riscv,sbi-suspend-param = <0x90000000>;
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entry-latency-us = <250>;
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exit-latency-us = <500>;
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min-residency-us = <950>;
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};
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CLUSTER_RET_0: cluster-retentive-0 {
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compatible = "riscv,idle-state";
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riscv,sbi-suspend-param = <0x11000000>;
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local-timer-stop;
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entry-latency-us = <50>;
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exit-latency-us = <100>;
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min-residency-us = <250>;
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wakeup-latency-us = <130>;
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};
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CLUSTER_NONRET_0: cluster-nonretentive-0 {
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compatible = "riscv,idle-state";
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riscv,sbi-suspend-param = <0x91000000>;
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local-timer-stop;
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entry-latency-us = <600>;
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exit-latency-us = <1100>;
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min-residency-us = <2700>;
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wakeup-latency-us = <1500>;
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};
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CPU_RET_1_0: cpu-retentive-1-0 {
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compatible = "riscv,idle-state";
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riscv,sbi-suspend-param = <0x10000010>;
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entry-latency-us = <20>;
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exit-latency-us = <40>;
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min-residency-us = <80>;
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};
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CPU_NONRET_1_0: cpu-nonretentive-1-0 {
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compatible = "riscv,idle-state";
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riscv,sbi-suspend-param = <0x90000010>;
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entry-latency-us = <250>;
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exit-latency-us = <500>;
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min-residency-us = <950>;
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};
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CLUSTER_RET_1: cluster-retentive-1 {
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compatible = "riscv,idle-state";
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riscv,sbi-suspend-param = <0x11000010>;
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local-timer-stop;
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entry-latency-us = <50>;
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exit-latency-us = <100>;
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min-residency-us = <250>;
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wakeup-latency-us = <130>;
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};
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CLUSTER_NONRET_1: cluster-nonretentive-1 {
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compatible = "riscv,idle-state";
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riscv,sbi-suspend-param = <0x91000010>;
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local-timer-stop;
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entry-latency-us = <600>;
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exit-latency-us = <1100>;
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min-residency-us = <2700>;
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wakeup-latency-us = <1500>;
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};
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};
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};
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...
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@ -99,6 +99,12 @@ properties:
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- compatible
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- interrupt-controller
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cpu-idle-states:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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description: |
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List of phandles to idle state nodes supported
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by this hart (see ./idle-states.yaml).
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required:
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- riscv,isa
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- interrupt-controller
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