firewire: ohci: enable cycle timer fix on ALi and NEC controllers
Discussed in "read_cycle_timer backwards for sub-cycle 0000, 0001", http://thread.gmane.org/gmane.linux.kernel.firewire.devel/13704 Known bad controllers: ALi M5271, listed by lspci as M5253 [10b9:5253] NEC OrangeLink [1033:00cd] (rev 03) NEC uPD72874 [1033:00f2] (rev 01) VIA VT6306 [1106:3044] (rev 46) VIA VT6308P, listed by lspci as rev c0 Reported-by: Pieter Palmers <pieterp@joow.be> Reported-by: Håkan Johansson <f96hajo@chalmers.se> Reported-by: Clemens Ladisch <clemens@ladisch.de> Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
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@ -1817,13 +1817,14 @@ static u64 ohci_get_bus_time(struct fw_card *card)
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c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
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} else {
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/*
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* VIA controllers have two bugs when updating the iso cycle
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* timer register:
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* 1) When the lowest six bits are wrapping around to zero,
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* Some controllers exhibit one or more of the following bugs
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* when updating the iso cycle timer register:
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* - When the lowest six bits are wrapping around to zero,
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* a read that happens at the same time will return garbage
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* in the lowest ten bits.
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* 2) When the cycleOffset field wraps around to zero, the
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* - When the cycleOffset field wraps around to zero, the
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* cycleCount field is not incremented for about 60 ns.
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* - Occasionally, the entire register reads zero.
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*
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* To catch these, we read the register three times and ensure
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* that the difference between each two consecutive reads is
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@ -2542,7 +2543,9 @@ static int __devinit pci_probe(struct pci_dev *dev,
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#endif
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ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI;
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ohci->iso_cycle_timer_quirk = dev->vendor == PCI_VENDOR_ID_VIA;
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ohci->iso_cycle_timer_quirk = dev->vendor == PCI_VENDOR_ID_AL ||
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dev->vendor == PCI_VENDOR_ID_NEC ||
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dev->vendor == PCI_VENDOR_ID_VIA;
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ar_context_init(&ohci->ar_request_ctx, ohci,
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OHCI1394_AsReqRcvContextControlSet);
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