cpufreq: armada-37xx: Add AVS support
Armada 37xx supports Adaptive Voltage Scaling and thanks to this patch a voltage is associated to each load level. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
Gregory CLEMENT
Rafael J. Wysocki
Родитель
2851b90709
Коммит
1c3528232f
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@ -51,6 +51,16 @@
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#define ARMADA_37XX_DVFS_LOAD_2 2
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#define ARMADA_37XX_DVFS_LOAD_3 3
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/* AVS register set */
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#define ARMADA_37XX_AVS_CTL0 0x0
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#define ARMADA_37XX_AVS_ENABLE BIT(30)
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#define ARMADA_37XX_AVS_HIGH_VDD_LIMIT 16
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#define ARMADA_37XX_AVS_LOW_VDD_LIMIT 22
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#define ARMADA_37XX_AVS_VDD_MASK 0x3F
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#define ARMADA_37XX_AVS_CTL2 0x8
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#define ARMADA_37XX_AVS_LOW_VDD_EN BIT(6)
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#define ARMADA_37XX_AVS_VSET(x) (0x1C + 4 * (x))
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/*
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* On Armada 37xx the Power management manages 4 level of CPU load,
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* each level can be associated with a CPU clock source, a CPU
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@ -58,6 +68,17 @@
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*/
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#define LOAD_LEVEL_NR 4
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#define MIN_VOLT_MV 1000
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/* AVS value for the corresponding voltage (in mV) */
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static int avs_map[] = {
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747, 758, 770, 782, 793, 805, 817, 828, 840, 852, 863, 875, 887, 898,
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910, 922, 933, 945, 957, 968, 980, 992, 1003, 1015, 1027, 1038, 1050,
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1062, 1073, 1085, 1097, 1108, 1120, 1132, 1143, 1155, 1167, 1178, 1190,
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1202, 1213, 1225, 1237, 1248, 1260, 1272, 1283, 1295, 1307, 1318, 1330,
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1342
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};
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struct armada37xx_cpufreq_state {
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struct regmap *regmap;
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u32 nb_l0l1;
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@ -71,6 +92,7 @@ static struct armada37xx_cpufreq_state *armada37xx_cpufreq_state;
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struct armada_37xx_dvfs {
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u32 cpu_freq_max;
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u8 divider[LOAD_LEVEL_NR];
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u32 avs[LOAD_LEVEL_NR];
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};
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static struct armada_37xx_dvfs armada_37xx_dvfs[] = {
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@ -148,6 +170,128 @@ static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
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clk_set_parent(clk, parent);
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}
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/*
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* Find out the armada 37x supported AVS value whose voltage value is
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* the round-up closest to the target voltage value.
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*/
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static u32 armada_37xx_avs_val_match(int target_vm)
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{
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u32 avs;
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/* Find out the round-up closest supported voltage value */
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for (avs = 0; avs < ARRAY_SIZE(avs_map); avs++)
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if (avs_map[avs] >= target_vm)
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break;
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/*
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* If all supported voltages are smaller than target one,
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* choose the largest supported voltage
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*/
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if (avs == ARRAY_SIZE(avs_map))
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avs = ARRAY_SIZE(avs_map) - 1;
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return avs;
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}
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/*
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* For Armada 37xx soc, L0(VSET0) VDD AVS value is set to SVC revision
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* value or a default value when SVC is not supported.
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* - L0 can be read out from the register of AVS_CTRL_0 and L0 voltage
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* can be got from the mapping table of avs_map.
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* - L1 voltage should be about 100mv smaller than L0 voltage
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* - L2 & L3 voltage should be about 150mv smaller than L0 voltage.
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* This function calculates L1 & L2 & L3 AVS values dynamically based
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* on L0 voltage and fill all AVS values to the AVS value table.
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*/
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static void __init armada37xx_cpufreq_avs_configure(struct regmap *base,
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struct armada_37xx_dvfs *dvfs)
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{
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unsigned int target_vm;
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int load_level = 0;
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u32 l0_vdd_min;
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if (base == NULL)
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return;
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/* Get L0 VDD min value */
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regmap_read(base, ARMADA_37XX_AVS_CTL0, &l0_vdd_min);
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l0_vdd_min = (l0_vdd_min >> ARMADA_37XX_AVS_LOW_VDD_LIMIT) &
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ARMADA_37XX_AVS_VDD_MASK;
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if (l0_vdd_min >= ARRAY_SIZE(avs_map)) {
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pr_err("L0 VDD MIN %d is not correct.\n", l0_vdd_min);
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return;
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}
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dvfs->avs[0] = l0_vdd_min;
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if (avs_map[l0_vdd_min] <= MIN_VOLT_MV) {
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/*
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* If L0 voltage is smaller than 1000mv, then all VDD sets
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* use L0 voltage;
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*/
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u32 avs_min = armada_37xx_avs_val_match(MIN_VOLT_MV);
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for (load_level = 1; load_level < LOAD_LEVEL_NR; load_level++)
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dvfs->avs[load_level] = avs_min;
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return;
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}
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/*
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* L1 voltage is equal to L0 voltage - 100mv and it must be
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* larger than 1000mv
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*/
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target_vm = avs_map[l0_vdd_min] - 100;
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target_vm = target_vm > MIN_VOLT_MV ? target_vm : MIN_VOLT_MV;
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dvfs->avs[1] = armada_37xx_avs_val_match(target_vm);
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/*
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* L2 & L3 voltage is equal to L0 voltage - 150mv and it must
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* be larger than 1000mv
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*/
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target_vm = avs_map[l0_vdd_min] - 150;
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target_vm = target_vm > MIN_VOLT_MV ? target_vm : MIN_VOLT_MV;
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dvfs->avs[2] = dvfs->avs[3] = armada_37xx_avs_val_match(target_vm);
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}
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static void __init armada37xx_cpufreq_avs_setup(struct regmap *base,
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struct armada_37xx_dvfs *dvfs)
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{
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unsigned int avs_val = 0, freq;
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int load_level = 0;
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if (base == NULL)
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return;
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/* Disable AVS before the configuration */
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regmap_update_bits(base, ARMADA_37XX_AVS_CTL0,
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ARMADA_37XX_AVS_ENABLE, 0);
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/* Enable low voltage mode */
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regmap_update_bits(base, ARMADA_37XX_AVS_CTL2,
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ARMADA_37XX_AVS_LOW_VDD_EN,
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ARMADA_37XX_AVS_LOW_VDD_EN);
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for (load_level = 1; load_level < LOAD_LEVEL_NR; load_level++) {
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freq = dvfs->cpu_freq_max / dvfs->divider[load_level];
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avs_val = dvfs->avs[load_level];
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regmap_update_bits(base, ARMADA_37XX_AVS_VSET(load_level-1),
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ARMADA_37XX_AVS_VDD_MASK << ARMADA_37XX_AVS_HIGH_VDD_LIMIT |
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ARMADA_37XX_AVS_VDD_MASK << ARMADA_37XX_AVS_LOW_VDD_LIMIT,
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avs_val << ARMADA_37XX_AVS_HIGH_VDD_LIMIT |
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avs_val << ARMADA_37XX_AVS_LOW_VDD_LIMIT);
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}
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/* Enable AVS after the configuration */
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regmap_update_bits(base, ARMADA_37XX_AVS_CTL0,
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ARMADA_37XX_AVS_ENABLE,
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ARMADA_37XX_AVS_ENABLE);
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}
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static void armada37xx_cpufreq_disable_dvfs(struct regmap *base)
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{
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unsigned int reg = ARMADA_37XX_NB_DYN_MOD,
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@ -216,7 +360,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
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struct platform_device *pdev;
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unsigned long freq;
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unsigned int cur_frequency;
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struct regmap *nb_pm_base;
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struct regmap *nb_pm_base, *avs_base;
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struct device *cpu_dev;
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int load_lvl, ret;
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struct clk *clk;
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@ -227,6 +371,14 @@ static int __init armada37xx_cpufreq_driver_init(void)
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if (IS_ERR(nb_pm_base))
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return -ENODEV;
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avs_base =
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syscon_regmap_lookup_by_compatible("marvell,armada-3700-avs");
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/* if AVS is not present don't use it but still try to setup dvfs */
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if (IS_ERR(avs_base)) {
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pr_info("Syscon failed for Adapting Voltage Scaling: skip it\n");
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avs_base = NULL;
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}
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/* Before doing any configuration on the DVFS first, disable it */
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armada37xx_cpufreq_disable_dvfs(nb_pm_base);
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@ -270,16 +422,21 @@ static int __init armada37xx_cpufreq_driver_init(void)
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armada37xx_cpufreq_state->regmap = nb_pm_base;
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armada37xx_cpufreq_avs_configure(avs_base, dvfs);
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armada37xx_cpufreq_avs_setup(avs_base, dvfs);
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armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider);
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clk_put(clk);
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for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
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load_lvl++) {
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unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000;
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freq = cur_frequency / dvfs->divider[load_lvl];
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ret = dev_pm_opp_add(cpu_dev, freq, 0);
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ret = dev_pm_opp_add(cpu_dev, freq, u_volt);
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if (ret)
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goto remove_opp;
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}
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/* Now that everything is setup, enable the DVFS at hardware level */
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