Merge tag 'drm-intel-fixes-2017-08-09-1' of git://anongit.freedesktop.org/git/drm-intel into drm-fixes
drm/i915 fixes for v4.13-rc5 * tag 'drm-intel-fixes-2017-08-09-1' of git://anongit.freedesktop.org/git/drm-intel: drm/i915: fix backlight invert for non-zero minimum brightness drm/i915/shrinker: Wrap need_resched() inside preempt-disable drm/i915/perf: fix flex eu registers programming drm/i915: Fix out-of-bounds array access in bdw_load_gamma_lut drm/i915/gvt: Change the max length of mmio_reg_rw from 4 to 8 drm/i915/gvt: Initialize MMIO Block with HW state drm/i915/gvt: clean workload queue if error happened drm/i915/gvt: change resetting to resetting_eng
This commit is contained in:
Dave Airlie
Коммит
1c52a78e71
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@ -46,6 +46,8 @@
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#define same_context(a, b) (((a)->context_id == (b)->context_id) && \
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((a)->lrca == (b)->lrca))
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static void clean_workloads(struct intel_vgpu *vgpu, unsigned long engine_mask);
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static int context_switch_events[] = {
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[RCS] = RCS_AS_CONTEXT_SWITCH,
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[BCS] = BCS_AS_CONTEXT_SWITCH,
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@ -499,10 +501,10 @@ static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
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static int complete_execlist_workload(struct intel_vgpu_workload *workload)
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{
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struct intel_vgpu *vgpu = workload->vgpu;
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struct intel_vgpu_execlist *execlist =
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&vgpu->execlist[workload->ring_id];
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int ring_id = workload->ring_id;
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struct intel_vgpu_execlist *execlist = &vgpu->execlist[ring_id];
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struct intel_vgpu_workload *next_workload;
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struct list_head *next = workload_q_head(vgpu, workload->ring_id)->next;
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struct list_head *next = workload_q_head(vgpu, ring_id)->next;
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bool lite_restore = false;
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int ret;
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@ -512,10 +514,25 @@ static int complete_execlist_workload(struct intel_vgpu_workload *workload)
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release_shadow_batch_buffer(workload);
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release_shadow_wa_ctx(&workload->wa_ctx);
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if (workload->status || vgpu->resetting)
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if (workload->status || (vgpu->resetting_eng & ENGINE_MASK(ring_id))) {
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/* if workload->status is not successful means HW GPU
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* has occurred GPU hang or something wrong with i915/GVT,
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* and GVT won't inject context switch interrupt to guest.
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* So this error is a vGPU hang actually to the guest.
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* According to this we should emunlate a vGPU hang. If
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* there are pending workloads which are already submitted
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* from guest, we should clean them up like HW GPU does.
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*
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* if it is in middle of engine resetting, the pending
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* workloads won't be submitted to HW GPU and will be
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* cleaned up during the resetting process later, so doing
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* the workload clean up here doesn't have any impact.
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**/
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clean_workloads(vgpu, ENGINE_MASK(ring_id));
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goto out;
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}
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if (!list_empty(workload_q_head(vgpu, workload->ring_id))) {
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if (!list_empty(workload_q_head(vgpu, ring_id))) {
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struct execlist_ctx_descriptor_format *this_desc, *next_desc;
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next_workload = container_of(next,
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@ -72,11 +72,13 @@ static int expose_firmware_sysfs(struct intel_gvt *gvt)
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struct intel_gvt_device_info *info = &gvt->device_info;
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struct pci_dev *pdev = gvt->dev_priv->drm.pdev;
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struct intel_gvt_mmio_info *e;
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struct gvt_mmio_block *block = gvt->mmio.mmio_block;
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int num = gvt->mmio.num_mmio_block;
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struct gvt_firmware_header *h;
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void *firmware;
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void *p;
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unsigned long size, crc32_start;
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int i;
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int i, j;
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int ret;
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size = sizeof(*h) + info->mmio_size + info->cfg_space_size;
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@ -105,6 +107,13 @@ static int expose_firmware_sysfs(struct intel_gvt *gvt)
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hash_for_each(gvt->mmio.mmio_info_table, i, e, node)
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*(u32 *)(p + e->offset) = I915_READ_NOTRACE(_MMIO(e->offset));
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for (i = 0; i < num; i++, block++) {
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for (j = 0; j < block->size; j += 4)
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*(u32 *)(p + INTEL_GVT_MMIO_OFFSET(block->offset) + j) =
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I915_READ_NOTRACE(_MMIO(INTEL_GVT_MMIO_OFFSET(
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block->offset) + j));
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}
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memcpy(gvt->firmware.mmio, p, info->mmio_size);
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crc32_start = offsetof(struct gvt_firmware_header, crc32) + 4;
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@ -149,7 +149,7 @@ struct intel_vgpu {
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bool active;
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bool pv_notified;
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bool failsafe;
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bool resetting;
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unsigned int resetting_eng;
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void *sched_data;
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struct vgpu_sched_ctl sched_ctl;
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@ -195,6 +195,15 @@ struct intel_gvt_fence {
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unsigned long vgpu_allocated_fence_num;
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};
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/* Special MMIO blocks. */
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struct gvt_mmio_block {
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unsigned int device;
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i915_reg_t offset;
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unsigned int size;
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gvt_mmio_func read;
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gvt_mmio_func write;
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};
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#define INTEL_GVT_MMIO_HASH_BITS 11
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struct intel_gvt_mmio {
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@ -214,6 +223,9 @@ struct intel_gvt_mmio {
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/* This reg could be accessed by unaligned address */
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#define F_UNALIGN (1 << 6)
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struct gvt_mmio_block *mmio_block;
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unsigned int num_mmio_block;
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DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
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unsigned int num_tracked_mmio;
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};
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@ -2857,31 +2857,15 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
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return 0;
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}
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/* Special MMIO blocks. */
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static struct gvt_mmio_block {
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unsigned int device;
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i915_reg_t offset;
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unsigned int size;
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gvt_mmio_func read;
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gvt_mmio_func write;
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} gvt_mmio_blocks[] = {
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{D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
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{D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
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{D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
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pvinfo_mmio_read, pvinfo_mmio_write},
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{D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL},
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{D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL},
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{D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL},
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};
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static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
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unsigned int offset)
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{
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unsigned long device = intel_gvt_get_device_type(gvt);
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struct gvt_mmio_block *block = gvt_mmio_blocks;
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struct gvt_mmio_block *block = gvt->mmio.mmio_block;
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int num = gvt->mmio.num_mmio_block;
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int i;
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for (i = 0; i < ARRAY_SIZE(gvt_mmio_blocks); i++, block++) {
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for (i = 0; i < num; i++, block++) {
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if (!(device & block->device))
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continue;
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if (offset >= INTEL_GVT_MMIO_OFFSET(block->offset) &&
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@ -2912,6 +2896,17 @@ void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
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gvt->mmio.mmio_attribute = NULL;
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}
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/* Special MMIO blocks. */
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static struct gvt_mmio_block mmio_blocks[] = {
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{D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
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{D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
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{D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
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pvinfo_mmio_read, pvinfo_mmio_write},
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{D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL},
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{D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL},
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{D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL},
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};
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/**
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* intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
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* @gvt: GVT device
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@ -2951,6 +2946,9 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
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goto err;
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}
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gvt->mmio.mmio_block = mmio_blocks;
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gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
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gvt_dbg_mmio("traced %u virtual mmio registers\n",
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gvt->mmio.num_tracked_mmio);
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return 0;
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@ -3030,7 +3028,7 @@ int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
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gvt_mmio_func func;
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int ret;
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if (WARN_ON(bytes > 4))
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if (WARN_ON(bytes > 8))
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return -EINVAL;
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/*
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@ -432,7 +432,8 @@ static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
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i915_gem_request_put(fetch_and_zero(&workload->req));
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if (!workload->status && !vgpu->resetting) {
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if (!workload->status && !(vgpu->resetting_eng &
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ENGINE_MASK(ring_id))) {
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update_guest_context(workload);
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for_each_set_bit(event, workload->pending_events,
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@ -480,11 +480,13 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
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{
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struct intel_gvt *gvt = vgpu->gvt;
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struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
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unsigned int resetting_eng = dmlr ? ALL_ENGINES : engine_mask;
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gvt_dbg_core("------------------------------------------\n");
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gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
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vgpu->id, dmlr, engine_mask);
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vgpu->resetting = true;
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vgpu->resetting_eng = resetting_eng;
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intel_vgpu_stop_schedule(vgpu);
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/*
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@ -497,7 +499,7 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
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mutex_lock(&gvt->lock);
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}
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intel_vgpu_reset_execlist(vgpu, dmlr ? ALL_ENGINES : engine_mask);
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intel_vgpu_reset_execlist(vgpu, resetting_eng);
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/* full GPU reset or device model level reset */
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if (engine_mask == ALL_ENGINES || dmlr) {
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@ -520,7 +522,7 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
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}
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}
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vgpu->resetting = false;
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vgpu->resetting_eng = 0;
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gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
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gvt_dbg_core("------------------------------------------\n");
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}
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@ -43,16 +43,21 @@ static bool shrinker_lock(struct drm_i915_private *dev_priv, bool *unlock)
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return true;
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case MUTEX_TRYLOCK_FAILED:
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*unlock = false;
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preempt_disable();
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do {
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cpu_relax();
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if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
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case MUTEX_TRYLOCK_SUCCESS:
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*unlock = true;
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return true;
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break;
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}
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} while (!need_resched());
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preempt_enable();
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return *unlock;
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return false;
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case MUTEX_TRYLOCK_SUCCESS:
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*unlock = true;
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return true;
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}
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BUG();
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@ -1601,11 +1601,11 @@ static int gen8_emit_oa_config(struct drm_i915_gem_request *req)
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u32 *cs;
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int i;
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cs = intel_ring_begin(req, n_flex_regs * 2 + 4);
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cs = intel_ring_begin(req, ARRAY_SIZE(flex_mmio) * 2 + 4);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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*cs++ = MI_LOAD_REGISTER_IMM(n_flex_regs + 1);
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*cs++ = MI_LOAD_REGISTER_IMM(ARRAY_SIZE(flex_mmio) + 1);
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*cs++ = i915_mmio_reg_offset(GEN8_OACTXCONTROL);
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*cs++ = (dev_priv->perf.oa.period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
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@ -398,6 +398,7 @@ static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
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}
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/* Program the max register to clamp values > 1.0. */
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i = lut_size - 1;
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I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
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drm_color_lut_extract(lut[i].red, 16));
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I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
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@ -469,7 +469,7 @@ static u32 intel_panel_compute_brightness(struct intel_connector *connector,
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if (i915.invert_brightness > 0 ||
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dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
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return panel->backlight.max - val;
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return panel->backlight.max - val + panel->backlight.min;
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}
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return val;
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