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Collected changes for existing Rockchip boards 

- convert to new clock driver
 - bring structure in line with recent rk3288 comments
   (no soc-nodes, using phandles when adding changes, sorted by address)
 - i2c, board-pmic and pwm nodes nodes
 - sd card slot and ir receiver on radxa rock
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Merge tag 'v3.17-rockchip-rk3xxx-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

Merge "ARM: dts: changes for existing rockchip boards" from Heiko Stuebner:

Collected changes for existing Rockchip boards
- convert to new clock driver
- bring structure in line with recent rk3288 comments
  (no soc-nodes, using phandles when adding changes, sorted by address)
- i2c, board-pmic and pwm nodes nodes
- sd card slot and ir receiver on radxa rock

* tag 'v3.17-rockchip-rk3xxx-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rk3188-radxarock: add GPIO IR receiver node
  ARM: dts: rockchip: add pwm nodes
  ARM: dts: rockchip: add both clocks to uart nodes
  ARM: dts: rk3188-radxarock: enable sd-card slot
  ARM: dts: add i2c and regulator nodes to rk3188-radxarock
  ARM: dts: rockchip: add tps65910 regulator for bqcurie2
  ARM: dts: add rk3066 and rk3188 i2c device nodes and pinctrl settings
  ARM: dts: rockchip: oder nodes by register address
  ARM: dts: rockchip: remove address from pinctrl nodes
  ARM: dts: uses handles to reference nodes for changes
  ARM: dts: rockchip: add handles for shared nodes that don't have one yet
  ARM: dts: rockchip: remove soc subnodes
  arm: dts: rockchip: remove obsolete clock gate definitions
  ARM: dts: rockchip: move oscillator input clock into main dtsi
  ARM: dts: rockchip: add cru nodes and update device clocks to use it

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2014-07-28 14:16:24 +02:00
Родитель b99cfa66e1 08567053f5
Коммит 1c607f0af0
7 изменённых файлов: 1194 добавлений и 1161 удалений
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214
arch/arm/boot/dts/rk3066a-bqcurie2.dts
Просмотреть файл

@ -24,87 +24,167 @@
reg = <0x60000000 0x40000000>;
};
soc {
uart0: serial@10124000 {
status = "okay";
vcc_sd0: fixed-regulator {
compatible = "regulator-fixed";
regulator-name = "sdmmc-supply";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {
gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */
linux,code = <116>;
label = "GPIO Key Power";
linux,input-type = <1>;
gpio-key,wakeup = <1>;
debounce-interval = <100>;
};
uart1: serial@10126000 {
status = "okay";
button@1 {
gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */
linux,code = <104>;
label = "GPIO Key Vol-";
linux,input-type = <1>;
gpio-key,wakeup = <0>;
debounce-interval = <100>;
};
/* VOL+ comes somehow thru the ADC */
};
};
uart2: serial@20064000 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
status = "okay";
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
uart3: serial@20068000 {
status = "okay";
};
tps: tps@2d {
reg = <0x2d>;
vcc_sd0: fixed-regulator {
compatible = "regulator-fixed";
regulator-name = "sdmmc-supply";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
startup-delay-us = <100000>;
};
interrupt-parent = <&gpio6>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
dwmmc@10214000 { /* sdmmc */
num-slots = <1>;
status = "okay";
vcc5-supply = <&vcc_io>;
vcc6-supply = <&vcc_io>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
vmmc-supply = <&vcc_sd0>;
slot@0 {
reg = <0>;
bus-width = <4>;
disable-wp;
regulators {
vcc_rtc: regulator@0 {
regulator-name = "vcc_rtc";
regulator-always-on;
};
};
dwmmc@10218000 { /* wifi */
num-slots = <1>;
status = "okay";
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
slot@0 {
reg = <0>;
bus-width = <4>;
disable-wp;
vcc_io: regulator@1 {
regulator-name = "vcc_io";
regulator-always-on;
};
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
vdd_arm: regulator@2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
button@0 {
gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */
linux,code = <116>;
label = "GPIO Key Power";
linux,input-type = <1>;
gpio-key,wakeup = <1>;
debounce-interval = <100>;
vcc_ddr: regulator@3 {
regulator-name = "vcc_ddr";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
button@1 {
gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */
linux,code = <104>;
label = "GPIO Key Vol-";
linux,input-type = <1>;
gpio-key,wakeup = <0>;
debounce-interval = <100>;
vcc18_cif: regulator@5 {
regulator-name = "vcc18_cif";
regulator-always-on;
};
vdd_11: regulator@6 {
regulator-name = "vdd_11";
regulator-always-on;
};
vcc_25: regulator@7 {
regulator-name = "vcc_25";
regulator-always-on;
};
vcc_18: regulator@8 {
regulator-name = "vcc_18";
regulator-always-on;
};
vcc25_hdmi: regulator@9 {
regulator-name = "vcc25_hdmi";
regulator-always-on;
};
vcca_33: regulator@10 {
regulator-name = "vcca_33";
regulator-always-on;
};
vcc_tp: regulator@11 {
regulator-name = "vcc_tp";
regulator-always-on;
};
vcc28_cif: regulator@12 {
regulator-name = "vcc28_cif";
regulator-always-on;
};
/* VOL+ comes somehow thru the ADC */
};
};
};
/* must be included after &tps gets defined */
#include "tps65910.dtsi"
&mmc0 { /* sdmmc */
num-slots = <1>;
status = "okay";
vmmc-supply = <&vcc_sd0>;
slot@0 {
reg = <0>;
bus-width = <4>;
disable-wp;
};
};
&mmc1 { /* wifi */
num-slots = <1>;
status = "okay";
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
slot@0 {
reg = <0>;
bus-width = <4>;
disable-wp;
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};

299
arch/arm/boot/dts/rk3066a-clocks.dtsi
Просмотреть файл

@ -1,299 +0,0 @@
/*
* Copyright (c) 2013 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/ {
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/*
* This is a dummy clock, to be used as placeholder on
* other mux clocks when a specific parent clock is not
* yet implemented. It should be dropped when the driver
* is complete.
*/
dummy: dummy {
compatible = "fixed-clock";
clock-frequency = <0>;
#clock-cells = <0>;
};
xin24m: xin24m {
compatible = "fixed-clock";
clock-frequency = <24000000>;
#clock-cells = <0>;
};
dummy48m: dummy48m {
compatible = "fixed-clock";
clock-frequency = <48000000>;
#clock-cells = <0>;
};
dummy150m: dummy150m {
compatible = "fixed-clock";
clock-frequency = <150000000>;
#clock-cells = <0>;
};
clk_gates0: gate-clk@200000d0 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000d0 0x4>;
clocks = <&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"gate_core_periph", "gate_cpu_gpll",
"gate_ddrphy", "gate_aclk_cpu",
"gate_hclk_cpu", "gate_pclk_cpu",
"gate_atclk_cpu", "gate_i2s0",
"gate_i2s0_frac", "gate_i2s1",
"gate_i2s1_frac", "gate_i2s2",
"gate_i2s2_frac", "gate_spdif",
"gate_spdif_frac", "gate_testclk";
#clock-cells = <1>;
};
clk_gates1: gate-clk@200000d4 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000d4 0x4>;
clocks = <&xin24m>, <&xin24m>,
<&xin24m>, <&dummy>,
<&dummy>, <&xin24m>,
<&xin24m>, <&dummy>,
<&xin24m>, <&dummy>,
<&xin24m>, <&dummy>,
<&xin24m>, <&dummy>,
<&xin24m>, <&dummy>;
clock-output-names =
"gate_timer0", "gate_timer1",
"gate_timer2", "gate_jtag",
"gate_aclk_lcdc1_src", "gate_otgphy0",
"gate_otgphy1", "gate_ddr_gpll",
"gate_uart0", "gate_frac_uart0",
"gate_uart1", "gate_frac_uart1",
"gate_uart2", "gate_frac_uart2",
"gate_uart3", "gate_frac_uart3";
#clock-cells = <1>;
};
clk_gates2: gate-clk@200000d8 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000d8 0x4>;
clocks = <&clk_gates2 1>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&clk_gates2 3>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy48m>,
<&dummy>, <&dummy48m>,
<&dummy>, <&dummy>;
clock-output-names =
"gate_periph_src", "gate_aclk_periph",
"gate_hclk_periph", "gate_pclk_periph",
"gate_smc", "gate_mac",
"gate_hsadc", "gate_hsadc_frac",
"gate_saradc", "gate_spi0",
"gate_spi1", "gate_mmc0",
"gate_mac_lbtest", "gate_mmc1",
"gate_emmc", "gate_tsadc";
#clock-cells = <1>;
};
clk_gates3: gate-clk@200000dc {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000dc 0x4>;
clocks = <&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"gate_aclk_lcdc0_src", "gate_dclk_lcdc0",
"gate_dclk_lcdc1", "gate_pclkin_cif0",
"gate_pclkin_cif1", "reserved",
"reserved", "gate_cif0_out",
"gate_cif1_out", "gate_aclk_vepu",
"gate_hclk_vepu", "gate_aclk_vdpu",
"gate_hclk_vdpu", "gate_gpu_src",
"reserved", "gate_xin27m";
#clock-cells = <1>;
};
clk_gates4: gate-clk@200000e0 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000e0 0x4>;
clocks = <&clk_gates2 2>, <&clk_gates2 3>,
<&clk_gates2 1>, <&clk_gates2 1>,
<&clk_gates2 1>, <&clk_gates2 2>,
<&clk_gates2 2>, <&clk_gates2 2>,
<&clk_gates0 4>, <&clk_gates0 4>,
<&clk_gates0 3>, <&clk_gates0 3>,
<&clk_gates0 3>, <&clk_gates2 3>,
<&clk_gates0 4>;
clock-output-names =
"gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix",
"gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix",
"gate_aclk_pei_niu", "gate_hclk_usb_peri",
"gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri",
"gate_hclk_cpubus", "gate_hclk_ahb2apb",
"gate_aclk_strc_sys", "gate_aclk_l2mem_con",
"gate_aclk_intmem", "gate_pclk_tsadc",
"gate_hclk_hdmi";
#clock-cells = <1>;
};
clk_gates5: gate-clk@200000e4 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000e4 0x4>;
clocks = <&clk_gates0 3>, <&clk_gates2 1>,
<&clk_gates0 5>, <&clk_gates0 5>,
<&clk_gates0 5>, <&clk_gates0 5>,
<&clk_gates0 4>, <&clk_gates0 5>,
<&clk_gates2 1>, <&clk_gates2 2>,
<&clk_gates2 2>, <&clk_gates2 2>,
<&clk_gates2 2>, <&clk_gates4 5>,
<&clk_gates4 5>, <&dummy>;
clock-output-names =
"gate_aclk_dmac1", "gate_aclk_dmac2",
"gate_pclk_efuse", "gate_pclk_tzpc",
"gate_pclk_grf", "gate_pclk_pmu",
"gate_hclk_rom", "gate_pclk_ddrupctl",
"gate_aclk_smc", "gate_hclk_nandc",
"gate_hclk_mmc0", "gate_hclk_mmc1",
"gate_hclk_emmc", "gate_hclk_otg0",
"gate_hclk_otg1", "gate_aclk_gpu";
#clock-cells = <1>;
};
clk_gates6: gate-clk@200000e8 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000e8 0x4>;
clocks = <&clk_gates3 0>, <&clk_gates0 4>,
<&clk_gates0 4>, <&clk_gates1 4>,
<&clk_gates0 4>, <&clk_gates3 0>,
<&clk_gates0 4>, <&clk_gates1 4>,
<&clk_gates3 0>, <&clk_gates0 4>,
<&clk_gates0 4>, <&clk_gates1 4>,
<&clk_gates0 4>, <&clk_gates3 0>,
<&dummy>, <&dummy>;
clock-output-names =
"gate_aclk_lcdc0", "gate_hclk_lcdc0",
"gate_hclk_lcdc1", "gate_aclk_lcdc1",
"gate_hclk_cif0", "gate_aclk_cif0",
"gate_hclk_cif1", "gate_aclk_cif1",
"gate_aclk_ipp", "gate_hclk_ipp",
"gate_hclk_rga", "gate_aclk_rga",
"gate_hclk_vio_bus", "gate_aclk_vio0",
"gate_aclk_vcodec", "gate_shclk_vio_h2h";
#clock-cells = <1>;
};
clk_gates7: gate-clk@200000ec {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000ec 0x4>;
clocks = <&clk_gates2 2>, <&clk_gates0 4>,
<&clk_gates0 4>, <&clk_gates0 4>,
<&clk_gates0 4>, <&clk_gates2 2>,
<&clk_gates2 2>, <&clk_gates0 5>,
<&clk_gates0 5>, <&clk_gates0 5>,
<&clk_gates0 5>, <&clk_gates2 3>,
<&clk_gates2 3>, <&clk_gates2 3>,
<&clk_gates2 3>, <&clk_gates2 3>;
clock-output-names =
"gate_hclk_emac", "gate_hclk_spdif",
"gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch",
"gate_hclk_i2s_8ch", "gate_hclk_hsadc",
"gate_hclk_pidf", "gate_pclk_timer0",
"gate_pclk_timer1", "gate_pclk_timer2",
"gate_pclk_pwm01", "gate_pclk_pwm23",
"gate_pclk_spi0", "gate_pclk_spi1",
"gate_pclk_saradc", "gate_pclk_wdt";
#clock-cells = <1>;
};
clk_gates8: gate-clk@200000f0 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000f0 0x4>;
clocks = <&clk_gates0 5>, <&clk_gates0 5>,
<&clk_gates2 3>, <&clk_gates2 3>,
<&clk_gates0 5>, <&clk_gates0 5>,
<&clk_gates2 3>, <&clk_gates2 3>,
<&clk_gates2 3>, <&clk_gates0 5>,
<&clk_gates0 5>, <&clk_gates0 5>,
<&clk_gates2 3>, <&clk_gates2 3>,
<&dummy>, <&clk_gates0 5>;
clock-output-names =
"gate_pclk_uart0", "gate_pclk_uart1",
"gate_pclk_uart2", "gate_pclk_uart3",
"gate_pclk_i2c0", "gate_pclk_i2c1",
"gate_pclk_i2c2", "gate_pclk_i2c3",
"gate_pclk_i2c4", "gate_pclk_gpio0",
"gate_pclk_gpio1", "gate_pclk_gpio2",
"gate_pclk_gpio3", "gate_pclk_gpio4",
"reserved", "gate_pclk_gpio6";
#clock-cells = <1>;
};
clk_gates9: gate-clk@200000f4 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000f4 0x4>;
clocks = <&dummy>, <&clk_gates0 5>,
<&dummy>, <&dummy>,
<&dummy>, <&clk_gates1 4>,
<&clk_gates0 5>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>;
clock-output-names =
"gate_clk_core_dbg", "gate_pclk_dbg",
"gate_clk_trace", "gate_atclk",
"gate_clk_l2c", "gate_aclk_vio1",
"gate_pclk_publ", "gate_aclk_intmem0",
"gate_aclk_intmem1", "gate_aclk_intmem2",
"gate_aclk_intmem3";
#clock-cells = <1>;
};
};
};

531
arch/arm/boot/dts/rk3066a.dtsi
Просмотреть файл

@ -15,8 +15,8 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3066a-cru.h>
#include "rk3xxx.dtsi"
#include "rk3066a-clocks.dtsi"
/ {
compatible = "rockchip,rk3066a";
@ -40,247 +40,388 @@
};
};
soc {
timer@20038000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x20038000 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates1 0>, <&clk_gates7 7>;
clock-names = "timer", "pclk";
sram: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x10080000 0x10000>;
smp-sram@0 {
compatible = "rockchip,rk3066-smp-sram";
reg = <0x0 0x50>;
};
};
cru: clock-controller@20000000 {
compatible = "rockchip,rk3066a-cru";
reg = <0x20000000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
timer@2000e000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x2000e000 0x100>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
clock-names = "timer", "pclk";
};
timer@20038000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x20038000 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
clock-names = "timer", "pclk";
};
timer@2003a000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x2003a000 0x100>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
clock-names = "timer", "pclk";
};
pinctrl: pinctrl {
compatible = "rockchip,rk3066a-pinctrl";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio0@20034000 {
compatible = "rockchip,gpio-bank";
reg = <0x20034000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
timer@2003a000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x2003a000 0x100>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates1 1>, <&clk_gates7 8>;
clock-names = "timer", "pclk";
gpio1: gpio1@2003c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003c000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
timer@2000e000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x2000e000 0x100>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates1 2>, <&clk_gates7 9>;
clock-names = "timer", "pclk";
gpio2: gpio2@2003e000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003e000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
sram: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x10080000 0x10000>;
gpio3: gpio3@20080000 {
compatible = "rockchip,gpio-bank";
reg = <0x20080000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>;
smp-sram@0 {
compatible = "rockchip,rk3066-smp-sram";
reg = <0x0 0x50>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio4@20084000 {
compatible = "rockchip,gpio-bank";
reg = <0x20084000 0x100>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio6: gpio6@2000a000 {
compatible = "rockchip,gpio-bank";
reg = <0x2000a000 0x100>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO6>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pcfg_pull_default: pcfg_pull_default {
bias-pull-pin-default;
};
pcfg_pull_none: pcfg_pull_none {
bias-disable;
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
};
};
pinctrl@20008000 {
compatible = "rockchip,rk3066a-pinctrl";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
};
};
gpio0: gpio0@20034000 {
compatible = "rockchip,gpio-bank";
reg = <0x20034000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 9>;
i2c2 {
i2c2_xfer: i2c2-xfer {
rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
};
};
gpio-controller;
#gpio-cells = <2>;
i2c3 {
i2c3_xfer: i2c3-xfer {
rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
<RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
};
};
interrupt-controller;
#interrupt-cells = <2>;
i2c4 {
i2c4_xfer: i2c4-xfer {
rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
};
};
pwm0 {
pwm0_out: pwm0-out {
rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_out: pwm1-out {
rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
};
};
pwm2 {
pwm2_out: pwm2-out {
rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
};
};
pwm3 {
pwm3_out: pwm3-out {
rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
};
gpio1: gpio1@2003c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003c000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 10>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
uart0_cts: uart0-cts {
rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
};
gpio2: gpio2@2003e000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003e000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 11>;
uart0_rts: uart0-rts {
rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
};
};
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
};
gpio3: gpio3@20080000 {
compatible = "rockchip,gpio-bank";
reg = <0x20080000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 12>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
uart1_cts: uart1-cts {
rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
};
gpio4: gpio4@20084000 {
compatible = "rockchip,gpio-bank";
reg = <0x20084000 0x100>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 13>;
uart1_rts: uart1-rts {
rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
};
};
gpio-controller;
#gpio-cells = <2>;
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
};
/* no rts / cts for uart2 */
};
interrupt-controller;
#interrupt-cells = <2>;
uart3 {
uart3_xfer: uart3-xfer {
rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
};
gpio6: gpio6@2000a000 {
compatible = "rockchip,gpio-bank";
reg = <0x2000a000 0x100>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 15>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
uart3_cts: uart3-cts {
rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
};
pcfg_pull_default: pcfg_pull_default {
bias-pull-pin-default;
uart3_rts: uart3-rts {
rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
};
};
sd0 {
sd0_clk: sd0-clk {
rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
};
pcfg_pull_none: pcfg_pull_none {
bias-disable;
sd0_cmd: sd0-cmd {
rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
};
uart0_cts: uart0-cts {
rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
};
uart0_rts: uart0-rts {
rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
};
sd0_cd: sd0-cd {
rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
};
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
};
uart1_cts: uart1-cts {
rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
};
uart1_rts: uart1-rts {
rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
};
sd0_wp: sd0-wp {
rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
};
/* no rts / cts for uart2 */
sd0_bus1: sd0-bus-width1 {
rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
};
uart3 {
uart3_xfer: uart3-xfer {
rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
};
sd0_bus4: sd0-bus-width4 {
rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
};
};
uart3_cts: uart3-cts {
rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
};
uart3_rts: uart3-rts {
rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
};
sd1 {
sd1_clk: sd1-clk {
rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
};
sd0 {
sd0_clk: sd0-clk {
rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
};
sd0_cmd: sd0-cmd {
rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
};
sd0_cd: sd0-cd {
rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
};
sd0_wp: sd0-wp {
rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
};
sd0_bus1: sd0-bus-width1 {
rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
};
sd0_bus4: sd0-bus-width4 {
rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
};
sd1_cmd: sd1-cmd {
rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
};
sd1 {
sd1_clk: sd1-clk {
rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
};
sd1_cd: sd1-cd {
rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
};
sd1_cmd: sd1-cmd {
rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
};
sd1_wp: sd1-wp {
rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
};
sd1_cd: sd1-cd {
rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
};
sd1_bus1: sd1-bus-width1 {
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
};
sd1_wp: sd1-wp {
rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
};
sd1_bus1: sd1-bus-width1 {
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
};
sd1_bus4: sd1-bus-width4 {
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
};
sd1_bus4: sd1-bus-width4 {
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
};
};
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_xfer>;
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_xfer>;
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_xfer>;
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_xfer>;
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
};
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_out>;
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pwm1_out>;
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pwm2_out>;
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pwm3_out>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_xfer>;
};

289
arch/arm/boot/dts/rk3188-clocks.dtsi
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@ -1,289 +0,0 @@
/*
* Copyright (c) 2013 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/ {
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/*
* This is a dummy clock, to be used as placeholder on
* other mux clocks when a specific parent clock is not
* yet implemented. It should be dropped when the driver
* is complete.
*/
dummy: dummy {
compatible = "fixed-clock";
clock-frequency = <0>;
#clock-cells = <0>;
};
xin24m: xin24m {
compatible = "fixed-clock";
clock-frequency = <24000000>;
#clock-cells = <0>;
};
dummy48m: dummy48m {
compatible = "fixed-clock";
clock-frequency = <48000000>;
#clock-cells = <0>;
};
dummy150m: dummy150m {
compatible = "fixed-clock";
clock-frequency = <150000000>;
#clock-cells = <0>;
};
clk_gates0: gate-clk@200000d0 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000d0 0x4>;
clocks = <&dummy150m>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"gate_core_periph", "gate_cpu_gpll",
"gate_ddrphy", "gate_aclk_cpu",
"gate_hclk_cpu", "gate_pclk_cpu",
"gate_atclk_cpu", "gate_aclk_core",
"reserved", "gate_i2s0",
"gate_i2s0_frac", "reserved",
"reserved", "gate_spdif",
"gate_spdif_frac", "gate_testclk";
#clock-cells = <1>;
};
clk_gates1: gate-clk@200000d4 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000d4 0x4>;
clocks = <&xin24m>, <&xin24m>,
<&xin24m>, <&dummy>,
<&dummy>, <&xin24m>,
<&xin24m>, <&dummy>,
<&xin24m>, <&dummy>,
<&xin24m>, <&dummy>,
<&xin24m>, <&dummy>,
<&xin24m>, <&dummy>;
clock-output-names =
"gate_timer0", "gate_timer1",
"gate_timer3", "gate_jtag",
"gate_aclk_lcdc1_src", "gate_otgphy0",
"gate_otgphy1", "gate_ddr_gpll",
"gate_uart0", "gate_frac_uart0",
"gate_uart1", "gate_frac_uart1",
"gate_uart2", "gate_frac_uart2",
"gate_uart3", "gate_frac_uart3";
#clock-cells = <1>;
};
clk_gates2: gate-clk@200000d8 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000d8 0x4>;
clocks = <&clk_gates2 1>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&clk_gates2 3>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy48m>,
<&dummy>, <&dummy48m>,
<&dummy>, <&dummy>;
clock-output-names =
"gate_periph_src", "gate_aclk_periph",
"gate_hclk_periph", "gate_pclk_periph",
"gate_smc", "gate_mac",
"gate_hsadc", "gate_hsadc_frac",
"gate_saradc", "gate_spi0",
"gate_spi1", "gate_mmc0",
"gate_mac_lbtest", "gate_mmc1",
"gate_emmc", "reserved";
#clock-cells = <1>;
};
clk_gates3: gate-clk@200000dc {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000dc 0x4>;
clocks = <&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&xin24m>, <&xin24m>,
<&dummy>, <&dummy>,
<&xin24m>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&xin24m>, <&dummy>;
clock-output-names =
"gate_aclk_lcdc0_src", "gate_dclk_lcdc0",
"gate_dclk_lcdc1", "gate_pclkin_cif0",
"gate_timer2", "gate_timer4",
"gate_hsicphy", "gate_cif0_out",
"gate_timer5", "gate_aclk_vepu",
"gate_hclk_vepu", "gate_aclk_vdpu",
"gate_hclk_vdpu", "reserved",
"gate_timer6", "gate_aclk_gpu_src";
#clock-cells = <1>;
};
clk_gates4: gate-clk@200000e0 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000e0 0x4>;
clocks = <&clk_gates2 2>, <&clk_gates2 3>,
<&clk_gates2 1>, <&clk_gates2 1>,
<&clk_gates2 1>, <&clk_gates2 2>,
<&clk_gates2 2>, <&clk_gates2 2>,
<&clk_gates0 4>, <&clk_gates0 4>,
<&clk_gates0 3>, <&dummy>,
<&clk_gates0 3>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix",
"gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix",
"gate_aclk_pei_niu", "gate_hclk_usb_peri",
"gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri",
"gate_hclk_cpubus", "gate_hclk_ahb2apb",
"gate_aclk_strc_sys", "reserved",
"gate_aclk_intmem", "reserved",
"gate_hclk_imem1", "gate_hclk_imem0";
#clock-cells = <1>;
};
clk_gates5: gate-clk@200000e4 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000e4 0x4>;
clocks = <&clk_gates0 3>, <&clk_gates2 1>,
<&clk_gates0 5>, <&clk_gates0 5>,
<&clk_gates0 5>, <&clk_gates0 5>,
<&clk_gates0 4>, <&clk_gates0 5>,
<&clk_gates2 1>, <&clk_gates2 2>,
<&clk_gates2 2>, <&clk_gates2 2>,
<&clk_gates2 2>, <&clk_gates4 5>;
clock-output-names =
"gate_aclk_dmac1", "gate_aclk_dmac2",
"gate_pclk_efuse", "gate_pclk_tzpc",
"gate_pclk_grf", "gate_pclk_pmu",
"gate_hclk_rom", "gate_pclk_ddrupctl",
"gate_aclk_smc", "gate_hclk_nandc",
"gate_hclk_mmc0", "gate_hclk_mmc1",
"gate_hclk_emmc", "gate_hclk_otg0";
#clock-cells = <1>;
};
clk_gates6: gate-clk@200000e8 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000e8 0x4>;
clocks = <&clk_gates3 0>, <&clk_gates0 4>,
<&clk_gates0 4>, <&clk_gates1 4>,
<&clk_gates0 4>, <&clk_gates3 0>,
<&dummy>, <&dummy>,
<&clk_gates3 0>, <&clk_gates0 4>,
<&clk_gates0 4>, <&clk_gates1 4>,
<&clk_gates0 4>, <&clk_gates3 0>;
clock-output-names =
"gate_aclk_lcdc0", "gate_hclk_lcdc0",
"gate_hclk_lcdc1", "gate_aclk_lcdc1",
"gate_hclk_cif0", "gate_aclk_cif0",
"reserved", "reserved",
"gate_aclk_ipp", "gate_hclk_ipp",
"gate_hclk_rga", "gate_aclk_rga",
"gate_hclk_vio_bus", "gate_aclk_vio0";
#clock-cells = <1>;
};
clk_gates7: gate-clk@200000ec {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000ec 0x4>;
clocks = <&clk_gates2 2>, <&clk_gates0 4>,
<&clk_gates0 4>, <&dummy>,
<&dummy>, <&clk_gates2 2>,
<&clk_gates2 2>, <&clk_gates0 5>,
<&dummy>, <&clk_gates0 5>,
<&clk_gates0 5>, <&clk_gates2 3>,
<&clk_gates2 3>, <&clk_gates2 3>,
<&clk_gates2 3>, <&clk_gates2 3>;
clock-output-names =
"gate_hclk_emac", "gate_hclk_spdif",
"gate_hclk_i2s0_2ch", "gate_hclk_otg1",
"gate_hclk_hsic", "gate_hclk_hsadc",
"gate_hclk_pidf", "gate_pclk_timer0",
"reserved", "gate_pclk_timer2",
"gate_pclk_pwm01", "gate_pclk_pwm23",
"gate_pclk_spi0", "gate_pclk_spi1",
"gate_pclk_saradc", "gate_pclk_wdt";
#clock-cells = <1>;
};
clk_gates8: gate-clk@200000f0 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000f0 0x4>;
clocks = <&clk_gates0 5>, <&clk_gates0 5>,
<&clk_gates2 3>, <&clk_gates2 3>,
<&clk_gates0 5>, <&clk_gates0 5>,
<&clk_gates2 3>, <&clk_gates2 3>,
<&clk_gates2 3>, <&clk_gates0 5>,
<&clk_gates0 5>, <&clk_gates0 5>,
<&clk_gates2 3>, <&dummy>;
clock-output-names =
"gate_pclk_uart0", "gate_pclk_uart1",
"gate_pclk_uart2", "gate_pclk_uart3",
"gate_pclk_i2c0", "gate_pclk_i2c1",
"gate_pclk_i2c2", "gate_pclk_i2c3",
"gate_pclk_i2c4", "gate_pclk_gpio0",
"gate_pclk_gpio1", "gate_pclk_gpio2",
"gate_pclk_gpio3", "gate_aclk_gps";
#clock-cells = <1>;
};
clk_gates9: gate-clk@200000f4 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000f4 0x4>;
clocks = <&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"gate_clk_core_dbg", "gate_pclk_dbg",
"gate_clk_trace", "gate_atclk",
"gate_clk_l2c", "gate_aclk_vio1",
"gate_pclk_publ", "gate_aclk_gpu";
#clock-cells = <1>;
};
};
};

238
arch/arm/boot/dts/rk3188-radxarock.dts
Просмотреть файл

@ -23,59 +23,203 @@
reg = <0x60000000 0x80000000>;
};
soc {
uart0: serial@10124000 {
status = "okay";
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {
gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
linux,code = <116>;
label = "GPIO Key Power";
linux,input-type = <1>;
gpio-key,wakeup = <1>;
debounce-interval = <100>;
};
};
gpio-leds {
compatible = "gpio-leds";
green {
gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
default-state = "off";
};
uart1: serial@10126000 {
status = "okay";
yellow {
gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
default-state = "off";
};
uart2: serial@20064000 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
status = "okay";
sleep {
gpios = <&gpio0 15 0>;
default-state = "off";
};
};
uart3: serial@20068000 {
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {
gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
linux,code = <116>;
label = "GPIO Key Power";
linux,input-type = <1>;
gpio-key,wakeup = <1>;
debounce-interval = <100>;
};
};
gpio-leds {
compatible = "gpio-leds";
green {
gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
default-state = "off";
};
yellow {
gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
default-state = "off";
};
sleep {
gpios = <&gpio0 15 0>;
default-state = "off";
};
};
ir_recv: gpio-ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio0 10 1>;
pinctrl-names = "default";
pinctrl-0 = <&ir_recv_pin>;
};
vcc_sd0: sdmmc-regulator {
compatible = "regulator-fixed";
regulator-name = "sdmmc-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 1 GPIO_ACTIVE_LOW>;
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
act8846: act8846@5a {
compatible = "active-semi,act8846";
reg = <0x5a>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&act8846_dvs0_ctl>;
regulators {
vcc_ddr: REG1 {
regulator-name = "VCC_DDR";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vdd_log: REG2 {
regulator-name = "VDD_LOG";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
vdd_arm: REG3 {
regulator-name = "VDD_ARM";
regulator-min-microvolt = <875000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
};
vcc_io: REG4 {
regulator-name = "VCC_IO";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_10: REG5 {
regulator-name = "VDD_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
vdd_hdmi: REG6 {
regulator-name = "VDD_HDMI";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
vcc18: REG7 {
regulator-name = "VCC_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vcca_33: REG8 {
regulator-name = "VCCA_33";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vcc_rmii: REG9 {
regulator-name = "VCC_RMII";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vccio_wl: REG10 {
regulator-name = "VCCIO_WL";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vcc_18: REG11 {
regulator-name = "VCC18_IO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vcc28: REG12 {
regulator-name = "VCC_28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
};
};
};
&mmc0 {
num-slots = <1>;
status = "okay";
vmmc-supply = <&vcc_sd0>;
slot@0 {
reg = <0>;
bus-width = <4>;
disable-wp;
};
};
&pinctrl {
pcfg_output_low: pcfg-output-low {
output-low;
};
act8846 {
act8846_dvs0_ctl: act8846-dvs0-ctl {
rockchip,pins = <RK_GPIO3 27 RK_FUNC_GPIO &pcfg_output_low>;
};
};
ir-receiver {
ir_recv_pin: ir-recv-pin {
rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
status = "okay";
};
&uart3 {
status = "okay";
};

470
arch/arm/boot/dts/rk3188.dtsi
Просмотреть файл

@ -15,8 +15,8 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3188-cru.h>
#include "rk3xxx.dtsi"
#include "rk3188-clocks.dtsi"
/ {
compatible = "rockchip,rk3188";
@ -52,215 +52,351 @@
};
};
soc {
global-timer@1013c200 {
interrupts = <GIC_PPI 11 0xf04>;
sram: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x8000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x10080000 0x8000>;
smp-sram@0 {
compatible = "rockchip,rk3066-smp-sram";
reg = <0x0 0x50>;
};
};
cru: clock-controller@20000000 {
compatible = "rockchip,rk3188-cru";
reg = <0x20000000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pinctrl: pinctrl {
compatible = "rockchip,rk3188-pinctrl";
rockchip,grf = <&grf>;
rockchip,pmu = <&pmu>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio0@0x2000a000 {
compatible = "rockchip,rk3188-gpio-bank0";
reg = <0x2000a000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
local-timer@1013c600 {
interrupts = <GIC_PPI 13 0xf04>;
gpio1: gpio1@0x2003c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003c000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
sram: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x8000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x10080000 0x8000>;
gpio2: gpio2@2003e000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003e000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>;
smp-sram@0 {
compatible = "rockchip,rk3066-smp-sram";
reg = <0x0 0x50>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio3@20080000 {
compatible = "rockchip,gpio-bank";
reg = <0x20080000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pcfg_pull_up: pcfg_pull_up {
bias-pull-up;
};
pcfg_pull_down: pcfg_pull_down {
bias-pull-down;
};
pcfg_pull_none: pcfg_pull_none {
bias-disable;
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
};
};
pinctrl@20008000 {
compatible = "rockchip,rk3188-pinctrl";
rockchip,grf = <&grf>;
rockchip,pmu = <&pmu>;
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
};
};
#address-cells = <1>;
#size-cells = <1>;
ranges;
i2c2 {
i2c2_xfer: i2c2-xfer {
rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
};
};
gpio0: gpio0@0x2000a000 {
compatible = "rockchip,rk3188-gpio-bank0";
reg = <0x2000a000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 9>;
i2c3 {
i2c3_xfer: i2c3-xfer {
rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
<RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
};
};
gpio-controller;
#gpio-cells = <2>;
i2c4 {
i2c4_xfer: i2c4-xfer {
rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
};
};
interrupt-controller;
#interrupt-cells = <2>;
pwm0 {
pwm0_out: pwm0-out {
rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_out: pwm1-out {
rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
};
};
pwm2 {
pwm2_out: pwm2-out {
rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
};
};
pwm3 {
pwm3_out: pwm3-out {
rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
};
gpio1: gpio1@0x2003c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003c000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 10>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
uart0_cts: uart0-cts {
rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
};
gpio2: gpio2@2003e000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003e000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 11>;
uart0_rts: uart0-rts {
rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
};
};
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
};
gpio3: gpio3@20080000 {
compatible = "rockchip,gpio-bank";
reg = <0x20080000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 12>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
uart1_cts: uart1-cts {
rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
};
pcfg_pull_up: pcfg_pull_up {
bias-pull-up;
uart1_rts: uart1-rts {
rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
};
/* no rts / cts for uart2 */
};
uart3 {
uart3_xfer: uart3-xfer {
rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
};
pcfg_pull_down: pcfg_pull_down {
bias-pull-down;
uart3_cts: uart3-cts {
rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
};
pcfg_pull_none: pcfg_pull_none {
bias-disable;
uart3_rts: uart3-rts {
rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
};
};
sd0 {
sd0_clk: sd0-clk {
rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
};
uart0_rts: uart0-rts {
rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
};
sd0_cmd: sd0-cmd {
rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
};
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
};
uart1_cts: uart1-cts {
rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
};
uart1_rts: uart1-rts {
rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
};
sd0_cd: sd0-cd {
rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
};
/* no rts / cts for uart2 */
sd0_wp: sd0-wp {
rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
};
uart3 {
uart3_xfer: uart3-xfer {
rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
};
uart3_cts: uart3-cts {
rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
};
uart3_rts: uart3-rts {
rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
};
sd0_pwr: sd0-pwr {
rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
};
sd0 {
sd0_clk: sd0-clk {
rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
};
sd0_cmd: sd0-cmd {
rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
};
sd0_cd: sd0-cd {
rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
};
sd0_wp: sd0-wp {
rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
};
sd0_pwr: sd0-pwr {
rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
};
sd0_bus1: sd0-bus-width1 {
rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
};
sd0_bus4: sd0-bus-width4 {
rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
};
sd0_bus1: sd0-bus-width1 {
rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
};
sd1 {
sd1_clk: sd1-clk {
rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
};
sd0_bus4: sd0-bus-width4 {
rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
};
};
sd1_cmd: sd1-cmd {
rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
};
sd1 {
sd1_clk: sd1-clk {
rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
};
sd1_cd: sd1-cd {
rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
};
sd1_cmd: sd1-cmd {
rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
};
sd1_wp: sd1-wp {
rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
};
sd1_cd: sd1-cd {
rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
};
sd1_bus1: sd1-bus-width1 {
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
};
sd1_wp: sd1-wp {
rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
};
sd1_bus4: sd1-bus-width4 {
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
};
sd1_bus1: sd1-bus-width1 {
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
};
sd1_bus4: sd1-bus-width4 {
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
};
};
};
};
&global_timer {
interrupts = <GIC_PPI 11 0xf04>;
};
&local_timer {
interrupts = <GIC_PPI 13 0xf04>;
};
&i2c0 {
compatible = "rockchip,rk3188-i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
};
&i2c1 {
compatible = "rockchip,rk3188-i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_xfer>;
};
&i2c2 {
compatible = "rockchip,rk3188-i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c2_xfer>;
};
&i2c3 {
compatible = "rockchip,rk3188-i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c3_xfer>;
};
&i2c4 {
compatible = "rockchip,rk3188-i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c4_xfer>;
};
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_out>;
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pwm1_out>;
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pwm2_out>;
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pwm3_out>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_xfer>;
};

314
arch/arm/boot/dts/rk3xxx.dtsi
Просмотреть файл

@ -20,120 +20,240 @@
/ {
interrupt-parent = <&gic>;
soc {
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
};
xin24m: oscillator {
compatible = "fixed-clock";
clock-frequency = <24000000>;
#clock-cells = <0>;
clock-output-names = "xin24m";
};
L2: l2-cache-controller@10138000 {
compatible = "arm,pl310-cache";
reg = <0x10138000 0x1000>;
cache-unified;
cache-level = <2>;
};
scu@1013c000 {
compatible = "arm,cortex-a9-scu";
reg = <0x1013c000 0x100>;
};
global_timer: global-timer@1013c200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x1013c200 0x20>;
interrupts = <GIC_PPI 11 0x304>;
clocks = <&cru CORE_PERI>;
};
local_timer: local-timer@1013c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x1013c600 0x20>;
interrupts = <GIC_PPI 13 0x304>;
clocks = <&cru CORE_PERI>;
};
gic: interrupt-controller@1013d000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x1013d000 0x1000>,
<0x1013c100 0x0100>;
};
uart0: serial@10124000 {
compatible = "snps,dw-apb-uart";
reg = <0x10124000 0x400>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
status = "disabled";
};
uart1: serial@10126000 {
compatible = "snps,dw-apb-uart";
reg = <0x10126000 0x400>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
status = "disabled";
};
mmc0: dwmmc@10214000 {
compatible = "rockchip,rk2928-dw-mshc";
reg = <0x10214000 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
#size-cells = <0>;
scu@1013c000 {
compatible = "arm,cortex-a9-scu";
reg = <0x1013c000 0x100>;
};
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
clock-names = "biu", "ciu";
pmu: pmu@20004000 {
compatible = "rockchip,rk3066-pmu", "syscon";
reg = <0x20004000 0x100>;
};
status = "disabled";
};
grf: grf@20008000 {
compatible = "syscon";
reg = <0x20008000 0x200>;
};
mmc1: dwmmc@10218000 {
compatible = "rockchip,rk2928-dw-mshc";
reg = <0x10218000 0x1000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
gic: interrupt-controller@1013d000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x1013d000 0x1000>,
<0x1013c100 0x0100>;
};
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
clock-names = "biu", "ciu";
L2: l2-cache-controller@10138000 {
compatible = "arm,pl310-cache";
reg = <0x10138000 0x1000>;
cache-unified;
cache-level = <2>;
};
status = "disabled";
};
global-timer@1013c200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x1013c200 0x20>;
interrupts = <GIC_PPI 11 0x304>;
clocks = <&dummy150m>;
};
pmu: pmu@20004000 {
compatible = "rockchip,rk3066-pmu", "syscon";
reg = <0x20004000 0x100>;
};
local-timer@1013c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x1013c600 0x20>;
interrupts = <GIC_PPI 13 0x304>;
clocks = <&dummy150m>;
};
grf: grf@20008000 {
compatible = "syscon";
reg = <0x20008000 0x200>;
};
uart0: serial@10124000 {
compatible = "snps,dw-apb-uart";
reg = <0x10124000 0x400>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
clocks = <&clk_gates1 8>;
status = "disabled";
};
i2c0: i2c@2002d000 {
compatible = "rockchip,rk3066-i2c";
reg = <0x2002d000 0x1000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
uart1: serial@10126000 {
compatible = "snps,dw-apb-uart";
reg = <0x10126000 0x400>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
clocks = <&clk_gates1 10>;
status = "disabled";
};
rockchip,grf = <&grf>;
rockchip,bus-index = <0>;
uart2: serial@20064000 {
compatible = "snps,dw-apb-uart";
reg = <0x20064000 0x400>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
clocks = <&clk_gates1 12>;
status = "disabled";
};
clock-names = "i2c";
clocks = <&cru PCLK_I2C0>;
uart3: serial@20068000 {
compatible = "snps,dw-apb-uart";
reg = <0x20068000 0x400>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
clocks = <&clk_gates1 14>;
status = "disabled";
};
status = "disabled";
};
dwmmc@10214000 {
compatible = "rockchip,rk2928-dw-mshc";
reg = <0x10214000 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
i2c1: i2c@2002f000 {
compatible = "rockchip,rk3066-i2c";
reg = <0x2002f000 0x1000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk_gates5 10>, <&clk_gates2 11>;
clock-names = "biu", "ciu";
rockchip,grf = <&grf>;
status = "disabled";
};
clocks = <&cru PCLK_I2C1>;
clock-names = "i2c";
dwmmc@10218000 {
compatible = "rockchip,rk2928-dw-mshc";
reg = <0x10218000 0x1000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
clocks = <&clk_gates5 11>, <&clk_gates2 13>;
clock-names = "biu", "ciu";
pwm0: pwm@20030000 {
compatible = "rockchip,rk2928-pwm";
reg = <0x20030000 0x10>;
#pwm-cells = <2>;
clocks = <&cru PCLK_PWM01>;
status = "disabled";
};
status = "disabled";
};
pwm1: pwm@20030010 {
compatible = "rockchip,rk2928-pwm";
reg = <0x20030010 0x10>;
#pwm-cells = <2>;
clocks = <&cru PCLK_PWM01>;
status = "disabled";
};
pwm2: pwm@20050020 {
compatible = "rockchip,rk2928-pwm";
reg = <0x20050020 0x10>;
#pwm-cells = <2>;
clocks = <&cru PCLK_PWM23>;
status = "disabled";
};
pwm3: pwm@20050030 {
compatible = "rockchip,rk2928-pwm";
reg = <0x20050030 0x10>;
#pwm-cells = <2>;
clocks = <&cru PCLK_PWM23>;
status = "disabled";
};
i2c2: i2c@20056000 {
compatible = "rockchip,rk3066-i2c";
reg = <0x20056000 0x1000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
rockchip,grf = <&grf>;
clocks = <&cru PCLK_I2C2>;
clock-names = "i2c";
status = "disabled";
};
i2c3: i2c@2005a000 {
compatible = "rockchip,rk3066-i2c";
reg = <0x2005a000 0x1000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
rockchip,grf = <&grf>;
clocks = <&cru PCLK_I2C3>;
clock-names = "i2c";
status = "disabled";
};
i2c4: i2c@2005e000 {
compatible = "rockchip,rk3066-i2c";
reg = <0x2005e000 0x1000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
rockchip,grf = <&grf>;
clocks = <&cru PCLK_I2C4>;
clock-names = "i2c";
status = "disabled";
};
uart2: serial@20064000 {
compatible = "snps,dw-apb-uart";
reg = <0x20064000 0x400>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
status = "disabled";
};
uart3: serial@20068000 {
compatible = "snps,dw-apb-uart";
reg = <0x20068000 0x400>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
status = "disabled";
};
};