arm64/cpufeatures: Introduce ESR_ELx_SYS64_ISS_RT()
Extracting target register from ESR.ISS encoding has already been required at multiple instances. Just make it a macro definition and replace all the existing use cases. Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -187,6 +187,8 @@
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#define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \
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ESR_ELx_SYS64_ISS_DIR_MASK)
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#define ESR_ELx_SYS64_ISS_RT(esr) \
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(((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
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/*
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* User space cache operations have the following sysreg encoding
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* in System instructions.
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@ -335,7 +335,7 @@ static inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)
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static inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)
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{
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u32 esr = kvm_vcpu_get_hsr(vcpu);
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return (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
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return ESR_ELx_SYS64_ISS_RT(esr);
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}
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static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
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@ -438,7 +438,7 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
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static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
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{
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unsigned long address;
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int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
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int rt = ESR_ELx_SYS64_ISS_RT(esr);
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int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
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int ret = 0;
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@ -473,7 +473,7 @@ static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
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static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)
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{
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int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
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int rt = ESR_ELx_SYS64_ISS_RT(esr);
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unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);
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pt_regs_write_reg(regs, rt, val);
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@ -483,7 +483,7 @@ static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)
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static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
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{
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int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
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int rt = ESR_ELx_SYS64_ISS_RT(esr);
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pt_regs_write_reg(regs, rt, arch_counter_get_cntvct());
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arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
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@ -491,7 +491,7 @@ static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
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static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
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{
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int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
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int rt = ESR_ELx_SYS64_ISS_RT(esr);
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pt_regs_write_reg(regs, rt, arch_timer_get_rate());
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arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
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