Revert "drm/msm/dpu: add support for clk and bw scaling for display"
This is causing multiple armv7 missing do_div() errors, so lets drop it
for now.
This reverts commit 04d9044f6c.
Cc: Kalyan Thota <kalyan_t@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Rob Clark
Родитель
d9e19d7966
Коммит
1cb2c4a2c8
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@ -29,73 +29,6 @@ enum dpu_perf_mode {
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DPU_PERF_MODE_MAX
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};
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/**
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* @_dpu_core_perf_calc_bw() - to calculate BW per crtc
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* @kms - pointer to the dpu_kms
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* @crtc - pointer to a crtc
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* Return: returns aggregated BW for all planes in crtc.
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*/
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static u64 _dpu_core_perf_calc_bw(struct dpu_kms *kms,
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struct drm_crtc *crtc)
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{
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struct drm_plane *plane;
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struct dpu_plane_state *pstate;
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u64 crtc_plane_bw = 0;
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u32 bw_factor;
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drm_atomic_crtc_for_each_plane(plane, crtc) {
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pstate = to_dpu_plane_state(plane->state);
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if (!pstate)
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continue;
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crtc_plane_bw += pstate->plane_fetch_bw;
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}
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bw_factor = kms->catalog->perf.bw_inefficiency_factor;
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if (bw_factor)
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crtc_plane_bw = mult_frac(crtc_plane_bw, bw_factor, 100);
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return crtc_plane_bw;
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}
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/**
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* _dpu_core_perf_calc_clk() - to calculate clock per crtc
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* @kms - pointer to the dpu_kms
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* @crtc - pointer to a crtc
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* @state - pointer to a crtc state
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* Return: returns max clk for all planes in crtc.
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*/
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static u64 _dpu_core_perf_calc_clk(struct dpu_kms *kms,
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struct drm_crtc *crtc, struct drm_crtc_state *state)
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{
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struct drm_plane *plane;
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struct dpu_plane_state *pstate;
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struct drm_display_mode *mode;
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u64 crtc_clk;
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u32 clk_factor;
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mode = &state->adjusted_mode;
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crtc_clk = mode->vtotal * mode->hdisplay * drm_mode_vrefresh(mode);
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drm_atomic_crtc_for_each_plane(plane, crtc) {
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pstate = to_dpu_plane_state(plane->state);
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if (!pstate)
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continue;
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crtc_clk = max(pstate->plane_clk, crtc_clk);
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}
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clk_factor = kms->catalog->perf.clk_inefficiency_factor;
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if (clk_factor)
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crtc_clk = mult_frac(crtc_clk, clk_factor, 100);
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return crtc_clk;
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}
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static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
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{
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struct msm_drm_private *priv;
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@ -118,7 +51,12 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
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dpu_cstate = to_dpu_crtc_state(state);
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memset(perf, 0, sizeof(struct dpu_core_perf_params));
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if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
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if (!dpu_cstate->bw_control) {
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perf->bw_ctl = kms->catalog->perf.max_bw_high *
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1000ULL;
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perf->max_per_pipe_ib = perf->bw_ctl;
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perf->core_clk_rate = kms->perf.max_core_clk_rate;
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} else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
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perf->bw_ctl = 0;
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perf->max_per_pipe_ib = 0;
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perf->core_clk_rate = 0;
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@ -126,10 +64,6 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
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perf->bw_ctl = kms->perf.fix_core_ab_vote;
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perf->max_per_pipe_ib = kms->perf.fix_core_ib_vote;
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perf->core_clk_rate = kms->perf.fix_core_clk_rate;
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} else {
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perf->bw_ctl = _dpu_core_perf_calc_bw(kms, crtc);
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perf->max_per_pipe_ib = kms->catalog->perf.min_dram_ib;
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perf->core_clk_rate = _dpu_core_perf_calc_clk(kms, crtc, state);
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}
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DPU_DEBUG(
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@ -181,7 +115,11 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
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DPU_DEBUG("crtc:%d bw:%llu ctrl:%d\n",
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tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl,
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tmp_cstate->bw_control);
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/*
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* For bw check only use the bw if the
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* atomic property has been already set
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*/
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if (tmp_cstate->bw_control)
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bw_sum_of_intfs += tmp_cstate->new_perf.bw_ctl;
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}
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@ -193,7 +131,9 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
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DPU_DEBUG("final threshold bw limit = %d\n", threshold);
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if (!threshold) {
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if (!dpu_cstate->bw_control) {
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DPU_DEBUG("bypass bandwidth check\n");
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} else if (!threshold) {
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DPU_ERROR("no bandwidth limits specified\n");
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return -E2BIG;
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} else if (bw > threshold) {
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@ -214,8 +154,7 @@ static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms,
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= dpu_crtc_get_client_type(crtc);
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struct drm_crtc *tmp_crtc;
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struct dpu_crtc_state *dpu_cstate;
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int i, ret = 0;
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u64 avg_bw;
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int ret = 0;
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drm_for_each_crtc(tmp_crtc, crtc->dev) {
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if (tmp_crtc->enabled &&
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@ -226,21 +165,10 @@ static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms,
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perf.max_per_pipe_ib = max(perf.max_per_pipe_ib,
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dpu_cstate->new_perf.max_per_pipe_ib);
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perf.bw_ctl += dpu_cstate->new_perf.bw_ctl;
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DPU_DEBUG("crtc=%d bw=%llu paths:%d\n",
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tmp_crtc->base.id,
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dpu_cstate->new_perf.bw_ctl, kms->num_paths);
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DPU_DEBUG("crtc=%d bw=%llu\n", tmp_crtc->base.id,
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dpu_cstate->new_perf.bw_ctl);
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}
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}
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avg_bw = kms->num_paths ?
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perf.bw_ctl / kms->num_paths : 0;
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for (i = 0; i < kms->num_paths; i++)
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icc_set_bw(kms->path[i],
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Bps_to_icc(avg_bw), (perf.max_per_pipe_ib));
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return ret;
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}
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@ -541,8 +541,7 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
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.max_bw_high = 6800000,
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.min_core_ib = 2400000,
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.min_llcc_ib = 800000,
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.min_dram_ib = 1600000,
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.min_prefill_lines = 24,
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.min_dram_ib = 800000,
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.danger_lut_tbl = {0xff, 0xffff, 0x0},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(sc7180_qos_linear),
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@ -559,8 +558,6 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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.clk_inefficiency_factor = 105,
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.bw_inefficiency_factor = 120,
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};
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/*************************************************************
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@ -651,8 +651,6 @@ struct dpu_perf_cdp_cfg {
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* @downscaling_prefill_lines downscaling latency in lines
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* @amortizable_theshold minimum y position for traffic shaping prefill
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* @min_prefill_lines minimum pipeline latency in lines
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* @clk_inefficiency_factor DPU src clock inefficiency factor
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* @bw_inefficiency_factor DPU axi bus bw inefficiency factor
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* @safe_lut_tbl: LUT tables for safe signals
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* @danger_lut_tbl: LUT tables for danger signals
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* @qos_lut_tbl: LUT tables for QoS signals
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@ -677,8 +675,6 @@ struct dpu_perf_cfg {
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u32 downscaling_prefill_lines;
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u32 amortizable_threshold;
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u32 min_prefill_lines;
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u32 clk_inefficiency_factor;
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u32 bw_inefficiency_factor;
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u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
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u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
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struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
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@ -303,28 +303,6 @@ static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms)
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return 0;
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}
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static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms)
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{
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struct icc_path *path0;
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struct icc_path *path1;
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struct drm_device *dev = dpu_kms->dev;
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path0 = of_icc_get(dev->dev, "mdp0-mem");
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path1 = of_icc_get(dev->dev, "mdp1-mem");
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if (IS_ERR_OR_NULL(path0))
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return PTR_ERR_OR_ZERO(path0);
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dpu_kms->path[0] = path0;
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dpu_kms->num_paths = 1;
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if (!IS_ERR_OR_NULL(path1)) {
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dpu_kms->path[1] = path1;
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dpu_kms->num_paths++;
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}
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return 0;
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}
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static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
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{
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return dpu_crtc_vblank(crtc, true);
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@ -994,9 +972,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
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dpu_vbif_init_memtypes(dpu_kms);
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if (of_device_is_compatible(dev->dev->of_node, "qcom,sc7180-mdss"))
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dpu_kms_parse_data_bus_icc_path(dpu_kms);
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pm_runtime_put_sync(&dpu_kms->pdev->dev);
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return 0;
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@ -1102,7 +1077,7 @@ static int dpu_dev_remove(struct platform_device *pdev)
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static int __maybe_unused dpu_runtime_suspend(struct device *dev)
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{
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int i, rc = -1;
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int rc = -1;
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struct platform_device *pdev = to_platform_device(dev);
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struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
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struct dss_module_power *mp = &dpu_kms->mp;
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@ -1111,9 +1086,6 @@ static int __maybe_unused dpu_runtime_suspend(struct device *dev)
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if (rc)
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DPU_ERROR("clock disable failed rc:%d\n", rc);
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for (i = 0; i < dpu_kms->num_paths; i++)
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icc_set_bw(dpu_kms->path[i], 0, 0);
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return rc;
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}
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@ -1125,15 +1097,8 @@ static int __maybe_unused dpu_runtime_resume(struct device *dev)
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struct drm_encoder *encoder;
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struct drm_device *ddev;
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struct dss_module_power *mp = &dpu_kms->mp;
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int i;
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ddev = dpu_kms->dev;
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/* Min vote of BW is required before turning on AXI clk */
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for (i = 0; i < dpu_kms->num_paths; i++)
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icc_set_bw(dpu_kms->path[i], 0,
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dpu_kms->catalog->perf.min_dram_ib);
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rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
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if (rc) {
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DPU_ERROR("clock enable failed rc:%d\n", rc);
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|
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@ -8,8 +8,6 @@
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#ifndef __DPU_KMS_H__
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#define __DPU_KMS_H__
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#include <linux/interconnect.h>
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#include <drm/drm_drv.h>
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#include "msm_drv.h"
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@ -139,8 +137,6 @@ struct dpu_kms {
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* when disabled.
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*/
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atomic_t bandwidth_ref;
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struct icc_path *path[2];
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u32 num_paths;
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};
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struct vsync_info {
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@ -8,6 +8,7 @@
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|||
#include <linux/irqdesc.h>
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#include <linux/irqchip/chained_irq.h>
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#include "dpu_kms.h"
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#include <linux/interconnect.h>
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#define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)
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@ -314,11 +315,9 @@ int dpu_mdss_init(struct drm_device *dev)
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}
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dpu_mdss->mmio_len = resource_size(res);
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|
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if (!of_device_is_compatible(dev->dev->of_node, "qcom,sc7180-mdss")) {
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ret = dpu_mdss_parse_data_bus_icc_path(dev, dpu_mdss);
|
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if (ret)
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return ret;
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||||
}
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ret = dpu_mdss_parse_data_bus_icc_path(dev, dpu_mdss);
|
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if (ret)
|
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return ret;
|
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|
||||
mp = &dpu_mdss->mp;
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ret = msm_dss_parse_clock(pdev, mp);
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|
|
|
|||
|
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@ -131,84 +131,6 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
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|||
return to_dpu_kms(priv->kms);
|
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}
|
||||
|
||||
/**
|
||||
* _dpu_plane_calc_bw - calculate bandwidth required for a plane
|
||||
* @Plane: Pointer to drm plane.
|
||||
* Result: Updates calculated bandwidth in the plane state.
|
||||
* BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest)
|
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* Prefill BW Equation: line src bytes * line_time
|
||||
*/
|
||||
static void _dpu_plane_calc_bw(struct drm_plane *plane,
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struct drm_framebuffer *fb)
|
||||
{
|
||||
struct dpu_plane *pdpu = to_dpu_plane(plane);
|
||||
struct dpu_plane_state *pstate;
|
||||
struct drm_display_mode *mode;
|
||||
const struct dpu_format *fmt = NULL;
|
||||
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
|
||||
int src_width, src_height, dst_height, fps;
|
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u64 plane_prefill_bw;
|
||||
u64 plane_bw;
|
||||
u32 hw_latency_lines;
|
||||
u32 scale_factor;
|
||||
int vbp, vpw;
|
||||
|
||||
pstate = to_dpu_plane_state(plane->state);
|
||||
mode = &plane->state->crtc->mode;
|
||||
|
||||
fmt = dpu_get_dpu_format_ext(fb->format->format, fb->modifier);
|
||||
|
||||
src_width = drm_rect_width(&pdpu->pipe_cfg.src_rect);
|
||||
src_height = drm_rect_height(&pdpu->pipe_cfg.src_rect);
|
||||
dst_height = drm_rect_height(&pdpu->pipe_cfg.dst_rect);
|
||||
fps = drm_mode_vrefresh(mode);
|
||||
vbp = mode->vtotal - mode->vsync_end;
|
||||
vpw = mode->vsync_end - mode->vsync_start;
|
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hw_latency_lines = dpu_kms->catalog->perf.min_prefill_lines;
|
||||
scale_factor = src_height > dst_height ?
|
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mult_frac(src_height, 1, dst_height) : 1;
|
||||
|
||||
plane_bw =
|
||||
src_width * mode->vtotal * fps * fmt->bpp * scale_factor;
|
||||
|
||||
plane_prefill_bw =
|
||||
src_width * hw_latency_lines * fps * fmt->bpp * scale_factor;
|
||||
|
||||
plane_prefill_bw = mult_frac(plane_prefill_bw, mode->vtotal, (vbp+vpw));
|
||||
|
||||
pstate->plane_fetch_bw = max(plane_bw, plane_prefill_bw);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* _dpu_plane_calc_clk - calculate clock required for a plane
|
||||
* @Plane: Pointer to drm plane.
|
||||
* Result: Updates calculated clock in the plane state.
|
||||
* Clock equation: dst_w * v_total * fps * (src_h / dst_h)
|
||||
*/
|
||||
static void _dpu_plane_calc_clk(struct drm_plane *plane)
|
||||
{
|
||||
struct dpu_plane *pdpu = to_dpu_plane(plane);
|
||||
struct dpu_plane_state *pstate;
|
||||
struct drm_display_mode *mode;
|
||||
int dst_width, src_height, dst_height, fps;
|
||||
|
||||
pstate = to_dpu_plane_state(plane->state);
|
||||
mode = &plane->state->crtc->mode;
|
||||
|
||||
src_height = drm_rect_height(&pdpu->pipe_cfg.src_rect);
|
||||
dst_width = drm_rect_width(&pdpu->pipe_cfg.dst_rect);
|
||||
dst_height = drm_rect_height(&pdpu->pipe_cfg.dst_rect);
|
||||
fps = drm_mode_vrefresh(mode);
|
||||
|
||||
pstate->plane_clk =
|
||||
dst_width * mode->vtotal * fps;
|
||||
|
||||
if (src_height > dst_height)
|
||||
pstate->plane_clk = mult_frac(pstate->plane_clk,
|
||||
src_height, dst_height);
|
||||
}
|
||||
|
||||
/**
|
||||
* _dpu_plane_calc_fill_level - calculate fill level of the given source format
|
||||
* @plane: Pointer to drm plane
|
||||
|
|
@ -1180,10 +1102,6 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
|
|||
}
|
||||
|
||||
_dpu_plane_set_qos_remap(plane);
|
||||
|
||||
_dpu_plane_calc_bw(plane, fb);
|
||||
|
||||
_dpu_plane_calc_clk(plane);
|
||||
}
|
||||
|
||||
static void _dpu_plane_atomic_disable(struct drm_plane *plane)
|
||||
|
|
|
|||
|
|
@ -25,8 +25,6 @@
|
|||
* @scaler3_cfg: configuration data for scaler3
|
||||
* @pixel_ext: configuration data for pixel extensions
|
||||
* @cdp_cfg: CDP configuration
|
||||
* @plane_fetch_bw: calculated BW per plane
|
||||
* @plane_clk: calculated clk per plane
|
||||
*/
|
||||
struct dpu_plane_state {
|
||||
struct drm_plane_state base;
|
||||
|
|
@ -41,8 +39,6 @@ struct dpu_plane_state {
|
|||
struct dpu_hw_pixel_ext pixel_ext;
|
||||
|
||||
struct dpu_hw_pipe_cdp_cfg cdp_cfg;
|
||||
u64 plane_fetch_bw;
|
||||
u64 plane_clk;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
|||
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