ARM: at91: remove legacy IRQ driver and related code
Remove irc.c and associated header file. The related code was idendified by the CONFIG_OLD_IRQ_AT91 option that was removed previously. It has been spotted by following coccinelle semantic match: @rule1@ expression E; statement S; @@ ( - if (IS_ENABLED(CONFIG_OLD_IRQ_AT91)) S | - if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && E) S ) Cc: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
This commit is contained in:
Nicolas Ferre
Родитель
ff78a189b0
Коммит
1ccdde057b
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@ -4,7 +4,6 @@
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obj-y := gpio.o setup.o sysirq_mask.o
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obj-$(CONFIG_OLD_IRQ_AT91) += irq.o
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obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
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# CPU-specific support
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@ -1,99 +0,0 @@
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/*
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* arch/arm/mach-at91/include/mach/at91_aic.h
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* Advanced Interrupt Controller (AIC) - System peripherals registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_AIC_H
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#define AT91_AIC_H
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#ifndef __ASSEMBLY__
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extern void __iomem *at91_aic_base;
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#define at91_aic_read(field) \
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__raw_readl(at91_aic_base + field)
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#define at91_aic_write(field, value) \
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__raw_writel(value, at91_aic_base + field)
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#else
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.extern at91_aic_base
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#endif
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/* Number of irq lines managed by AIC */
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#define NR_AIC_IRQS 32
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#define NR_AIC5_IRQS 128
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#define AT91_AIC5_SSR 0x0 /* Source Select Register [AIC5] */
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#define AT91_AIC5_INTSEL_MSK (0x7f << 0) /* Interrupt Line Selection Mask */
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#define AT91_AIC_IRQ_MIN_PRIORITY 0
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#define AT91_AIC_IRQ_MAX_PRIORITY 7
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#define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */
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#define AT91_AIC5_SMR 0x4 /* Source Mode Register [AIC5] */
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#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
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#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
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#define AT91_AIC_SRCTYPE_LOW (0 << 5)
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#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
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#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
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#define AT91_AIC_SRCTYPE_RISING (3 << 5)
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#define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
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#define AT91_AIC5_SVR 0x8 /* Source Vector Register [AIC5] */
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#define AT91_AIC_IVR 0x100 /* Interrupt Vector Register */
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#define AT91_AIC5_IVR 0x10 /* Interrupt Vector Register [AIC5] */
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#define AT91_AIC_FVR 0x104 /* Fast Interrupt Vector Register */
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#define AT91_AIC5_FVR 0x14 /* Fast Interrupt Vector Register [AIC5] */
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#define AT91_AIC_ISR 0x108 /* Interrupt Status Register */
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#define AT91_AIC5_ISR 0x18 /* Interrupt Status Register [AIC5] */
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#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
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#define AT91_AIC_IPR 0x10c /* Interrupt Pending Register */
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#define AT91_AIC5_IPR0 0x20 /* Interrupt Pending Register 0 [AIC5] */
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#define AT91_AIC5_IPR1 0x24 /* Interrupt Pending Register 1 [AIC5] */
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#define AT91_AIC5_IPR2 0x28 /* Interrupt Pending Register 2 [AIC5] */
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#define AT91_AIC5_IPR3 0x2c /* Interrupt Pending Register 3 [AIC5] */
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#define AT91_AIC_IMR 0x110 /* Interrupt Mask Register */
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#define AT91_AIC5_IMR 0x30 /* Interrupt Mask Register [AIC5] */
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#define AT91_AIC_CISR 0x114 /* Core Interrupt Status Register */
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#define AT91_AIC5_CISR 0x34 /* Core Interrupt Status Register [AIC5] */
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#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
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#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
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#define AT91_AIC_IECR 0x120 /* Interrupt Enable Command Register */
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#define AT91_AIC5_IECR 0x40 /* Interrupt Enable Command Register [AIC5] */
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#define AT91_AIC_IDCR 0x124 /* Interrupt Disable Command Register */
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#define AT91_AIC5_IDCR 0x44 /* Interrupt Disable Command Register [AIC5] */
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#define AT91_AIC_ICCR 0x128 /* Interrupt Clear Command Register */
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#define AT91_AIC5_ICCR 0x48 /* Interrupt Clear Command Register [AIC5] */
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#define AT91_AIC_ISCR 0x12c /* Interrupt Set Command Register */
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#define AT91_AIC5_ISCR 0x4c /* Interrupt Set Command Register [AIC5] */
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#define AT91_AIC_EOICR 0x130 /* End of Interrupt Command Register */
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#define AT91_AIC5_EOICR 0x38 /* End of Interrupt Command Register [AIC5] */
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#define AT91_AIC_SPU 0x134 /* Spurious Interrupt Vector Register */
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#define AT91_AIC5_SPU 0x3c /* Spurious Interrupt Vector Register [AIC5] */
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#define AT91_AIC_DCR 0x138 /* Debug Control Register */
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#define AT91_AIC5_DCR 0x6c /* Debug Control Register [AIC5] */
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#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
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#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
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#define AT91_AIC_FFER 0x140 /* Fast Forcing Enable Register [SAM9 only] */
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#define AT91_AIC5_FFER 0x50 /* Fast Forcing Enable Register [AIC5] */
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#define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */
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#define AT91_AIC5_FFDR 0x54 /* Fast Forcing Disable Register [AIC5] */
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#define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */
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#define AT91_AIC5_FFSR 0x58 /* Fast Forcing Status Register [AIC5] */
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void at91_aic_handle_irq(struct pt_regs *regs);
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void at91_aic5_handle_irq(struct pt_regs *regs);
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#endif
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@ -22,7 +22,6 @@
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include "at91_aic.h"
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#include "generic.h"
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static void __init at91rm9200_dt_timer_init(void)
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@ -21,7 +21,6 @@
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include "at91_aic.h"
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#include "board.h"
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#include "generic.h"
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@ -24,7 +24,6 @@
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include "at91_aic.h"
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#include "generic.h"
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static void __init sama5_dt_device_init(void)
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@ -29,8 +29,6 @@ extern void __init at91_dt_initialize(void);
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/* Interrupts */
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extern void __init at91_init_irq_default(void);
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extern void __init at91_init_interrupts(unsigned int priority[]);
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extern void __init at91_aic_init(unsigned int priority[],
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unsigned int ext_irq_mask);
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extern int __init at91_aic_of_init(struct device_node *node,
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struct device_node *parent);
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extern int __init at91_aic5_of_init(struct device_node *node,
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@ -1,296 +0,0 @@
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/*
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* linux/arch/arm/mach-at91/irq.c
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*
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* Copyright (C) 2004 SAN People
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* Copyright (C) 2004 ATMEL
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* Copyright (C) Rick Bronson
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/bitmap.h>
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#include <linux/types.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/setup.h>
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#include <asm/exception.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include "at91_aic.h"
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void __iomem *at91_aic_base;
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static struct irq_domain *at91_aic_domain;
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static struct device_node *at91_aic_np;
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static unsigned int n_irqs = NR_AIC_IRQS;
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#ifdef CONFIG_PM
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static unsigned long *wakeups;
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static unsigned long *backups;
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#define set_backup(bit) set_bit(bit, backups)
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#define clear_backup(bit) clear_bit(bit, backups)
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static int at91_aic_pm_init(void)
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{
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backups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
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if (!backups)
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return -ENOMEM;
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wakeups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
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if (!wakeups) {
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kfree(backups);
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return -ENOMEM;
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}
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return 0;
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}
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static int at91_aic_set_wake(struct irq_data *d, unsigned value)
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{
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if (unlikely(d->hwirq >= n_irqs))
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return -EINVAL;
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if (value)
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set_bit(d->hwirq, wakeups);
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else
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clear_bit(d->hwirq, wakeups);
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return 0;
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}
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void at91_irq_suspend(void)
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{
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at91_aic_write(AT91_AIC_IDCR, *backups);
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at91_aic_write(AT91_AIC_IECR, *wakeups);
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}
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void at91_irq_resume(void)
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{
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at91_aic_write(AT91_AIC_IDCR, *wakeups);
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at91_aic_write(AT91_AIC_IECR, *backups);
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}
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#else
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static inline int at91_aic_pm_init(void)
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{
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return 0;
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}
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#define set_backup(bit)
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#define clear_backup(bit)
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#define at91_aic_set_wake NULL
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#endif /* CONFIG_PM */
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asmlinkage void __exception_irq_entry
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at91_aic_handle_irq(struct pt_regs *regs)
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{
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u32 irqnr;
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u32 irqstat;
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irqnr = at91_aic_read(AT91_AIC_IVR);
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irqstat = at91_aic_read(AT91_AIC_ISR);
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/*
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* ISR value is 0 when there is no current interrupt or when there is
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* a spurious interrupt
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*/
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if (!irqstat)
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at91_aic_write(AT91_AIC_EOICR, 0);
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else
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handle_IRQ(irqnr, regs);
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}
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static void at91_aic_mask_irq(struct irq_data *d)
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{
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/* Disable interrupt on AIC */
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at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
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/* Update ISR cache */
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clear_backup(d->hwirq);
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}
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static void at91_aic_unmask_irq(struct irq_data *d)
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{
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/* Enable interrupt on AIC */
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at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
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/* Update ISR cache */
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set_backup(d->hwirq);
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}
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static void at91_aic_eoi(struct irq_data *d)
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{
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/*
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* Mark end-of-interrupt on AIC, the controller doesn't care about
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* the value written. Moreover it's a write-only register.
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*/
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at91_aic_write(AT91_AIC_EOICR, 0);
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}
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static unsigned long *at91_extern_irq;
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u32 at91_get_extern_irq(void)
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{
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if (!at91_extern_irq)
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return 0;
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return *at91_extern_irq;
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}
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#define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq)
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static int at91_aic_compute_srctype(struct irq_data *d, unsigned type)
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{
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int srctype;
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switch (type) {
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case IRQ_TYPE_LEVEL_HIGH:
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srctype = AT91_AIC_SRCTYPE_HIGH;
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break;
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case IRQ_TYPE_EDGE_RISING:
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srctype = AT91_AIC_SRCTYPE_RISING;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
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srctype = AT91_AIC_SRCTYPE_LOW;
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else
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srctype = -EINVAL;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
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srctype = AT91_AIC_SRCTYPE_FALLING;
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else
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srctype = -EINVAL;
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break;
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default:
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srctype = -EINVAL;
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}
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return srctype;
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}
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static int at91_aic_set_type(struct irq_data *d, unsigned type)
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{
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unsigned int smr;
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int srctype;
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srctype = at91_aic_compute_srctype(d, type);
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if (srctype < 0)
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return srctype;
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smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
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at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
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return 0;
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}
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static struct irq_chip at91_aic_chip = {
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.name = "AIC",
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.irq_mask = at91_aic_mask_irq,
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.irq_unmask = at91_aic_unmask_irq,
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.irq_set_type = at91_aic_set_type,
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.irq_set_wake = at91_aic_set_wake,
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.irq_eoi = at91_aic_eoi,
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};
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static void __init at91_aic_hw_init(unsigned int spu_vector)
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{
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int i;
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/*
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* Perform 8 End Of Interrupt Command to make sure AIC
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* will not Lock out nIRQ
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*/
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for (i = 0; i < 8; i++)
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at91_aic_write(AT91_AIC_EOICR, 0);
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/*
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* Spurious Interrupt ID in Spurious Vector Register.
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* When there is no current interrupt, the IRQ Vector Register
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* reads the value stored in AIC_SPU
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*/
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at91_aic_write(AT91_AIC_SPU, spu_vector);
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/* No debugging in AIC: Debug (Protect) Control Register */
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at91_aic_write(AT91_AIC_DCR, 0);
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/* Disable and clear all interrupts initially */
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at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
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at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
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}
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/*
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* Initialize the AIC interrupt controller.
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*/
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void __init at91_aic_init(unsigned int *priority, unsigned int ext_irq_mask)
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{
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unsigned int i;
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int irq_base;
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at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
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* sizeof(*at91_extern_irq), GFP_KERNEL);
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if (at91_aic_pm_init() || at91_extern_irq == NULL)
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panic("Unable to allocate bit maps\n");
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*at91_extern_irq = ext_irq_mask;
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at91_aic_base = ioremap(AT91_AIC, 512);
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if (!at91_aic_base)
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panic("Unable to ioremap AIC registers\n");
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/* Add irq domain for AIC */
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irq_base = irq_alloc_descs(-1, 0, n_irqs, 0);
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if (irq_base < 0) {
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WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
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irq_base = 0;
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}
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at91_aic_domain = irq_domain_add_legacy(at91_aic_np, n_irqs,
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irq_base, 0,
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&irq_domain_simple_ops, NULL);
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if (!at91_aic_domain)
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panic("Unable to add AIC irq domain\n");
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|
||||
irq_set_default_host(at91_aic_domain);
|
||||
|
||||
/*
|
||||
* The IVR is used by macro get_irqnr_and_base to read and verify.
|
||||
* The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
|
||||
*/
|
||||
for (i = 0; i < n_irqs; i++) {
|
||||
/* Put hardware irq number in Source Vector Register: */
|
||||
at91_aic_write(AT91_AIC_SVR(i), NR_IRQS_LEGACY + i);
|
||||
/* Active Low interrupt, with the specified priority */
|
||||
at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
|
||||
irq_set_chip_and_handler(NR_IRQS_LEGACY + i, &at91_aic_chip, handle_fasteoi_irq);
|
||||
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
|
||||
at91_aic_hw_init(n_irqs);
|
||||
}
|
||||
|
|
@ -29,7 +29,6 @@
|
|||
#include <mach/cpu.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#include "at91_aic.h"
|
||||
#include "generic.h"
|
||||
#include "pm.h"
|
||||
#include "gpio.h"
|
||||
|
|
@ -136,19 +135,6 @@ static int at91_pm_enter(suspend_state_t state)
|
|||
else
|
||||
at91_gpio_suspend();
|
||||
|
||||
if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base) {
|
||||
at91_irq_suspend();
|
||||
|
||||
pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
|
||||
/* remember all the always-wake irqs */
|
||||
(at91_pmc_read(AT91_PMC_PCSR)
|
||||
| (1 << AT91_ID_FIQ)
|
||||
| (1 << AT91_ID_SYS)
|
||||
| (at91_get_extern_irq()))
|
||||
& at91_aic_read(AT91_AIC_IMR),
|
||||
state);
|
||||
}
|
||||
|
||||
switch (state) {
|
||||
/*
|
||||
* Suspend-to-RAM is like STANDBY plus slow clock mode, so
|
||||
|
|
@ -212,17 +198,9 @@ static int at91_pm_enter(suspend_state_t state)
|
|||
goto error;
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
|
||||
pr_debug("AT91: PM - wakeup %08x\n",
|
||||
at91_aic_read(AT91_AIC_IPR) &
|
||||
at91_aic_read(AT91_AIC_IMR));
|
||||
|
||||
error:
|
||||
target_state = PM_SUSPEND_ON;
|
||||
|
||||
if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
|
||||
at91_irq_resume();
|
||||
|
||||
if (of_have_populated_dt())
|
||||
at91_pinctrl_gpio_resume();
|
||||
else
|
||||
|
|
|
|||
|
|
@ -49,10 +49,6 @@ void __init at91_init_irq_default(void)
|
|||
|
||||
void __init at91_init_interrupts(unsigned int *priority)
|
||||
{
|
||||
/* Initialize the AIC interrupt controller */
|
||||
if (IS_ENABLED(CONFIG_OLD_IRQ_AT91))
|
||||
at91_aic_init(priority, at91_boot_soc.extern_irq);
|
||||
|
||||
/* Enable GPIO interrupts */
|
||||
at91_gpio_irq_setup();
|
||||
}
|
||||
|
|
|
|||
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Ссылка в новой задаче