dt-bindings: Add binding for i.MX8MQ CCM
This adds the binding for the i.MX8MQ Clock Controller Module. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Lucas Stach
Stephen Boyd
Родитель
651022382c
Коммит
1cf3817bf1
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@ -0,0 +1,20 @@
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* Clock bindings for NXP i.MX8M Quad
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Required properties:
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- compatible: Should be "fsl,imx8mq-ccm"
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- reg: Address and length of the register set
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- #clock-cells: Should be <1>
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- clocks: list of clock specifiers, must contain an entry for each required
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entry in clock-names
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- clock-names: should include the following entries:
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- "ckil"
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- "osc_25m"
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- "osc_27m"
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- "clk_ext1"
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- "clk_ext2"
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- "clk_ext3"
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- "clk_ext4"
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h
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for the full list of i.MX8M Quad clock IDs.
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@ -0,0 +1,395 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
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#define __DT_BINDINGS_CLOCK_IMX8MQ_H
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#define IMX8MQ_CLK_DUMMY 0
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#define IMX8MQ_CLK_32K 1
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#define IMX8MQ_CLK_25M 2
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#define IMX8MQ_CLK_27M 3
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#define IMX8MQ_CLK_EXT1 4
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#define IMX8MQ_CLK_EXT2 5
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#define IMX8MQ_CLK_EXT3 6
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#define IMX8MQ_CLK_EXT4 7
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/* ANAMIX PLL clocks */
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/* FRAC PLLs */
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/* ARM PLL */
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#define IMX8MQ_ARM_PLL_REF_SEL 8
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#define IMX8MQ_ARM_PLL_REF_DIV 9
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#define IMX8MQ_ARM_PLL 10
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#define IMX8MQ_ARM_PLL_BYPASS 11
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#define IMX8MQ_ARM_PLL_OUT 12
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/* GPU PLL */
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#define IMX8MQ_GPU_PLL_REF_SEL 13
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#define IMX8MQ_GPU_PLL_REF_DIV 14
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#define IMX8MQ_GPU_PLL 15
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#define IMX8MQ_GPU_PLL_BYPASS 16
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#define IMX8MQ_GPU_PLL_OUT 17
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/* VPU PLL */
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#define IMX8MQ_VPU_PLL_REF_SEL 18
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#define IMX8MQ_VPU_PLL_REF_DIV 19
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#define IMX8MQ_VPU_PLL 20
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#define IMX8MQ_VPU_PLL_BYPASS 21
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#define IMX8MQ_VPU_PLL_OUT 22
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/* AUDIO PLL1 */
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#define IMX8MQ_AUDIO_PLL1_REF_SEL 23
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#define IMX8MQ_AUDIO_PLL1_REF_DIV 24
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#define IMX8MQ_AUDIO_PLL1 25
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#define IMX8MQ_AUDIO_PLL1_BYPASS 26
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#define IMX8MQ_AUDIO_PLL1_OUT 27
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/* AUDIO PLL2 */
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#define IMX8MQ_AUDIO_PLL2_REF_SEL 28
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#define IMX8MQ_AUDIO_PLL2_REF_DIV 29
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#define IMX8MQ_AUDIO_PLL2 30
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#define IMX8MQ_AUDIO_PLL2_BYPASS 31
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#define IMX8MQ_AUDIO_PLL2_OUT 32
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/* VIDEO PLL1 */
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#define IMX8MQ_VIDEO_PLL1_REF_SEL 33
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#define IMX8MQ_VIDEO_PLL1_REF_DIV 34
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#define IMX8MQ_VIDEO_PLL1 35
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#define IMX8MQ_VIDEO_PLL1_BYPASS 36
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#define IMX8MQ_VIDEO_PLL1_OUT 37
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/* SYS1 PLL */
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#define IMX8MQ_SYS1_PLL1_REF_SEL 38
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#define IMX8MQ_SYS1_PLL1_REF_DIV 39
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#define IMX8MQ_SYS1_PLL1 40
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#define IMX8MQ_SYS1_PLL1_OUT 41
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#define IMX8MQ_SYS1_PLL1_OUT_DIV 42
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#define IMX8MQ_SYS1_PLL2 43
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#define IMX8MQ_SYS1_PLL2_DIV 44
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#define IMX8MQ_SYS1_PLL2_OUT 45
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/* SYS2 PLL */
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#define IMX8MQ_SYS2_PLL1_REF_SEL 46
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#define IMX8MQ_SYS2_PLL1_REF_DIV 47
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#define IMX8MQ_SYS2_PLL1 48
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#define IMX8MQ_SYS2_PLL1_OUT 49
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#define IMX8MQ_SYS2_PLL1_OUT_DIV 50
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#define IMX8MQ_SYS2_PLL2 51
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#define IMX8MQ_SYS2_PLL2_DIV 52
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#define IMX8MQ_SYS2_PLL2_OUT 53
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/* SYS3 PLL */
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#define IMX8MQ_SYS3_PLL1_REF_SEL 54
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#define IMX8MQ_SYS3_PLL1_REF_DIV 55
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#define IMX8MQ_SYS3_PLL1 56
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#define IMX8MQ_SYS3_PLL1_OUT 57
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#define IMX8MQ_SYS3_PLL1_OUT_DIV 58
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#define IMX8MQ_SYS3_PLL2 59
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#define IMX8MQ_SYS3_PLL2_DIV 60
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#define IMX8MQ_SYS3_PLL2_OUT 61
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/* DRAM PLL */
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#define IMX8MQ_DRAM_PLL1_REF_SEL 62
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#define IMX8MQ_DRAM_PLL1_REF_DIV 63
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#define IMX8MQ_DRAM_PLL1 64
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#define IMX8MQ_DRAM_PLL1_OUT 65
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#define IMX8MQ_DRAM_PLL1_OUT_DIV 66
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#define IMX8MQ_DRAM_PLL2 67
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#define IMX8MQ_DRAM_PLL2_DIV 68
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#define IMX8MQ_DRAM_PLL2_OUT 69
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/* SYS PLL DIV */
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#define IMX8MQ_SYS1_PLL_40M 70
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#define IMX8MQ_SYS1_PLL_80M 71
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#define IMX8MQ_SYS1_PLL_100M 72
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#define IMX8MQ_SYS1_PLL_133M 73
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#define IMX8MQ_SYS1_PLL_160M 74
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#define IMX8MQ_SYS1_PLL_200M 75
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#define IMX8MQ_SYS1_PLL_266M 76
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#define IMX8MQ_SYS1_PLL_400M 77
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#define IMX8MQ_SYS1_PLL_800M 78
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#define IMX8MQ_SYS2_PLL_50M 79
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#define IMX8MQ_SYS2_PLL_100M 80
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#define IMX8MQ_SYS2_PLL_125M 81
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#define IMX8MQ_SYS2_PLL_166M 82
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#define IMX8MQ_SYS2_PLL_200M 83
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#define IMX8MQ_SYS2_PLL_250M 84
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#define IMX8MQ_SYS2_PLL_333M 85
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#define IMX8MQ_SYS2_PLL_500M 86
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#define IMX8MQ_SYS2_PLL_1000M 87
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/* CCM ROOT clocks */
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/* A53 */
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#define IMX8MQ_CLK_A53_SRC 88
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#define IMX8MQ_CLK_A53_CG 89
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#define IMX8MQ_CLK_A53_DIV 90
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/* M4 */
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#define IMX8MQ_CLK_M4_SRC 91
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#define IMX8MQ_CLK_M4_CG 92
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#define IMX8MQ_CLK_M4_DIV 93
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/* VPU */
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#define IMX8MQ_CLK_VPU_SRC 94
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#define IMX8MQ_CLK_VPU_CG 95
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#define IMX8MQ_CLK_VPU_DIV 96
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/* GPU CORE */
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#define IMX8MQ_CLK_GPU_CORE_SRC 97
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#define IMX8MQ_CLK_GPU_CORE_CG 98
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#define IMX8MQ_CLK_GPU_CORE_DIV 99
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/* GPU SHADER */
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#define IMX8MQ_CLK_GPU_SHADER_SRC 100
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#define IMX8MQ_CLK_GPU_SHADER_CG 101
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#define IMX8MQ_CLK_GPU_SHADER_DIV 102
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/* BUS TYPE */
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/* MAIN AXI */
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#define IMX8MQ_CLK_MAIN_AXI 103
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/* ENET AXI */
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#define IMX8MQ_CLK_ENET_AXI 104
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/* NAND_USDHC_BUS */
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#define IMX8MQ_CLK_NAND_USDHC_BUS 105
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/* VPU BUS */
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#define IMX8MQ_CLK_VPU_BUS 106
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/* DISP_AXI */
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#define IMX8MQ_CLK_DISP_AXI 107
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/* DISP APB */
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#define IMX8MQ_CLK_DISP_APB 108
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/* DISP RTRM */
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#define IMX8MQ_CLK_DISP_RTRM 109
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/* USB_BUS */
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#define IMX8MQ_CLK_USB_BUS 110
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/* GPU_AXI */
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#define IMX8MQ_CLK_GPU_AXI 111
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/* GPU_AHB */
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#define IMX8MQ_CLK_GPU_AHB 112
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/* NOC */
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#define IMX8MQ_CLK_NOC 113
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/* NOC_APB */
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#define IMX8MQ_CLK_NOC_APB 115
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/* AHB */
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#define IMX8MQ_CLK_AHB 116
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/* AUDIO AHB */
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#define IMX8MQ_CLK_AUDIO_AHB 117
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/* DRAM_ALT */
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#define IMX8MQ_CLK_DRAM_ALT 118
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/* DRAM APB */
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#define IMX8MQ_CLK_DRAM_APB 119
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/* VPU_G1 */
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#define IMX8MQ_CLK_VPU_G1 120
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/* VPU_G2 */
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#define IMX8MQ_CLK_VPU_G2 121
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/* DISP_DTRC */
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#define IMX8MQ_CLK_DISP_DTRC 122
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/* DISP_DC8000 */
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#define IMX8MQ_CLK_DISP_DC8000 123
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/* PCIE_CTRL */
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#define IMX8MQ_CLK_PCIE1_CTRL 124
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/* PCIE_PHY */
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#define IMX8MQ_CLK_PCIE1_PHY 125
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/* PCIE_AUX */
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#define IMX8MQ_CLK_PCIE1_AUX 126
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/* DC_PIXEL */
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#define IMX8MQ_CLK_DC_PIXEL 127
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/* LCDIF_PIXEL */
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#define IMX8MQ_CLK_LCDIF_PIXEL 128
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/* SAI1~6 */
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#define IMX8MQ_CLK_SAI1 129
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#define IMX8MQ_CLK_SAI2 130
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#define IMX8MQ_CLK_SAI3 131
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#define IMX8MQ_CLK_SAI4 132
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#define IMX8MQ_CLK_SAI5 133
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#define IMX8MQ_CLK_SAI6 134
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/* SPDIF1 */
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#define IMX8MQ_CLK_SPDIF1 135
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/* SPDIF2 */
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#define IMX8MQ_CLK_SPDIF2 136
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/* ENET_REF */
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#define IMX8MQ_CLK_ENET_REF 137
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/* ENET_TIMER */
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#define IMX8MQ_CLK_ENET_TIMER 138
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/* ENET_PHY */
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#define IMX8MQ_CLK_ENET_PHY_REF 139
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/* NAND */
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#define IMX8MQ_CLK_NAND 140
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/* QSPI */
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#define IMX8MQ_CLK_QSPI 141
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/* USDHC1 */
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#define IMX8MQ_CLK_USDHC1 142
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/* USDHC2 */
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#define IMX8MQ_CLK_USDHC2 143
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/* I2C1 */
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#define IMX8MQ_CLK_I2C1 144
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/* I2C2 */
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#define IMX8MQ_CLK_I2C2 145
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/* I2C3 */
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#define IMX8MQ_CLK_I2C3 146
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/* I2C4 */
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#define IMX8MQ_CLK_I2C4 147
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/* UART1 */
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#define IMX8MQ_CLK_UART1 148
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/* UART2 */
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#define IMX8MQ_CLK_UART2 149
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/* UART3 */
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#define IMX8MQ_CLK_UART3 150
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/* UART4 */
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#define IMX8MQ_CLK_UART4 151
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/* USB_CORE_REF */
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#define IMX8MQ_CLK_USB_CORE_REF 152
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/* USB_PHY_REF */
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#define IMX8MQ_CLK_USB_PHY_REF 163
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/* ECSPI1 */
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#define IMX8MQ_CLK_ECSPI1 164
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/* ECSPI2 */
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#define IMX8MQ_CLK_ECSPI2 165
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/* PWM1 */
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#define IMX8MQ_CLK_PWM1 166
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/* PWM2 */
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#define IMX8MQ_CLK_PWM2 167
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/* PWM3 */
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#define IMX8MQ_CLK_PWM3 168
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/* PWM4 */
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#define IMX8MQ_CLK_PWM4 169
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/* GPT1 */
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#define IMX8MQ_CLK_GPT1 170
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/* WDOG */
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#define IMX8MQ_CLK_WDOG 171
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/* WRCLK */
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#define IMX8MQ_CLK_WRCLK 172
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/* DSI_CORE */
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#define IMX8MQ_CLK_DSI_CORE 173
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/* DSI_PHY */
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#define IMX8MQ_CLK_DSI_PHY_REF 174
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/* DSI_DBI */
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#define IMX8MQ_CLK_DSI_DBI 175
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/*DSI_ESC */
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#define IMX8MQ_CLK_DSI_ESC 176
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/* CSI1_CORE */
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#define IMX8MQ_CLK_CSI1_CORE 177
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/* CSI1_PHY */
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#define IMX8MQ_CLK_CSI1_PHY_REF 178
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/* CSI_ESC */
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#define IMX8MQ_CLK_CSI1_ESC 179
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/* CSI2_CORE */
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#define IMX8MQ_CLK_CSI2_CORE 170
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/* CSI2_PHY */
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#define IMX8MQ_CLK_CSI2_PHY_REF 181
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/* CSI2_ESC */
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#define IMX8MQ_CLK_CSI2_ESC 182
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/* PCIE2_CTRL */
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#define IMX8MQ_CLK_PCIE2_CTRL 183
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/* PCIE2_PHY */
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#define IMX8MQ_CLK_PCIE2_PHY 184
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/* PCIE2_AUX */
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#define IMX8MQ_CLK_PCIE2_AUX 185
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/* ECSPI3 */
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#define IMX8MQ_CLK_ECSPI3 186
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/* CCGR clocks */
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#define IMX8MQ_CLK_A53_ROOT 187
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#define IMX8MQ_CLK_DRAM_ROOT 188
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#define IMX8MQ_CLK_ECSPI1_ROOT 189
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#define IMX8MQ_CLK_ECSPI2_ROOT 180
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#define IMX8MQ_CLK_ECSPI3_ROOT 181
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#define IMX8MQ_CLK_ENET1_ROOT 182
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#define IMX8MQ_CLK_GPT1_ROOT 193
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#define IMX8MQ_CLK_I2C1_ROOT 194
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#define IMX8MQ_CLK_I2C2_ROOT 195
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#define IMX8MQ_CLK_I2C3_ROOT 196
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#define IMX8MQ_CLK_I2C4_ROOT 197
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#define IMX8MQ_CLK_M4_ROOT 198
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#define IMX8MQ_CLK_PCIE1_ROOT 199
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#define IMX8MQ_CLK_PCIE2_ROOT 200
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#define IMX8MQ_CLK_PWM1_ROOT 201
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#define IMX8MQ_CLK_PWM2_ROOT 202
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#define IMX8MQ_CLK_PWM3_ROOT 203
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#define IMX8MQ_CLK_PWM4_ROOT 204
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#define IMX8MQ_CLK_QSPI_ROOT 205
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#define IMX8MQ_CLK_SAI1_ROOT 206
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#define IMX8MQ_CLK_SAI2_ROOT 207
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#define IMX8MQ_CLK_SAI3_ROOT 208
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#define IMX8MQ_CLK_SAI4_ROOT 209
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#define IMX8MQ_CLK_SAI5_ROOT 210
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#define IMX8MQ_CLK_SAI6_ROOT 212
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#define IMX8MQ_CLK_UART1_ROOT 213
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#define IMX8MQ_CLK_UART2_ROOT 214
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#define IMX8MQ_CLK_UART3_ROOT 215
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#define IMX8MQ_CLK_UART4_ROOT 216
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#define IMX8MQ_CLK_USB1_CTRL_ROOT 217
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#define IMX8MQ_CLK_USB2_CTRL_ROOT 218
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#define IMX8MQ_CLK_USB1_PHY_ROOT 219
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#define IMX8MQ_CLK_USB2_PHY_ROOT 220
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#define IMX8MQ_CLK_USDHC1_ROOT 221
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#define IMX8MQ_CLK_USDHC2_ROOT 222
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#define IMX8MQ_CLK_WDOG1_ROOT 223
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#define IMX8MQ_CLK_WDOG2_ROOT 224
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#define IMX8MQ_CLK_WDOG3_ROOT 225
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#define IMX8MQ_CLK_GPU_ROOT 226
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#define IMX8MQ_CLK_HEVC_ROOT 227
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#define IMX8MQ_CLK_AVC_ROOT 228
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#define IMX8MQ_CLK_VP9_ROOT 229
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#define IMX8MQ_CLK_HEVC_INTER_ROOT 230
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#define IMX8MQ_CLK_DISP_ROOT 231
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#define IMX8MQ_CLK_HDMI_ROOT 232
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#define IMX8MQ_CLK_HDMI_PHY_ROOT 233
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#define IMX8MQ_CLK_VPU_DEC_ROOT 234
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#define IMX8MQ_CLK_CSI1_ROOT 235
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#define IMX8MQ_CLK_CSI2_ROOT 236
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#define IMX8MQ_CLK_RAWNAND_ROOT 237
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#define IMX8MQ_CLK_SDMA1_ROOT 238
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#define IMX8MQ_CLK_SDMA2_ROOT 239
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#define IMX8MQ_CLK_VPU_G1_ROOT 240
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#define IMX8MQ_CLK_VPU_G2_ROOT 241
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/* SCCG PLL GATE */
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#define IMX8MQ_SYS1_PLL_OUT 232
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#define IMX8MQ_SYS2_PLL_OUT 243
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#define IMX8MQ_SYS3_PLL_OUT 244
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#define IMX8MQ_DRAM_PLL_OUT 245
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#define IMX8MQ_GPT_3M_CLK 246
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#define IMX8MQ_CLK_IPG_ROOT 247
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#define IMX8MQ_CLK_IPG_AUDIO_ROOT 248
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#define IMX8MQ_CLK_SAI1_IPG 249
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#define IMX8MQ_CLK_SAI2_IPG 250
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#define IMX8MQ_CLK_SAI3_IPG 251
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#define IMX8MQ_CLK_SAI4_IPG 252
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#define IMX8MQ_CLK_SAI5_IPG 253
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#define IMX8MQ_CLK_SAI6_IPG 254
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/* DSI AHB/IPG clocks */
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/* rxesc clock */
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#define IMX8MQ_CLK_DSI_AHB 255
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/* txesc clock */
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#define IMX8MQ_CLK_DSI_IPG_DIV 256
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#define IMX8MQ_CLK_TMU_ROOT 265
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/* Display root clocks */
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#define IMX8MQ_CLK_DISP_AXI_ROOT 266
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#define IMX8MQ_CLK_DISP_APB_ROOT 267
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#define IMX8MQ_CLK_DISP_RTRM_ROOT 268
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#define IMX8MQ_CLK_OCOTP_ROOT 269
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#define IMX8MQ_CLK_DRAM_ALT_ROOT 270
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#define IMX8MQ_CLK_DRAM_CORE 271
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#define IMX8MQ_CLK_MU_ROOT 272
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#define IMX8MQ_VIDEO2_PLL_OUT 273
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#define IMX8MQ_CLK_CLKO2 274
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#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 275
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#define IMX8MQ_CLK_END 276
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#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
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