bna: IOC failure auto recovery fix
Change Details: - Made IOC auto_recovery synchronized and not timer based. - Only one PCI function will attempt to recover and reinitialize the ASIC on a failure, that too after all the active PCI functions acknowledge the IOC failure. Signed-off-by: Debashis Dutt <ddutt@brocade.com> Signed-off-by: Rasesh Mody <rmody@brocade.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Rasesh Mody
David S. Miller
Родитель
aad75b66f1
Коммит
1d32f76962
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@ -112,16 +112,18 @@ struct bfa_ioc_pci_attr {
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* IOC states
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*/
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enum bfa_ioc_state {
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BFA_IOC_RESET = 1, /*!< IOC is in reset state */
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BFA_IOC_SEMWAIT = 2, /*!< Waiting for IOC h/w semaphore */
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BFA_IOC_HWINIT = 3, /*!< IOC h/w is being initialized */
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BFA_IOC_GETATTR = 4, /*!< IOC is being configured */
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BFA_IOC_OPERATIONAL = 5, /*!< IOC is operational */
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BFA_IOC_INITFAIL = 6, /*!< IOC hardware failure */
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BFA_IOC_HBFAIL = 7, /*!< IOC heart-beat failure */
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BFA_IOC_DISABLING = 8, /*!< IOC is being disabled */
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BFA_IOC_DISABLED = 9, /*!< IOC is disabled */
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BFA_IOC_FWMISMATCH = 10, /*!< IOC f/w different from drivers */
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BFA_IOC_UNINIT = 1, /*!< IOC is in uninit state */
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BFA_IOC_RESET = 2, /*!< IOC is in reset state */
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BFA_IOC_SEMWAIT = 3, /*!< Waiting for IOC h/w semaphore */
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BFA_IOC_HWINIT = 4, /*!< IOC h/w is being initialized */
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BFA_IOC_GETATTR = 5, /*!< IOC is being configured */
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BFA_IOC_OPERATIONAL = 6, /*!< IOC is operational */
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BFA_IOC_INITFAIL = 7, /*!< IOC hardware failure */
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BFA_IOC_FAIL = 8, /*!< IOC heart-beat failure */
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BFA_IOC_DISABLING = 9, /*!< IOC is being disabled */
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BFA_IOC_DISABLED = 10, /*!< IOC is disabled */
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BFA_IOC_FWMISMATCH = 11, /*!< IOC f/w different from drivers */
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BFA_IOC_ENABLING = 12, /*!< IOC is being enabled */
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};
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/**
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -26,16 +26,7 @@
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#define BFA_IOC_TOV 3000 /* msecs */
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#define BFA_IOC_HWSEM_TOV 500 /* msecs */
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#define BFA_IOC_HB_TOV 500 /* msecs */
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#define BFA_IOC_HWINIT_MAX 2
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#define BFA_IOC_TOV_RECOVER BFA_IOC_HB_TOV
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/**
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* Generic Scatter Gather Element used by driver
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*/
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struct bfa_sge {
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u32 sg_len;
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void *sg_addr;
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};
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#define BFA_IOC_HWINIT_MAX 5
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/**
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* PCI device information required by IOC
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@ -64,19 +55,6 @@ struct bfa_dma {
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#define BFI_SMEM_CB_SIZE 0x200000U /* ! 2MB for crossbow */
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#define BFI_SMEM_CT_SIZE 0x280000U /* ! 2.5MB for catapult */
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/**
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* @brief BFA dma address assignment macro
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*/
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#define bfa_dma_addr_set(dma_addr, pa) \
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__bfa_dma_addr_set(&dma_addr, (u64)pa)
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static inline void
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__bfa_dma_addr_set(union bfi_addr_u *dma_addr, u64 pa)
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{
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dma_addr->a32.addr_lo = (u32) pa;
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dma_addr->a32.addr_hi = (u32) (upper_32_bits(pa));
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}
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/**
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* @brief BFA dma address assignment macro. (big endian format)
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*/
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@ -105,8 +83,11 @@ struct bfa_ioc_regs {
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void __iomem *host_page_num_fn;
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void __iomem *heartbeat;
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void __iomem *ioc_fwstate;
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void __iomem *alt_ioc_fwstate;
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void __iomem *ll_halt;
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void __iomem *alt_ll_halt;
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void __iomem *err_set;
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void __iomem *ioc_fail_sync;
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void __iomem *shirq_isr_next;
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void __iomem *shirq_msk_next;
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void __iomem *smem_page_start;
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@ -165,16 +146,22 @@ struct bfa_ioc_hbfail_notify {
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(__notify)->cbarg = (__cbarg); \
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} while (0)
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struct bfa_iocpf {
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bfa_fsm_t fsm;
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struct bfa_ioc *ioc;
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u32 retry_count;
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bool auto_recover;
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};
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struct bfa_ioc {
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bfa_fsm_t fsm;
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struct bfa *bfa;
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struct bfa_pcidev pcidev;
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struct bfa_timer_mod *timer_mod;
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struct timer_list ioc_timer;
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struct timer_list iocpf_timer;
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struct timer_list sem_timer;
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struct timer_list hb_timer;
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u32 hb_count;
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u32 retry_count;
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struct list_head hb_notify_q;
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void *dbg_fwsave;
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int dbg_fwsave_len;
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@ -182,7 +169,6 @@ struct bfa_ioc {
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enum bfi_mclass ioc_mc;
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struct bfa_ioc_regs ioc_regs;
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struct bfa_ioc_drv_stats stats;
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bool auto_recover;
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bool fcmode;
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bool ctdev;
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bool cna;
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@ -195,6 +181,7 @@ struct bfa_ioc {
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struct bfa_ioc_cbfn *cbfn;
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struct bfa_ioc_mbox_mod mbox_mod;
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struct bfa_ioc_hwif *ioc_hwif;
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struct bfa_iocpf iocpf;
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};
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struct bfa_ioc_hwif {
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@ -205,8 +192,12 @@ struct bfa_ioc_hwif {
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void (*ioc_map_port) (struct bfa_ioc *ioc);
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void (*ioc_isr_mode_set) (struct bfa_ioc *ioc,
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bool msix);
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void (*ioc_notify_hbfail) (struct bfa_ioc *ioc);
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void (*ioc_notify_fail) (struct bfa_ioc *ioc);
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void (*ioc_ownership_reset) (struct bfa_ioc *ioc);
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void (*ioc_sync_join) (struct bfa_ioc *ioc);
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void (*ioc_sync_leave) (struct bfa_ioc *ioc);
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void (*ioc_sync_ack) (struct bfa_ioc *ioc);
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bool (*ioc_sync_complete) (struct bfa_ioc *ioc);
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};
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#define bfa_ioc_pcifn(__ioc) ((__ioc)->pcidev.pci_func)
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@ -271,7 +262,6 @@ void bfa_nw_ioc_enable(struct bfa_ioc *ioc);
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void bfa_nw_ioc_disable(struct bfa_ioc *ioc);
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void bfa_nw_ioc_error_isr(struct bfa_ioc *ioc);
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void bfa_nw_ioc_get_attr(struct bfa_ioc *ioc, struct bfa_ioc_attr *ioc_attr);
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void bfa_nw_ioc_hbfail_register(struct bfa_ioc *ioc,
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struct bfa_ioc_hbfail_notify *notify);
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@ -289,7 +279,8 @@ mac_t bfa_nw_ioc_get_mac(struct bfa_ioc *ioc);
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*/
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void bfa_nw_ioc_timeout(void *ioc);
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void bfa_nw_ioc_hb_check(void *ioc);
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void bfa_nw_ioc_sem_timeout(void *ioc);
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void bfa_nw_iocpf_timeout(void *ioc);
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void bfa_nw_iocpf_sem_timeout(void *ioc);
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/*
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* F/W Image Size & Chunk
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@ -22,6 +22,15 @@
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#include "bfi_ctreg.h"
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#include "bfa_defs.h"
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#define bfa_ioc_ct_sync_pos(__ioc) \
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((u32) (1 << bfa_ioc_pcifn(__ioc)))
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#define BFA_IOC_SYNC_REQD_SH 16
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#define bfa_ioc_ct_get_sync_ackd(__val) (__val & 0x0000ffff)
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#define bfa_ioc_ct_clear_sync_ackd(__val) (__val & 0xffff0000)
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#define bfa_ioc_ct_get_sync_reqd(__val) (__val >> BFA_IOC_SYNC_REQD_SH)
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#define bfa_ioc_ct_sync_reqd_pos(__ioc) \
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(bfa_ioc_ct_sync_pos(__ioc) << BFA_IOC_SYNC_REQD_SH)
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/*
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* forward declarations
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*/
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@ -30,8 +39,12 @@ static void bfa_ioc_ct_firmware_unlock(struct bfa_ioc *ioc);
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static void bfa_ioc_ct_reg_init(struct bfa_ioc *ioc);
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static void bfa_ioc_ct_map_port(struct bfa_ioc *ioc);
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static void bfa_ioc_ct_isr_mode_set(struct bfa_ioc *ioc, bool msix);
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static void bfa_ioc_ct_notify_hbfail(struct bfa_ioc *ioc);
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static void bfa_ioc_ct_notify_fail(struct bfa_ioc *ioc);
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static void bfa_ioc_ct_ownership_reset(struct bfa_ioc *ioc);
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static void bfa_ioc_ct_sync_join(struct bfa_ioc *ioc);
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static void bfa_ioc_ct_sync_leave(struct bfa_ioc *ioc);
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static void bfa_ioc_ct_sync_ack(struct bfa_ioc *ioc);
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static bool bfa_ioc_ct_sync_complete(struct bfa_ioc *ioc);
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static enum bfa_status bfa_ioc_ct_pll_init(void __iomem *rb, bool fcmode);
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static struct bfa_ioc_hwif nw_hwif_ct;
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@ -48,8 +61,12 @@ bfa_nw_ioc_set_ct_hwif(struct bfa_ioc *ioc)
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nw_hwif_ct.ioc_reg_init = bfa_ioc_ct_reg_init;
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nw_hwif_ct.ioc_map_port = bfa_ioc_ct_map_port;
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nw_hwif_ct.ioc_isr_mode_set = bfa_ioc_ct_isr_mode_set;
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nw_hwif_ct.ioc_notify_hbfail = bfa_ioc_ct_notify_hbfail;
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nw_hwif_ct.ioc_notify_fail = bfa_ioc_ct_notify_fail;
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nw_hwif_ct.ioc_ownership_reset = bfa_ioc_ct_ownership_reset;
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nw_hwif_ct.ioc_sync_join = bfa_ioc_ct_sync_join;
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nw_hwif_ct.ioc_sync_leave = bfa_ioc_ct_sync_leave;
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nw_hwif_ct.ioc_sync_ack = bfa_ioc_ct_sync_ack;
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nw_hwif_ct.ioc_sync_complete = bfa_ioc_ct_sync_complete;
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ioc->ioc_hwif = &nw_hwif_ct;
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}
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@ -86,6 +103,7 @@ bfa_ioc_ct_firmware_lock(struct bfa_ioc *ioc)
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if (usecnt == 0) {
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writel(1, ioc->ioc_regs.ioc_usage_reg);
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bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
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writel(0, ioc->ioc_regs.ioc_fail_sync);
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return true;
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}
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@ -149,12 +167,14 @@ bfa_ioc_ct_firmware_unlock(struct bfa_ioc *ioc)
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* Notify other functions on HB failure.
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*/
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static void
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bfa_ioc_ct_notify_hbfail(struct bfa_ioc *ioc)
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bfa_ioc_ct_notify_fail(struct bfa_ioc *ioc)
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{
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if (ioc->cna) {
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writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt);
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writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt);
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/* Wait for halt to take effect */
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readl(ioc->ioc_regs.ll_halt);
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readl(ioc->ioc_regs.alt_ll_halt);
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} else {
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writel(__PSS_ERR_STATUS_SET, ioc->ioc_regs.err_set);
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readl(ioc->ioc_regs.err_set);
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@ -206,15 +226,19 @@ bfa_ioc_ct_reg_init(struct bfa_ioc *ioc)
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if (ioc->port_id == 0) {
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ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
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ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
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ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG;
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ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].hfn;
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ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].lpu;
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ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;
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ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1;
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} else {
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ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
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ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
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ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC0_STATE_REG;
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ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].hfn;
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ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].lpu;
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ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1;
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ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0;
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}
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/*
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@ -232,6 +256,7 @@ bfa_ioc_ct_reg_init(struct bfa_ioc *ioc)
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ioc->ioc_regs.ioc_usage_sem_reg = (rb + HOST_SEM1_REG);
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ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
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ioc->ioc_regs.ioc_usage_reg = (rb + BFA_FW_USE_COUNT);
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ioc->ioc_regs.ioc_fail_sync = (rb + BFA_IOC_FAIL_SYNC);
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/**
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* sram memory access
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@ -317,6 +342,77 @@ bfa_ioc_ct_ownership_reset(struct bfa_ioc *ioc)
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bfa_nw_ioc_hw_sem_release(ioc);
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}
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/**
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* Synchronized IOC failure processing routines
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*/
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static void
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bfa_ioc_ct_sync_join(struct bfa_ioc *ioc)
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{
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u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
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u32 sync_pos = bfa_ioc_ct_sync_reqd_pos(ioc);
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writel((r32 | sync_pos), ioc->ioc_regs.ioc_fail_sync);
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}
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static void
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bfa_ioc_ct_sync_leave(struct bfa_ioc *ioc)
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{
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u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
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u32 sync_msk = bfa_ioc_ct_sync_reqd_pos(ioc) |
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bfa_ioc_ct_sync_pos(ioc);
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writel((r32 & ~sync_msk), ioc->ioc_regs.ioc_fail_sync);
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}
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static void
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bfa_ioc_ct_sync_ack(struct bfa_ioc *ioc)
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{
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u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
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writel((r32 | bfa_ioc_ct_sync_pos(ioc)), ioc->ioc_regs.ioc_fail_sync);
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}
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static bool
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bfa_ioc_ct_sync_complete(struct bfa_ioc *ioc)
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{
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u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
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u32 sync_reqd = bfa_ioc_ct_get_sync_reqd(r32);
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u32 sync_ackd = bfa_ioc_ct_get_sync_ackd(r32);
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u32 tmp_ackd;
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if (sync_ackd == 0)
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return true;
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/**
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* The check below is to see whether any other PCI fn
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* has reinitialized the ASIC (reset sync_ackd bits)
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* and failed again while this IOC was waiting for hw
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* semaphore (in bfa_iocpf_sm_semwait()).
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*/
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tmp_ackd = sync_ackd;
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if ((sync_reqd & bfa_ioc_ct_sync_pos(ioc)) &&
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!(sync_ackd & bfa_ioc_ct_sync_pos(ioc)))
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sync_ackd |= bfa_ioc_ct_sync_pos(ioc);
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if (sync_reqd == sync_ackd) {
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writel(bfa_ioc_ct_clear_sync_ackd(r32),
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ioc->ioc_regs.ioc_fail_sync);
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writel(BFI_IOC_FAIL, ioc->ioc_regs.ioc_fwstate);
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writel(BFI_IOC_FAIL, ioc->ioc_regs.alt_ioc_fwstate);
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return true;
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}
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/**
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* If another PCI fn reinitialized and failed again while
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* this IOC was waiting for hw sem, the sync_ackd bit for
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* this IOC need to be set again to allow reinitialization.
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*/
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if (tmp_ackd != sync_ackd)
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writel((r32 | sync_ackd), ioc->ioc_regs.ioc_fail_sync);
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return false;
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}
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static enum bfa_status
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bfa_ioc_ct_pll_init(void __iomem *rb, bool fcmode)
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{
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@ -535,6 +535,7 @@ enum {
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#define BFA_IOC1_HBEAT_REG HOST_SEM2_INFO_REG
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#define BFA_IOC1_STATE_REG HOST_SEM3_INFO_REG
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#define BFA_FW_USE_COUNT HOST_SEM4_INFO_REG
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#define BFA_IOC_FAIL_SYNC HOST_SEM5_INFO_REG
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#define CPE_DEPTH_Q(__n) \
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(CPE_DEPTH_Q0 + (__n) * (CPE_DEPTH_Q1 - CPE_DEPTH_Q0))
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@ -552,22 +553,30 @@ enum {
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(RME_PI_PTR_Q0 + (__n) * (RME_PI_PTR_Q1 - RME_PI_PTR_Q0))
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#define RME_CI_PTR_Q(__n) \
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(RME_CI_PTR_Q0 + (__n) * (RME_CI_PTR_Q1 - RME_CI_PTR_Q0))
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#define HQM_QSET_RXQ_DRBL_P0(__n) (HQM_QSET0_RXQ_DRBL_P0 + (__n) \
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* (HQM_QSET1_RXQ_DRBL_P0 - HQM_QSET0_RXQ_DRBL_P0))
|
||||
#define HQM_QSET_TXQ_DRBL_P0(__n) (HQM_QSET0_TXQ_DRBL_P0 + (__n) \
|
||||
* (HQM_QSET1_TXQ_DRBL_P0 - HQM_QSET0_TXQ_DRBL_P0))
|
||||
#define HQM_QSET_IB_DRBL_1_P0(__n) (HQM_QSET0_IB_DRBL_1_P0 + (__n) \
|
||||
* (HQM_QSET1_IB_DRBL_1_P0 - HQM_QSET0_IB_DRBL_1_P0))
|
||||
#define HQM_QSET_IB_DRBL_2_P0(__n) (HQM_QSET0_IB_DRBL_2_P0 + (__n) \
|
||||
* (HQM_QSET1_IB_DRBL_2_P0 - HQM_QSET0_IB_DRBL_2_P0))
|
||||
#define HQM_QSET_RXQ_DRBL_P1(__n) (HQM_QSET0_RXQ_DRBL_P1 + (__n) \
|
||||
* (HQM_QSET1_RXQ_DRBL_P1 - HQM_QSET0_RXQ_DRBL_P1))
|
||||
#define HQM_QSET_TXQ_DRBL_P1(__n) (HQM_QSET0_TXQ_DRBL_P1 + (__n) \
|
||||
* (HQM_QSET1_TXQ_DRBL_P1 - HQM_QSET0_TXQ_DRBL_P1))
|
||||
#define HQM_QSET_IB_DRBL_1_P1(__n) (HQM_QSET0_IB_DRBL_1_P1 + (__n) \
|
||||
* (HQM_QSET1_IB_DRBL_1_P1 - HQM_QSET0_IB_DRBL_1_P1))
|
||||
#define HQM_QSET_IB_DRBL_2_P1(__n) (HQM_QSET0_IB_DRBL_2_P1 + (__n) \
|
||||
* (HQM_QSET1_IB_DRBL_2_P1 - HQM_QSET0_IB_DRBL_2_P1))
|
||||
#define HQM_QSET_RXQ_DRBL_P0(__n) \
|
||||
(HQM_QSET0_RXQ_DRBL_P0 + (__n) * \
|
||||
(HQM_QSET1_RXQ_DRBL_P0 - HQM_QSET0_RXQ_DRBL_P0))
|
||||
#define HQM_QSET_TXQ_DRBL_P0(__n) \
|
||||
(HQM_QSET0_TXQ_DRBL_P0 + (__n) * \
|
||||
(HQM_QSET1_TXQ_DRBL_P0 - HQM_QSET0_TXQ_DRBL_P0))
|
||||
#define HQM_QSET_IB_DRBL_1_P0(__n) \
|
||||
(HQM_QSET0_IB_DRBL_1_P0 + (__n) * \
|
||||
(HQM_QSET1_IB_DRBL_1_P0 - HQM_QSET0_IB_DRBL_1_P0))
|
||||
#define HQM_QSET_IB_DRBL_2_P0(__n) \
|
||||
(HQM_QSET0_IB_DRBL_2_P0 + (__n) * \
|
||||
(HQM_QSET1_IB_DRBL_2_P0 - HQM_QSET0_IB_DRBL_2_P0))
|
||||
#define HQM_QSET_RXQ_DRBL_P1(__n) \
|
||||
(HQM_QSET0_RXQ_DRBL_P1 + (__n) * \
|
||||
(HQM_QSET1_RXQ_DRBL_P1 - HQM_QSET0_RXQ_DRBL_P1))
|
||||
#define HQM_QSET_TXQ_DRBL_P1(__n) \
|
||||
(HQM_QSET0_TXQ_DRBL_P1 + (__n) * \
|
||||
(HQM_QSET1_TXQ_DRBL_P1 - HQM_QSET0_TXQ_DRBL_P1))
|
||||
#define HQM_QSET_IB_DRBL_1_P1(__n) \
|
||||
(HQM_QSET0_IB_DRBL_1_P1 + (__n) * \
|
||||
(HQM_QSET1_IB_DRBL_1_P1 - HQM_QSET0_IB_DRBL_1_P1))
|
||||
#define HQM_QSET_IB_DRBL_2_P1(__n) \
|
||||
(HQM_QSET0_IB_DRBL_2_P1 + (__n) * \
|
||||
(HQM_QSET1_IB_DRBL_2_P1 - HQM_QSET0_IB_DRBL_2_P1))
|
||||
|
||||
#define CPE_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
|
||||
#define RME_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
|
||||
|
|
|
|||
|
|
@ -32,8 +32,6 @@ extern const u32 bna_napi_dim_vector[][BNA_BIAS_T_MAX];
|
|||
/* Log string size */
|
||||
#define BNA_MESSAGE_SIZE 256
|
||||
|
||||
#define bna_device_timer(_dev) bfa_timer_beat(&((_dev)->timer_mod))
|
||||
|
||||
/* MBOX API for PORT, TX, RX */
|
||||
#define bna_mbox_qe_fill(_qe, _cmd, _cmd_len, _cbfn, _cbarg) \
|
||||
do { \
|
||||
|
|
|
|||
|
|
@ -1425,13 +1425,24 @@ bnad_ioc_hb_check(unsigned long data)
|
|||
}
|
||||
|
||||
static void
|
||||
bnad_ioc_sem_timeout(unsigned long data)
|
||||
bnad_iocpf_timeout(unsigned long data)
|
||||
{
|
||||
struct bnad *bnad = (struct bnad *)data;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&bnad->bna_lock, flags);
|
||||
bfa_nw_ioc_sem_timeout((void *) &bnad->bna.device.ioc);
|
||||
bfa_nw_iocpf_timeout((void *) &bnad->bna.device.ioc);
|
||||
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
||||
}
|
||||
|
||||
static void
|
||||
bnad_iocpf_sem_timeout(unsigned long data)
|
||||
{
|
||||
struct bnad *bnad = (struct bnad *)data;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&bnad->bna_lock, flags);
|
||||
bfa_nw_iocpf_sem_timeout((void *) &bnad->bna.device.ioc);
|
||||
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
||||
}
|
||||
|
||||
|
|
@ -3132,11 +3143,13 @@ bnad_pci_probe(struct pci_dev *pdev,
|
|||
((unsigned long)bnad));
|
||||
setup_timer(&bnad->bna.device.ioc.hb_timer, bnad_ioc_hb_check,
|
||||
((unsigned long)bnad));
|
||||
setup_timer(&bnad->bna.device.ioc.sem_timer, bnad_ioc_sem_timeout,
|
||||
setup_timer(&bnad->bna.device.ioc.iocpf_timer, bnad_iocpf_timeout,
|
||||
((unsigned long)bnad));
|
||||
setup_timer(&bnad->bna.device.ioc.sem_timer, bnad_iocpf_sem_timeout,
|
||||
((unsigned long)bnad));
|
||||
|
||||
/* Now start the timer before calling IOC */
|
||||
mod_timer(&bnad->bna.device.ioc.ioc_timer,
|
||||
mod_timer(&bnad->bna.device.ioc.iocpf_timer,
|
||||
jiffies + msecs_to_jiffies(BNA_IOC_TIMER_FREQ));
|
||||
|
||||
/*
|
||||
|
|
|
|||
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