Blackfin arch: add TWIx_REGBASE and SPIx_REGBASE to specific CPU header files, use the new REGBASE for board platform resources
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
Bryan Wu
Родитель
b7b2d344e7
Коммит
1d487f468d
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@ -21,8 +21,6 @@
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#ifndef _SPI_CHANNEL_H_
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#define _SPI_CHANNEL_H_
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#define SPI0_REGBASE 0xffc00500
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#define SPI_READ 0
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#define SPI_WRITE 1
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@ -102,6 +102,7 @@
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/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
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#define SPI0_REGBASE 0xFFC00500
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#define SPI_CTL 0xFFC00500 /* SPI Control Register */
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#define SPI_FLG 0xFFC00504 /* SPI Flag register */
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#define SPI_STAT 0xFFC00508 /* SPI Status register */
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@ -480,6 +481,7 @@
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/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
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#define TWI0_REGBASE 0xFFC01400
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#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
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#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
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#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
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@ -104,6 +104,7 @@
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#define UART_GCTL 0xFFC00424 /* Global Control Register */
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/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
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#define SPI0_REGBASE 0xFFC00500
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#define SPI_CTL 0xFFC00500 /* SPI Control Register */
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#define SPI_FLG 0xFFC00504 /* SPI Flag register */
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#define SPI_STAT 0xFFC00508 /* SPI Status register */
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@ -86,6 +86,7 @@
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#define UART0_GCTL 0xFFC00424 /* Global Control Register */
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/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
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#define SPI0_REGBASE 0xFFC00500
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#define SPI_CTL 0xFFC00500 /* SPI Control Register */
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#define SPI_FLG 0xFFC00504 /* SPI Flag register */
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#define SPI_STAT 0xFFC00508 /* SPI Status register */
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@ -456,6 +457,7 @@
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#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
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/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
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#define TWI0_REGBASE 0xFFC01400
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#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
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#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
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#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
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@ -81,6 +81,7 @@
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/* Two Wire Interface Registers (TWI1) */
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#define TWI1_REGBASE 0xffc02200
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#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
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#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
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#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
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@ -120,6 +120,7 @@
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/* Two Wire Interface Registers (TWI1) */
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#define TWI1_REGBASE 0xffc02200
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#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
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#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
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#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
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@ -139,6 +140,7 @@
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/* SPI2 Registers */
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#define SPI2_REGBASE 0xffc02400
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#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
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#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
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#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
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@ -121,6 +121,7 @@
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/* Two Wire Interface Registers (TWI1) */
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#define TWI1_REGBASE 0xffc02200
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#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
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#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
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#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
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@ -140,6 +141,7 @@
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/* SPI2 Registers */
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#define SPI2_REGBASE 0xffc02400
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#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
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#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
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#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
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@ -109,6 +109,7 @@
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/* SPI0 Registers */
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#define SPI0_REGBASE 0xffc00500
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#define SPI0_CTL 0xffc00500 /* SPI0 Control Register */
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#define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */
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#define SPI0_STAT 0xffc00508 /* SPI0 Status Register */
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@ -121,6 +122,7 @@
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/* Two Wire Interface Registers (TWI0) */
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#define TWI0_REGBASE 0xffc00700
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#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */
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#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */
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#define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */
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@ -978,6 +980,7 @@
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/* SPI1 Registers */
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#define SPI1_REGBASE 0xffc02300
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#define SPI1_CTL 0xffc02300 /* SPI1 Control Register */
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#define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */
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#define SPI1_STAT 0xffc02308 /* SPI1 Status Register */
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@ -120,6 +120,7 @@
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#define UART_GCTL 0xFFC00424 /* Global Control Register */
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/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
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#define SPI0_REGBASE 0xFFC00500
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#define SPI_CTL 0xFFC00500 /* SPI Control Register */
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#define SPI_FLG 0xFFC00504 /* SPI Flag register */
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#define SPI_STAT 0xFFC00508 /* SPI Status register */
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