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Blackfin arch: add TWIx_REGBASE and SPIx_REGBASE to specific CPU header files, use the new REGBASE for board platform resources 

Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
Bryan Wu 2007-10-11 00:30:56 +08:00
Родитель b7b2d344e7
Коммит 1d487f468d
9 изменённых файлов: 14 добавлений и 2 удалений
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2
include/asm-blackfin/bfin5xx_spi.h
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@ -21,8 +21,6 @@
#ifndef _SPI_CHANNEL_H_ #ifndef _SPI_CHANNEL_H_
#define _SPI_CHANNEL_H_ #define _SPI_CHANNEL_H_
#define SPI0_REGBASE 0xffc00500
#define SPI_READ 0 #define SPI_READ 0
#define SPI_WRITE 1 #define SPI_WRITE 1

2
include/asm-blackfin/mach-bf527/defBF52x_base.h
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@ -102,6 +102,7 @@
/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
#define SPI0_REGBASE 0xFFC00500
#define SPI_CTL 0xFFC00500 /* SPI Control Register */ #define SPI_CTL 0xFFC00500 /* SPI Control Register */
#define SPI_FLG 0xFFC00504 /* SPI Flag register */ #define SPI_FLG 0xFFC00504 /* SPI Flag register */
#define SPI_STAT 0xFFC00508 /* SPI Status register */ #define SPI_STAT 0xFFC00508 /* SPI Status register */
@ -480,6 +481,7 @@
/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
#define TWI0_REGBASE 0xFFC01400
#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ #define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ #define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ #define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */

1
include/asm-blackfin/mach-bf533/defBF532.h
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@ -104,6 +104,7 @@
#define UART_GCTL 0xFFC00424 /* Global Control Register */ #define UART_GCTL 0xFFC00424 /* Global Control Register */
/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
#define SPI0_REGBASE 0xFFC00500
#define SPI_CTL 0xFFC00500 /* SPI Control Register */ #define SPI_CTL 0xFFC00500 /* SPI Control Register */
#define SPI_FLG 0xFFC00504 /* SPI Flag register */ #define SPI_FLG 0xFFC00504 /* SPI Flag register */
#define SPI_STAT 0xFFC00508 /* SPI Status register */ #define SPI_STAT 0xFFC00508 /* SPI Status register */

2
include/asm-blackfin/mach-bf537/defBF534.h
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@ -86,6 +86,7 @@
#define UART0_GCTL 0xFFC00424 /* Global Control Register */ #define UART0_GCTL 0xFFC00424 /* Global Control Register */
/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
#define SPI0_REGBASE 0xFFC00500
#define SPI_CTL 0xFFC00500 /* SPI Control Register */ #define SPI_CTL 0xFFC00500 /* SPI Control Register */
#define SPI_FLG 0xFFC00504 /* SPI Flag register */ #define SPI_FLG 0xFFC00504 /* SPI Flag register */
#define SPI_STAT 0xFFC00508 /* SPI Status register */ #define SPI_STAT 0xFFC00508 /* SPI Status register */
@ -456,6 +457,7 @@
#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
#define TWI0_REGBASE 0xFFC01400
#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ #define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ #define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ #define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */

1
include/asm-blackfin/mach-bf548/defBF544.h
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@ -81,6 +81,7 @@
/* Two Wire Interface Registers (TWI1) */ /* Two Wire Interface Registers (TWI1) */
#define TWI1_REGBASE 0xffc02200
#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */

2
include/asm-blackfin/mach-bf548/defBF548.h
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@ -120,6 +120,7 @@
/* Two Wire Interface Registers (TWI1) */ /* Two Wire Interface Registers (TWI1) */
#define TWI1_REGBASE 0xffc02200
#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
@ -139,6 +140,7 @@
/* SPI2 Registers */ /* SPI2 Registers */
#define SPI2_REGBASE 0xffc02400
#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ #define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ #define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ #define SPI2_STAT 0xffc02408 /* SPI2 Status Register */

2
include/asm-blackfin/mach-bf548/defBF549.h
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@ -121,6 +121,7 @@
/* Two Wire Interface Registers (TWI1) */ /* Two Wire Interface Registers (TWI1) */
#define TWI1_REGBASE 0xffc02200
#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
@ -140,6 +141,7 @@
/* SPI2 Registers */ /* SPI2 Registers */
#define SPI2_REGBASE 0xffc02400
#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ #define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ #define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ #define SPI2_STAT 0xffc02408 /* SPI2 Status Register */

3
include/asm-blackfin/mach-bf548/defBF54x_base.h
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@ -109,6 +109,7 @@
/* SPI0 Registers */ /* SPI0 Registers */
#define SPI0_REGBASE 0xffc00500
#define SPI0_CTL 0xffc00500 /* SPI0 Control Register */ #define SPI0_CTL 0xffc00500 /* SPI0 Control Register */
#define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */ #define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */
#define SPI0_STAT 0xffc00508 /* SPI0 Status Register */ #define SPI0_STAT 0xffc00508 /* SPI0 Status Register */
@ -121,6 +122,7 @@
/* Two Wire Interface Registers (TWI0) */ /* Two Wire Interface Registers (TWI0) */
#define TWI0_REGBASE 0xffc00700
#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */ #define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */
#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */ #define TWI0_CONTROL 0xffc00704 /* TWI Control Register */
#define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */ #define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */
@ -978,6 +980,7 @@
/* SPI1 Registers */ /* SPI1 Registers */
#define SPI1_REGBASE 0xffc02300
#define SPI1_CTL 0xffc02300 /* SPI1 Control Register */ #define SPI1_CTL 0xffc02300 /* SPI1 Control Register */
#define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */ #define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */
#define SPI1_STAT 0xffc02308 /* SPI1 Status Register */ #define SPI1_STAT 0xffc02308 /* SPI1 Status Register */

1
include/asm-blackfin/mach-bf561/defBF561.h
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@ -120,6 +120,7 @@
#define UART_GCTL 0xFFC00424 /* Global Control Register */ #define UART_GCTL 0xFFC00424 /* Global Control Register */
/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
#define SPI0_REGBASE 0xFFC00500
#define SPI_CTL 0xFFC00500 /* SPI Control Register */ #define SPI_CTL 0xFFC00500 /* SPI Control Register */
#define SPI_FLG 0xFFC00504 /* SPI Flag register */ #define SPI_FLG 0xFFC00504 /* SPI Flag register */
#define SPI_STAT 0xFFC00508 /* SPI Status register */ #define SPI_STAT 0xFFC00508 /* SPI Status register */