MIPS: smp-cps: hotplug support
This patch adds support for offlining CPUs via hotplug when using the
CONFIG_MIPS_CPS SMP implementation. When a CPU is offlined one of 2
things will happen:
- If the CPU is part of a core which implements the MT ASE and there
is at least one other VPE online within that core then the VPE will
be halted by settings its TCHalt bit.
- Otherwise if supported the core will be powered down via the CPC.
- Otherwise the CPU will hang by executing an infinite loop.
Bringing CPUs back online is then a process of either clearing the
appropriate VPEs TCHalt bit or powering up the appropriate core via the
CPC. Throughout the process the struct core_boot_config vpe_mask field
must be maintained such that mips_cps_boot_vpes will start & stop the
correct VPEs.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
This commit is contained in:
Paul Burton
Родитель
3179d37ee1
Коммит
1d8f1f5a78
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@ -2059,9 +2059,11 @@ config MIPS_CPS
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depends on SYS_SUPPORTS_MIPS_CPS
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select MIPS_CM
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select MIPS_CPC
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select MIPS_CPS_PM if HOTPLUG_CPU
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select MIPS_GIC_IPI
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select SMP
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select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
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select SYS_SUPPORTS_HOTPLUG_CPU
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select SYS_SUPPORTS_SMP
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select WEAK_ORDERING
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help
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@ -20,6 +20,7 @@
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#include <asm/mips-cpc.h>
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#include <asm/mips_mt.h>
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#include <asm/mipsregs.h>
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#include <asm/pm-cps.h>
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#include <asm/smp-cps.h>
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#include <asm/time.h>
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#include <asm/uasm.h>
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@ -194,10 +195,12 @@ static void cps_boot_secondary(int cpu, struct task_struct *idle)
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atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
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preempt_disable();
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if (!test_bit(core, core_power)) {
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/* Boot a VPE on a powered down core */
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boot_core(core);
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return;
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goto out;
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}
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if (core != current_cpu_data.core) {
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@ -214,13 +217,15 @@ static void cps_boot_secondary(int cpu, struct task_struct *idle)
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NULL, 1);
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if (err)
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panic("Failed to call remote CPU\n");
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return;
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goto out;
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}
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BUG_ON(!cpu_has_mipsmt);
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/* Boot a VPE on this core */
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mips_cps_boot_vpes();
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out:
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preempt_enable();
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}
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static void cps_init_secondary(void)
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@ -250,6 +255,148 @@ static void cps_cpus_done(void)
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{
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static int cps_cpu_disable(void)
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{
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unsigned cpu = smp_processor_id();
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struct core_boot_config *core_cfg;
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if (!cpu)
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return -EBUSY;
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if (!cps_pm_support_state(CPS_PM_POWER_GATED))
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return -EINVAL;
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core_cfg = &mips_cps_core_bootcfg[current_cpu_data.core];
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atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask);
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smp_mb__after_atomic_dec();
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set_cpu_online(cpu, false);
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cpu_clear(cpu, cpu_callin_map);
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return 0;
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}
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static DECLARE_COMPLETION(cpu_death_chosen);
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static unsigned cpu_death_sibling;
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static enum {
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CPU_DEATH_HALT,
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CPU_DEATH_POWER,
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} cpu_death;
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void play_dead(void)
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{
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unsigned cpu, core;
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local_irq_disable();
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idle_task_exit();
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cpu = smp_processor_id();
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cpu_death = CPU_DEATH_POWER;
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if (cpu_has_mipsmt) {
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core = cpu_data[cpu].core;
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/* Look for another online VPE within the core */
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for_each_online_cpu(cpu_death_sibling) {
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if (cpu_data[cpu_death_sibling].core != core)
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continue;
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/*
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* There is an online VPE within the core. Just halt
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* this TC and leave the core alone.
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*/
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cpu_death = CPU_DEATH_HALT;
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break;
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}
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}
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/* This CPU has chosen its way out */
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complete(&cpu_death_chosen);
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if (cpu_death == CPU_DEATH_HALT) {
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/* Halt this TC */
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write_c0_tchalt(TCHALT_H);
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instruction_hazard();
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} else {
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/* Power down the core */
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cps_pm_enter_state(CPS_PM_POWER_GATED);
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}
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/* This should never be reached */
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panic("Failed to offline CPU %u", cpu);
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}
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static void wait_for_sibling_halt(void *ptr_cpu)
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{
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unsigned cpu = (unsigned)ptr_cpu;
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unsigned vpe_id = cpu_data[cpu].vpe_id;
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unsigned halted;
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unsigned long flags;
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do {
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local_irq_save(flags);
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settc(vpe_id);
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halted = read_tc_c0_tchalt();
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local_irq_restore(flags);
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} while (!(halted & TCHALT_H));
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}
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static void cps_cpu_die(unsigned int cpu)
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{
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unsigned core = cpu_data[cpu].core;
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unsigned stat;
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int err;
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/* Wait for the cpu to choose its way out */
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if (!wait_for_completion_timeout(&cpu_death_chosen,
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msecs_to_jiffies(5000))) {
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pr_err("CPU%u: didn't offline\n", cpu);
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return;
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}
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/*
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* Now wait for the CPU to actually offline. Without doing this that
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* offlining may race with one or more of:
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*
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* - Onlining the CPU again.
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* - Powering down the core if another VPE within it is offlined.
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* - A sibling VPE entering a non-coherent state.
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*
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* In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
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* with which we could race, so do nothing.
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*/
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if (cpu_death == CPU_DEATH_POWER) {
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/*
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* Wait for the core to enter a powered down or clock gated
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* state, the latter happening when a JTAG probe is connected
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* in which case the CPC will refuse to power down the core.
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*/
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do {
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mips_cpc_lock_other(core);
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stat = read_cpc_co_stat_conf();
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stat &= CPC_Cx_STAT_CONF_SEQSTATE_MSK;
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mips_cpc_unlock_other();
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} while (stat != CPC_Cx_STAT_CONF_SEQSTATE_D0 &&
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stat != CPC_Cx_STAT_CONF_SEQSTATE_D2 &&
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stat != CPC_Cx_STAT_CONF_SEQSTATE_U2);
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/* Indicate the core is powered off */
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bitmap_clear(core_power, core, 1);
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} else if (cpu_has_mipsmt) {
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/*
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* Have a CPU with access to the offlined CPUs registers wait
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* for its TC to halt.
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*/
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err = smp_call_function_single(cpu_death_sibling,
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wait_for_sibling_halt,
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(void *)cpu, 1);
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if (err)
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panic("Failed to call remote sibling CPU\n");
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}
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}
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#endif /* CONFIG_HOTPLUG_CPU */
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static struct plat_smp_ops cps_smp_ops = {
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.smp_setup = cps_smp_setup,
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.prepare_cpus = cps_prepare_cpus,
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@ -259,6 +406,10 @@ static struct plat_smp_ops cps_smp_ops = {
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.send_ipi_single = gic_send_ipi_single,
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.send_ipi_mask = gic_send_ipi_mask,
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.cpus_done = cps_cpus_done,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_disable = cps_cpu_disable,
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.cpu_die = cps_cpu_die,
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#endif
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};
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bool mips_cps_smp_in_use(void)
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