ARM: ux500: move PM-related PRCMU functions to machine
We are trying to decompose and decentralize the code in the DB8500 PRCMU out into subdrivers. The code moved in this patch concerns a group of functions used for decoupling and recoupling the IRQs from the GIC. During sleep and idle the Ux500 system will transfer all IRQ handling to the PRCMU using these functions. Basically we are left with the two alternatives of code placement as: - arch/arm/mach-ux500/pm.c - this because the code is closely related to the GIC, and takes ownership of some of the registers from the PRCMU related to this PM functionality. - drivers/mfd/db8500-prcmu-pm.c - because the code is affecting stuff in the PRCMU register range. But then this code needs to remap and handle GIC registers. This patch implementation is taking the first approach. Currently the cpuidle driver is the only piece of code using this set of functions, but it will later also be used by the suspend/resume code which is currently under review. The header file is moved to: <linux/platform_data/arm-ux500-pm.h> The function prototypes need to be placed in a globally visible header since the CPUidle code is planned to move out to drivers/cpuidle. Acked-by: Samuel Ortiz <sameo@linux.intel.com> Acked-by: Rickard Andersson <rickard.andersson@stericsson.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
Родитель
b047d98127
Коммит
1e22a8c614
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@ -3,7 +3,7 @@
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#
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obj-y := cpu.o devices.o devices-common.o \
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id.o usb.o timer.o
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id.o usb.o timer.o pm.o
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obj-$(CONFIG_CPU_IDLE) += cpuidle.o
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obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
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obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o
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@ -20,6 +20,7 @@
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#include <linux/irqchip.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/platform_data/clk-ux500.h>
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#include <linux/platform_data/arm-ux500-pm.h>
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#include <asm/mach/map.h>
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@ -68,12 +69,15 @@ void __init ux500_init_irq(void)
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*/
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if (cpu_is_u8500_family()) {
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prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
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ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
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u8500_clk_init();
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} else if (cpu_is_u9540()) {
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prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
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ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
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u8500_clk_init();
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} else if (cpu_is_u8540()) {
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prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
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ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
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u8540_clk_init();
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}
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}
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@ -16,6 +16,7 @@
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#include <linux/atomic.h>
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#include <linux/smp.h>
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#include <linux/mfd/dbx500-prcmu.h>
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#include <linux/platform_data/arm-ux500-pm.h>
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#include <asm/cpuidle.h>
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#include <asm/proc-fns.h>
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@ -0,0 +1,167 @@
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/*
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* Copyright (C) ST-Ericsson SA 2010-2013
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* Author: Rickard Andersson <rickard.andersson@stericsson.com> for
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* ST-Ericsson.
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* Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro.
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* License terms: GNU General Public License (GPL) version 2
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*
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*/
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#include <linux/kernel.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/platform_data/arm-ux500-pm.h>
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#include <mach/hardware.h>
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/* ARM WFI Standby signal register */
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#define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130)
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#define PRCM_ARM_WFI_STANDBY_WFI0 0x08
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#define PRCM_ARM_WFI_STANDBY_WFI1 0x10
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#define PRCM_IOCR (prcmu_base + 0x310)
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#define PRCM_IOCR_IOFORCE 0x1
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/* Dual A9 core interrupt management unit registers */
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#define PRCM_A9_MASK_REQ (prcmu_base + 0x328)
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#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1
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#define PRCM_A9_MASK_ACK (prcmu_base + 0x32c)
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#define PRCM_ARMITMSK31TO0 (prcmu_base + 0x11c)
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#define PRCM_ARMITMSK63TO32 (prcmu_base + 0x120)
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#define PRCM_ARMITMSK95TO64 (prcmu_base + 0x124)
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#define PRCM_ARMITMSK127TO96 (prcmu_base + 0x128)
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#define PRCM_POWER_STATE_VAL (prcmu_base + 0x25C)
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#define PRCM_ARMITVAL31TO0 (prcmu_base + 0x260)
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#define PRCM_ARMITVAL63TO32 (prcmu_base + 0x264)
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#define PRCM_ARMITVAL95TO64 (prcmu_base + 0x268)
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#define PRCM_ARMITVAL127TO96 (prcmu_base + 0x26C)
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static void __iomem *prcmu_base;
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/* This function decouple the gic from the prcmu */
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int prcmu_gic_decouple(void)
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{
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u32 val = readl(PRCM_A9_MASK_REQ);
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/* Set bit 0 register value to 1 */
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writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
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PRCM_A9_MASK_REQ);
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/* Make sure the register is updated */
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readl(PRCM_A9_MASK_REQ);
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/* Wait a few cycles for the gic mask completion */
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udelay(1);
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return 0;
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}
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/* This function recouple the gic with the prcmu */
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int prcmu_gic_recouple(void)
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{
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u32 val = readl(PRCM_A9_MASK_REQ);
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/* Set bit 0 register value to 0 */
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writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
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return 0;
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}
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#define PRCMU_GIC_NUMBER_REGS 5
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/*
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* This function checks if there are pending irq on the gic. It only
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* makes sense if the gic has been decoupled before with the
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* db8500_prcmu_gic_decouple function. Disabling an interrupt only
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* disables the forwarding of the interrupt to any CPU interface. It
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* does not prevent the interrupt from changing state, for example
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* becoming pending, or active and pending if it is already
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* active. Hence, we have to check the interrupt is pending *and* is
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* active.
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*/
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bool prcmu_gic_pending_irq(void)
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{
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u32 pr; /* Pending register */
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u32 er; /* Enable register */
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void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
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int i;
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/* 5 registers. STI & PPI not skipped */
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for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {
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pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
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er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
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if (pr & er)
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return true; /* There is a pending interrupt */
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}
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return false;
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}
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/*
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* This function checks if there are pending interrupt on the
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* prcmu which has been delegated to monitor the irqs with the
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* db8500_prcmu_copy_gic_settings function.
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*/
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bool prcmu_pending_irq(void)
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{
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u32 it, im;
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int i;
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for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
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it = readl(PRCM_ARMITVAL31TO0 + i * 4);
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im = readl(PRCM_ARMITMSK31TO0 + i * 4);
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if (it & im)
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return true; /* There is a pending interrupt */
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}
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return false;
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}
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/*
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* This function checks if the specified cpu is in in WFI. It's usage
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* makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
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* function. Of course passing smp_processor_id() to this function will
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* always return false...
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*/
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bool prcmu_is_cpu_in_wfi(int cpu)
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{
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return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 :
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PRCM_ARM_WFI_STANDBY_WFI0;
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}
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/*
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* This function copies the gic SPI settings to the prcmu in order to
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* monitor them and abort/finish the retention/off sequence or state.
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*/
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int prcmu_copy_gic_settings(void)
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{
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u32 er; /* Enable register */
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void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
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int i;
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/* We skip the STI and PPI */
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for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
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er = readl_relaxed(dist_base +
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GIC_DIST_ENABLE_SET + (i + 1) * 4);
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writel(er, PRCM_ARMITMSK31TO0 + i * 4);
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}
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return 0;
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}
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void __init ux500_pm_init(u32 phy_base, u32 size)
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{
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prcmu_base = ioremap(phy_base, size);
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if (!prcmu_base) {
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pr_err("could not remap PRCMU for PM functions\n");
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return;
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}
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/*
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* On watchdog reboot the GIC is in some cases decoupled.
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* This will make sure that the GIC is correctly configured.
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*/
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prcmu_gic_recouple();
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}
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@ -26,7 +26,6 @@
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#include <linux/fs.h>
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#include <linux/platform_device.h>
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#include <linux/uaccess.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/dbx500-prcmu.h>
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#include <linux/mfd/abx500/ab8500.h>
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@ -794,119 +793,6 @@ u8 db8500_prcmu_get_power_state_result(void)
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return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
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}
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/* This function decouple the gic from the prcmu */
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int db8500_prcmu_gic_decouple(void)
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{
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u32 val = readl(PRCM_A9_MASK_REQ);
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/* Set bit 0 register value to 1 */
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writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
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PRCM_A9_MASK_REQ);
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/* Make sure the register is updated */
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readl(PRCM_A9_MASK_REQ);
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/* Wait a few cycles for the gic mask completion */
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udelay(1);
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return 0;
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}
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/* This function recouple the gic with the prcmu */
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int db8500_prcmu_gic_recouple(void)
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{
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u32 val = readl(PRCM_A9_MASK_REQ);
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/* Set bit 0 register value to 0 */
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writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
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return 0;
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}
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#define PRCMU_GIC_NUMBER_REGS 5
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/*
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* This function checks if there are pending irq on the gic. It only
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* makes sense if the gic has been decoupled before with the
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* db8500_prcmu_gic_decouple function. Disabling an interrupt only
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* disables the forwarding of the interrupt to any CPU interface. It
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* does not prevent the interrupt from changing state, for example
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* becoming pending, or active and pending if it is already
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* active. Hence, we have to check the interrupt is pending *and* is
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* active.
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*/
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bool db8500_prcmu_gic_pending_irq(void)
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{
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u32 pr; /* Pending register */
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u32 er; /* Enable register */
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void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
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int i;
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/* 5 registers. STI & PPI not skipped */
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for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {
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pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
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er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
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if (pr & er)
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return true; /* There is a pending interrupt */
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}
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return false;
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}
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/*
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* This function checks if there are pending interrupt on the
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* prcmu which has been delegated to monitor the irqs with the
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* db8500_prcmu_copy_gic_settings function.
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*/
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bool db8500_prcmu_pending_irq(void)
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{
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u32 it, im;
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int i;
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for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
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it = readl(PRCM_ARMITVAL31TO0 + i * 4);
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im = readl(PRCM_ARMITMSK31TO0 + i * 4);
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if (it & im)
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return true; /* There is a pending interrupt */
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}
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return false;
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}
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/*
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* This function checks if the specified cpu is in in WFI. It's usage
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* makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
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* function. Of course passing smp_processor_id() to this function will
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* always return false...
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*/
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bool db8500_prcmu_is_cpu_in_wfi(int cpu)
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{
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return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 :
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PRCM_ARM_WFI_STANDBY_WFI0;
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}
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/*
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* This function copies the gic SPI settings to the prcmu in order to
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* monitor them and abort/finish the retention/off sequence or state.
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*/
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int db8500_prcmu_copy_gic_settings(void)
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{
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u32 er; /* Enable register */
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void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
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int i;
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/* We skip the STI and PPI */
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for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
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er = readl_relaxed(dist_base +
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GIC_DIST_ENABLE_SET + (i + 1) * 4);
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writel(er, PRCM_ARMITMSK31TO0 + i * 4);
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}
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return 0;
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}
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/* This function should only be called while mb0_transfer.lock is held. */
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static void config_wakeups(void)
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{
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@ -74,33 +74,11 @@
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#define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0)
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#define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1)
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/* ARM WFI Standby signal register */
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#define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130)
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#define PRCM_ARM_WFI_STANDBY_WFI0 0x08
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#define PRCM_ARM_WFI_STANDBY_WFI1 0x10
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#define PRCM_IOCR (prcmu_base + 0x310)
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#define PRCM_IOCR_IOFORCE 0x1
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/* CPU mailbox registers */
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#define PRCM_MBOX_CPU_VAL (prcmu_base + 0x0fc)
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#define PRCM_MBOX_CPU_SET (prcmu_base + 0x100)
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#define PRCM_MBOX_CPU_CLR (prcmu_base + 0x104)
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/* Dual A9 core interrupt management unit registers */
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#define PRCM_A9_MASK_REQ (prcmu_base + 0x328)
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#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1
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#define PRCM_A9_MASK_ACK (prcmu_base + 0x32c)
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#define PRCM_ARMITMSK31TO0 (prcmu_base + 0x11c)
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#define PRCM_ARMITMSK63TO32 (prcmu_base + 0x120)
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#define PRCM_ARMITMSK95TO64 (prcmu_base + 0x124)
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#define PRCM_ARMITMSK127TO96 (prcmu_base + 0x128)
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#define PRCM_POWER_STATE_VAL (prcmu_base + 0x25C)
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#define PRCM_ARMITVAL31TO0 (prcmu_base + 0x260)
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#define PRCM_ARMITVAL63TO32 (prcmu_base + 0x264)
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#define PRCM_ARMITVAL95TO64 (prcmu_base + 0x268)
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#define PRCM_ARMITVAL127TO96 (prcmu_base + 0x26C)
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#define PRCM_HOSTACCESS_REQ (prcmu_base + 0x334)
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#define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ 0x1
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#define PRCM_HOSTACCESS_REQ_WAKE_REQ BIT(16)
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@ -522,12 +522,6 @@ int db8500_prcmu_load_a9wdog(u8 id, u32 val);
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void db8500_prcmu_system_reset(u16 reset_code);
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int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
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u8 db8500_prcmu_get_power_state_result(void);
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int db8500_prcmu_gic_decouple(void);
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int db8500_prcmu_gic_recouple(void);
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int db8500_prcmu_copy_gic_settings(void);
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bool db8500_prcmu_gic_pending_irq(void);
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bool db8500_prcmu_pending_irq(void);
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bool db8500_prcmu_is_cpu_in_wfi(int cpu);
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void db8500_prcmu_enable_wakeups(u32 wakeups);
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int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
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int db8500_prcmu_request_clock(u8 clock, bool enable);
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@ -293,36 +293,6 @@ static inline u8 prcmu_get_power_state_result(void)
|
|||
return db8500_prcmu_get_power_state_result();
|
||||
}
|
||||
|
||||
static inline int prcmu_gic_decouple(void)
|
||||
{
|
||||
return db8500_prcmu_gic_decouple();
|
||||
}
|
||||
|
||||
static inline int prcmu_gic_recouple(void)
|
||||
{
|
||||
return db8500_prcmu_gic_recouple();
|
||||
}
|
||||
|
||||
static inline bool prcmu_gic_pending_irq(void)
|
||||
{
|
||||
return db8500_prcmu_gic_pending_irq();
|
||||
}
|
||||
|
||||
static inline bool prcmu_is_cpu_in_wfi(int cpu)
|
||||
{
|
||||
return db8500_prcmu_is_cpu_in_wfi(cpu);
|
||||
}
|
||||
|
||||
static inline int prcmu_copy_gic_settings(void)
|
||||
{
|
||||
return db8500_prcmu_copy_gic_settings();
|
||||
}
|
||||
|
||||
static inline bool prcmu_pending_irq(void)
|
||||
{
|
||||
return db8500_prcmu_pending_irq();
|
||||
}
|
||||
|
||||
static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
|
||||
{
|
||||
return db8500_prcmu_set_epod(epod_id, epod_state);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* Copyright (C) ST-Ericsson SA 2010-2013
|
||||
* Author: Rickard Andersson <rickard.andersson@stericsson.com> for
|
||||
* ST-Ericsson.
|
||||
* Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro.
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef ARM_UX500_PM_H
|
||||
#define ARM_UX500_PM_H
|
||||
|
||||
int prcmu_gic_decouple(void);
|
||||
int prcmu_gic_recouple(void);
|
||||
bool prcmu_gic_pending_irq(void);
|
||||
bool prcmu_pending_irq(void);
|
||||
bool prcmu_is_cpu_in_wfi(int cpu);
|
||||
int prcmu_copy_gic_settings(void);
|
||||
void ux500_pm_init(u32 phy_base, u32 size);
|
||||
|
||||
#endif /* ARM_UX500_PM_H */
|
||||
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