arm64: dts: qcom: msm8998: Enumerate i2c controllers
msm8998 has a dozen i2c controllers which can be used to connect to board specific peripherals. Enumerate the controllers so that boards can wire up as needed. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> [bjorn: Renumbered labels on BLSP2 nodes] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Jeffrey Hugo
Andy Gross
Родитель
d558f4c2c4
Коммит
1e71d0c273
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@ -624,6 +624,186 @@
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status = "disabled";
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};
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blsp1_i2c1: i2c@c175000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x0c175000 0x600>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <400000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp1_i2c2: i2c@c176000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x0c176000 0x600>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <400000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp1_i2c3: i2c@c177000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x0c177000 0x600>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <400000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp1_i2c4: i2c@c178000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x0c178000 0x600>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <400000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp1_i2c5: i2c@c179000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x0c179000 0x600>;
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <400000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp1_i2c6: i2c@c17a000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x0c17a000 0x600>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <400000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp2_i2c0: i2c@c1b5000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x0c1b5000 0x600>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
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<&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <400000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp2_i2c1: i2c@c1b6000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x0c1b6000 0x600>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
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<&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <400000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp2_i2c2: i2c@c1b7000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x0c1b7000 0x600>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
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<&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <400000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp2_i2c3: i2c@c1b8000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x0c1b8000 0x600>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
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<&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <400000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp2_i2c4: i2c@c1b9000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x0c1b9000 0x600>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
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<&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <400000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp2_i2c5: i2c@c1ba000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x0c175000 0x600>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
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<&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <400000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp2_uart1: serial@c1b0000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0xc1b0000 0x1000>;
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