Power, reset and clock related changes via Paul Walmsley <paul@pwsan.com>:

Some low-level optimizations and fixes that don't belong in an -rc
 series for various OMAP-family chips, targeted for v3.15.
 
 Basic build, boot, and PM test logs are available here:
 
 http://www.pwsan.com/omap/testlogs/prcm-a-for-v3.15/20140228124518/
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.15 (GNU/Linux)
 
 iQIcBAABAgAGBQJTE7pTAAoJEBvUPslcq6VzJqkP/2spS9ijHH9zwCjhydS1FNpc
 V7ZV2cN12/6nVyzijSFXnVRgXNJ6TAkWiuPoUThnWpTI4cTy0SQEJPB9dkSBLdqj
 mjmSisQFXJLpasiR5paV1P8rtNffKHq53fvuRx9gGsucxPMOBmH8ZQ6Mn3XXgcGX
 N7ax31bE8/ZIWmheIfSXrVZ5LM/v1iSDYB3DbY3vIu3OJ8iRLinB6+e45qvRSxhM
 dSzCf7inFXRjAfpUQzeiHKay4oTBAesFv4tzSgDP5Xsew7p+Qu3C9+5ey9cHRWDB
 XhkjmlsoRjb46ElLRzLMAHBA3IwgFpMrhF03FvRqWf4T7N16CsjXeeC18c3CsRBG
 X4E175dq0P1fn5CPJ+B5ayhZSFx2RehADlE2ZCsE0N7o/Jp3mYB+vKXtOeyUXTy2
 klQRGyLBg5yEtVY+yDBsIsNFfBvDkD5ar3CnI2DVTglQ5I4Iwh7YP00nGstYPWka
 T6dRPiKCLJlRmtmldgr2QdYt6+o80tb17J0fpxcjhBNmGNoqDBoNk4XaJVY6unjC
 ZWfN81dikQj0HNl1Z1Aa/fxHSp6nfi36gWFXyk1FeNU5y/LCI0eXuVXuNwjPn/u5
 V0Z7nqllZkELkB7jv1p9/HkTMBg5mZDRGahBxG/LY051O2m7qKk0BZiE5nfNH2g7
 3sBdbu6mzHoL/X+Benoq
 =+YmH
 -----END PGP SIGNATURE-----

Merge tag 'omap-for-v3.15/prcm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc

Power, reset and clock related changes via Paul Walmsley <paul@pwsan.com>, via
Tony Lindgren:

Some low-level optimizations and fixes that don't belong in an -rc
series for various OMAP-family chips, targeted for v3.15.

Basic build, boot, and PM test logs are available here:

http://www.pwsan.com/omap/testlogs/prcm-a-for-v3.15/20140228124518/

* tag 'omap-for-v3.15/prcm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP3+: DPLL: stop reparenting to same parent if already done
  ARM: OMAP2+: clock: fix rate prints
  ARM: AM43x: hwmod data: register spinlock OCP interface
  ARM: OMAP2+: clockdomain: Reintroduce SW_SLEEP Support
  ARM: OMAP2+: AM43xx: implement support for machine restart

Signed-off-by: Olof Johansson <olof@lixom.net>

arch/arm/mach-omap2/Makefile

@@ -60,6 +60,7 @@ AFLAGS_sram34xx.o			:=-Wa,-march=armv7-a
 obj-$(CONFIG_SOC_OMAP2420)		+= omap2-restart.o
 obj-$(CONFIG_SOC_OMAP2430)		+= omap2-restart.o
 obj-$(CONFIG_SOC_AM33XX)		+= am33xx-restart.o
+obj-$(CONFIG_SOC_AM43XX)		+= omap4-restart.o
 obj-$(CONFIG_ARCH_OMAP3)		+= omap3-restart.o
 obj-$(CONFIG_ARCH_OMAP4)		+= omap4-restart.o
 obj-$(CONFIG_SOC_OMAP5)			+= omap4-restart.o

arch/arm/mach-omap2/board-generic.c

@@ -231,6 +231,7 @@ DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
 	.init_machine	= omap_generic_init,
 	.init_time	= omap3_gptimer_timer_init,
 	.dt_compat	= am43_boards_compat,
+	.restart	= omap44xx_restart,
 MACHINE_END
 #endif
 

arch/arm/mach-omap2/clkt_dpll.c

@@ -306,7 +306,7 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
 
 	ref_rate = __clk_get_rate(dd->clk_ref);
 	clk_name = __clk_get_name(hw->clk);
-	pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
+	pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
 		 clk_name, target_rate);
 
 	scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
@@ -342,7 +342,7 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
 		if (r == DPLL_MULT_UNDERFLOW)
 			continue;
 
-		pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
+		pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n",
 			 clk_name, m, n, new_rate);
 
 		if (target_rate == new_rate) {
@@ -354,7 +354,7 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
 	}
 
 	if (target_rate != new_rate) {
-		pr_debug("clock: %s: cannot round to rate %ld\n",
+		pr_debug("clock: %s: cannot round to rate %lu\n",
 			 clk_name, target_rate);
 		return ~0;
 	}

arch/arm/mach-omap2/cminst44xx.c

@@ -254,6 +254,11 @@ void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs)
  *
  */
 
+void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs)
+{
+	_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
+}
+
 /**
  * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state
  * @part: PRCM partition ID that the CM_CLKCTRL register exists in
@@ -404,8 +409,17 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
 
 static int omap4_clkdm_sleep(struct clockdomain *clkdm)
 {
-	omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
-					clkdm->cm_inst, clkdm->clkdm_offs);
+	if (clkdm->flags & CLKDM_CAN_HWSUP)
+		omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
+						clkdm->cm_inst,
+						clkdm->clkdm_offs);
+	else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
+		omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
+					       clkdm->cm_inst,
+					       clkdm->clkdm_offs);
+	else
+		return -EINVAL;
+
 	return 0;
 }
 

arch/arm/mach-omap2/dpll3xxx.c

@@ -525,7 +525,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
 	* stuff is inherited for free
 	*/
 
-	if (!ret)
+	if (!ret && clk_get_parent(hw->clk) != new_parent)
 		__clk_reparent(hw->clk, new_parent);
 
 	return 0;

arch/arm/mach-omap2/omap_hwmod_43xx_data.c

@@ -719,6 +719,7 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
 	&am33xx_l4_ls__uart4,
 	&am33xx_l4_ls__uart5,
 	&am33xx_l4_ls__uart6,
+	&am33xx_l4_ls__spinlock,
 	&am33xx_l4_ls__elm,
 	&am33xx_l4_ls__epwmss0,
 	&am33xx_epwmss0__ecap0,

arch/arm/mach-omap2/prminst44xx.c

@@ -25,6 +25,7 @@
 #include "prminst44xx.h"
 #include "prm-regbits-44xx.h"
 #include "prcm44xx.h"
+#include "prcm43xx.h"
 #include "prcm_mpu44xx.h"
 #include "soc.h"
 
@@ -176,6 +177,8 @@ void omap4_prminst_global_warm_sw_reset(void)
 		dev_inst = OMAP54XX_PRM_DEVICE_INST;
 	else if (soc_is_dra7xx())
 		dev_inst = DRA7XX_PRM_DEVICE_INST;
+	else if (soc_is_am43xx())
+		dev_inst = AM43XX_PRM_DEVICE_INST;
 	else
 		return;