PCI: mobiveil: Add MSI support
Implement MSI support for Mobiveil PCIe Host Bridge IP device driver. Signed-off-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Subrahmanya Lingappa
Bjorn Helgaas
Родитель
9af6bcb11e
Коммит
1e913e5833
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@ -14,6 +14,7 @@
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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@ -56,6 +57,7 @@
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#define PAB_INTP_AMBA_MISC_ENB 0x0b0c
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#define PAB_INTP_AMBA_MISC_STAT 0x0b1c
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#define PAB_INTP_INTX_MASK 0x01e0
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#define PAB_INTP_MSI_MASK 0x8
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#define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win)
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#define WIN_ENABLE_SHIFT 0
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@ -86,6 +88,19 @@
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/* starting offset of INTX bits in status register */
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#define PAB_INTX_START 5
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/* supported number of MSI interrupts */
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#define PCI_NUM_MSI 16
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/* MSI registers */
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#define MSI_BASE_LO_OFFSET 0x04
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#define MSI_BASE_HI_OFFSET 0x08
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#define MSI_SIZE_OFFSET 0x0c
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#define MSI_ENABLE_OFFSET 0x14
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#define MSI_STATUS_OFFSET 0x18
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#define MSI_DATA_OFFSET 0x20
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#define MSI_ADDR_L_OFFSET 0x24
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#define MSI_ADDR_H_OFFSET 0x28
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/* outbound and inbound window definitions */
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#define WIN_NUM_0 0
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#define WIN_NUM_1 1
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@ -100,11 +115,21 @@
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#define LINK_WAIT_MIN 90000
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#define LINK_WAIT_MAX 100000
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struct mobiveil_msi { /* MSI information */
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struct mutex lock; /* protect bitmap variable */
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struct irq_domain *msi_domain;
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struct irq_domain *dev_domain;
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phys_addr_t msi_pages_phys;
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int num_of_vectors;
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DECLARE_BITMAP(msi_irq_in_use, PCI_NUM_MSI);
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};
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struct mobiveil_pcie {
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struct platform_device *pdev;
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struct list_head resources;
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void __iomem *config_axi_slave_base; /* endpoint config base */
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void __iomem *csr_axi_slave_base; /* root port config base */
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void __iomem *apb_csr_base; /* MSI register base */
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void __iomem *pcie_reg_base; /* Physical PCIe Controller Base */
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struct irq_domain *intx_domain;
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raw_spinlock_t intx_mask_lock;
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@ -115,6 +140,7 @@ struct mobiveil_pcie {
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int ib_wins_configured; /* configured inbound windows */
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struct resource *ob_io_res;
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char root_bus_nr;
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struct mobiveil_msi msi;
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};
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static inline void csr_writel(struct mobiveil_pcie *pcie, const u32 value,
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@ -193,13 +219,15 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc);
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struct device *dev = &pcie->pdev->dev;
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u32 intr_status;
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struct mobiveil_msi *msi = &pcie->msi;
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u32 msi_data, msi_addr_lo, msi_addr_hi;
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u32 intr_status, msi_status;
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unsigned long shifted_status;
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u32 bit, virq, val, mask;
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/*
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* The core provides interrupt for INTx.
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* So we'll read INTx status.
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* The core provides a single interrupt for both INTx/MSI messages.
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* So we'll read both INTx and MSI status
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*/
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chained_irq_enter(chip, desc);
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@ -231,6 +259,35 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
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} while ((shifted_status >> PAB_INTX_START) != 0);
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}
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/* read extra MSI status register */
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msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET);
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/* handle MSI interrupts */
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while (msi_status & 1) {
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msi_data = readl_relaxed(pcie->apb_csr_base
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+ MSI_DATA_OFFSET);
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/*
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* MSI_STATUS_OFFSET register gets updated to zero
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* once we pop not only the MSI data but also address
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* from MSI hardware FIFO. So keeping these following
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* two dummy reads.
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*/
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msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
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MSI_ADDR_L_OFFSET);
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msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
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MSI_ADDR_H_OFFSET);
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dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
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msi_data, msi_addr_hi, msi_addr_lo);
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virq = irq_find_mapping(msi->dev_domain, msi_data);
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if (virq)
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generic_handle_irq(virq);
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msi_status = readl_relaxed(pcie->apb_csr_base +
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MSI_STATUS_OFFSET);
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}
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/* Clear the interrupt status */
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csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
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chained_irq_exit(chip, desc);
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@ -266,6 +323,12 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
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return PTR_ERR(pcie->csr_axi_slave_base);
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pcie->pcie_reg_base = res->start;
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/* map MSI config resource */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr");
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pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res);
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if (IS_ERR(pcie->apb_csr_base))
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return PTR_ERR(pcie->apb_csr_base);
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/* read the number of windows requested */
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if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins))
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pcie->apio_wins = MAX_PIO_WINDOWS;
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@ -415,6 +478,22 @@ static int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
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return -ETIMEDOUT;
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}
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static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
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{
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phys_addr_t msg_addr = pcie->pcie_reg_base;
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struct mobiveil_msi *msi = &pcie->msi;
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pcie->msi.num_of_vectors = PCI_NUM_MSI;
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msi->msi_pages_phys = (phys_addr_t)msg_addr;
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writel_relaxed(lower_32_bits(msg_addr),
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pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
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writel_relaxed(upper_32_bits(msg_addr),
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pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
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writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
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writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
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}
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static int mobiveil_host_init(struct mobiveil_pcie *pcie)
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{
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u32 value, pab_ctrl, type = 0;
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@ -443,7 +522,8 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
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csr_writel(pcie, pab_ctrl | (1 << AMBA_PIO_ENABLE_SHIFT) |
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(1 << PEX_PIO_ENABLE_SHIFT), PAB_CTRL);
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csr_writel(pcie, PAB_INTP_INTX_MASK, PAB_INTP_AMBA_MISC_ENB);
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csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
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PAB_INTP_AMBA_MISC_ENB);
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/*
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* program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
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@ -482,6 +562,9 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
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}
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}
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/* setup MSI hardware registers */
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mobiveil_pcie_enable_msi(pcie);
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return err;
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}
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@ -537,6 +620,116 @@ static const struct irq_domain_ops intx_domain_ops = {
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.map = mobiveil_pcie_intx_map,
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};
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static struct irq_chip mobiveil_msi_irq_chip = {
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.name = "Mobiveil PCIe MSI",
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.irq_mask = pci_msi_mask_irq,
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.irq_unmask = pci_msi_unmask_irq,
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};
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static struct msi_domain_info mobiveil_msi_domain_info = {
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
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.chip = &mobiveil_msi_irq_chip,
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};
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static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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{
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struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
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phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));
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msg->address_lo = lower_32_bits(addr);
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msg->address_hi = upper_32_bits(addr);
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msg->data = data->hwirq;
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dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",
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(int)data->hwirq, msg->address_hi, msg->address_lo);
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}
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static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
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const struct cpumask *mask, bool force)
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{
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return -EINVAL;
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}
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static struct irq_chip mobiveil_msi_bottom_irq_chip = {
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.name = "Mobiveil MSI",
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.irq_compose_msi_msg = mobiveil_compose_msi_msg,
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.irq_set_affinity = mobiveil_msi_set_affinity,
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};
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static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs, void *args)
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{
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struct mobiveil_pcie *pcie = domain->host_data;
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struct mobiveil_msi *msi = &pcie->msi;
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unsigned long bit;
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WARN_ON(nr_irqs != 1);
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mutex_lock(&msi->lock);
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bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors);
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if (bit >= msi->num_of_vectors) {
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mutex_unlock(&msi->lock);
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return -ENOSPC;
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}
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set_bit(bit, msi->msi_irq_in_use);
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mutex_unlock(&msi->lock);
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irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip,
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domain->host_data, handle_level_irq,
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NULL, NULL);
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return 0;
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}
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static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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{
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
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struct mobiveil_msi *msi = &pcie->msi;
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mutex_lock(&msi->lock);
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if (!test_bit(d->hwirq, msi->msi_irq_in_use)) {
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dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
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d->hwirq);
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} else {
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__clear_bit(d->hwirq, msi->msi_irq_in_use);
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}
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mutex_unlock(&msi->lock);
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}
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static const struct irq_domain_ops msi_domain_ops = {
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.alloc = mobiveil_irq_msi_domain_alloc,
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.free = mobiveil_irq_msi_domain_free,
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};
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static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
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{
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struct device *dev = &pcie->pdev->dev;
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struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
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struct mobiveil_msi *msi = &pcie->msi;
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mutex_init(&pcie->msi.lock);
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msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors,
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&msi_domain_ops, pcie);
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if (!msi->dev_domain) {
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dev_err(dev, "failed to create IRQ domain\n");
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return -ENOMEM;
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}
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msi->msi_domain = pci_msi_create_irq_domain(fwnode,
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&mobiveil_msi_domain_info, msi->dev_domain);
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if (!msi->msi_domain) {
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dev_err(dev, "failed to create MSI domain\n");
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irq_domain_remove(msi->dev_domain);
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return -ENOMEM;
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}
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return 0;
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}
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static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
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{
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struct device *dev = &pcie->pdev->dev;
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@ -554,6 +747,11 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
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raw_spin_lock_init(&pcie->intx_mask_lock);
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/* setup MSI */
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ret = mobiveil_allocate_msi_domains(pcie);
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if (ret)
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return ret;
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return 0;
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}
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