ARM: 8231/1: sa1100: introduce irqdomains support
Use irqdomains to manage both system and GPIO interrupts on SA1100 SoC family. This opens path to further cleanup and unification in sa1100 IRQ drivers. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Коммит
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@ -702,6 +702,7 @@ config ARCH_SA1100
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select CPU_SA1100
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select GENERIC_CLOCKEVENTS
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select HAVE_IDE
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select IRQ_DOMAIN
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select ISA
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select MULTI_IRQ_HANDLER
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select NEED_MACH_MEMORY_H
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@ -14,6 +14,7 @@
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/ioport.h>
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#include <linux/syscore_ops.h>
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@ -106,6 +107,23 @@ static struct irq_chip sa1100_low_gpio_chip = {
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.irq_set_wake = sa1100_low_gpio_wake,
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};
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static int sa1100_low_gpio_irqdomain_map(struct irq_domain *d,
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unsigned int irq, irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
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handle_edge_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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return 0;
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}
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static struct irq_domain_ops sa1100_low_gpio_irqdomain_ops = {
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.map = sa1100_low_gpio_irqdomain_map,
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.xlate = irq_domain_xlate_onetwocell,
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};
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static struct irq_domain *sa1100_low_gpio_irqdomain;
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/*
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* IRQ11 (GPIO11 through 27) handler. We enter here with the
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* irq_controller_lock held, and IRQs disabled. Decode the IRQ
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@ -187,6 +205,23 @@ static struct irq_chip sa1100_high_gpio_chip = {
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.irq_set_wake = sa1100_high_gpio_wake,
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};
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static int sa1100_high_gpio_irqdomain_map(struct irq_domain *d,
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unsigned int irq, irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
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handle_edge_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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return 0;
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}
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static struct irq_domain_ops sa1100_high_gpio_irqdomain_ops = {
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.map = sa1100_high_gpio_irqdomain_map,
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.xlate = irq_domain_xlate_onetwocell,
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};
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static struct irq_domain *sa1100_high_gpio_irqdomain;
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/*
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* We don't need to ACK IRQs on the SA1100 unless they're GPIOs
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* this is for internal IRQs i.e. from IRQ LCD to RTCAlrm.
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@ -224,6 +259,23 @@ static struct irq_chip sa1100_normal_chip = {
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.irq_set_wake = sa1100_set_wake,
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};
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static int sa1100_normal_irqdomain_map(struct irq_domain *d,
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unsigned int irq, irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &sa1100_normal_chip,
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handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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return 0;
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}
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static struct irq_domain_ops sa1100_normal_irqdomain_ops = {
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.map = sa1100_normal_irqdomain_map,
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.xlate = irq_domain_xlate_onetwocell,
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};
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static struct irq_domain *sa1100_normal_irqdomain;
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static struct resource irq_resource =
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DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
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@ -311,8 +363,6 @@ sa1100_handle_irq(struct pt_regs *regs)
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void __init sa1100_init_irq(void)
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{
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unsigned int irq;
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request_resource(&iomem_resource, &irq_resource);
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/* disable all IRQs */
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@ -332,23 +382,17 @@ void __init sa1100_init_irq(void)
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*/
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ICCR = 1;
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for (irq = IRQ_GPIO0; irq <= IRQ_GPIO10; irq++) {
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irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
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handle_edge_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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sa1100_low_gpio_irqdomain = irq_domain_add_legacy(NULL,
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11, IRQ_GPIO0, 0,
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&sa1100_low_gpio_irqdomain_ops, NULL);
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for (irq = IRQ_LCD; irq <= IRQ_RTCAlrm; irq++) {
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irq_set_chip_and_handler(irq, &sa1100_normal_chip,
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handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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sa1100_normal_irqdomain = irq_domain_add_legacy(NULL,
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20, IRQ_LCD, 12,
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&sa1100_normal_irqdomain_ops, NULL);
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for (irq = IRQ_GPIO11; irq <= IRQ_GPIO27; irq++) {
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irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
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handle_edge_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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sa1100_high_gpio_irqdomain = irq_domain_add_legacy(NULL,
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17, IRQ_GPIO11, 11,
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&sa1100_high_gpio_irqdomain_ops, NULL);
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/*
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* Install handler for GPIO 11-27 edge detect interrupts
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