Merge remote-tracking branch 'asoc/topic/fsl-ssi' into asoc-next

sound/soc/fsl/Kconfig

@@ -16,6 +16,7 @@ config SND_SOC_FSL_SSI
 	tristate "Synchronous Serial Interface module support"
 	select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC != n
 	select SND_SOC_IMX_PCM_FIQ if SND_IMX_SOC != n && ARCH_MXC
+	select REGMAP_MMIO
 	help
 	  Say Y if you want to add Synchronous Serial Interface (SSI)
 	  support for the Freescale CPUs.
@@ -207,12 +208,7 @@ config SND_SOC_PHYCORE_AC97
 
 config SND_SOC_EUKREA_TLV320
 	tristate "Eukrea TLV320"
-	depends on MACH_EUKREA_MBIMX27_BASEBOARD \
+	depends on ARCH_MXC && I2C
-		|| MACH_EUKREA_MBIMXSD25_BASEBOARD \
-		|| MACH_EUKREA_MBIMXSD35_BASEBOARD \
-		|| MACH_EUKREA_MBIMXSD51_BASEBOARD \
-		|| (OF && ARM)
-	depends on I2C
 	select SND_SOC_TLV320AIC23_I2C
 	select SND_SOC_IMX_AUDMUX
 	select SND_SOC_IMX_SSI

sound/soc/fsl/fsl_ssi.h

@@ -12,32 +12,30 @@
 #ifndef _MPC8610_I2S_H
 #define _MPC8610_I2S_H
 
-/* SSI Register Map */
+/* SSI registers */
-struct ccsr_ssi {
+#define CCSR_SSI_STX0			0x00
-	__be32 stx0;	/* 0x.0000 - SSI Transmit Data Register 0 */
+#define CCSR_SSI_STX1			0x04
-	__be32 stx1;	/* 0x.0004 - SSI Transmit Data Register 1 */
+#define CCSR_SSI_SRX0			0x08
-	__be32 srx0;	/* 0x.0008 - SSI Receive Data Register 0 */
+#define CCSR_SSI_SRX1			0x0c
-	__be32 srx1;	/* 0x.000C - SSI Receive Data Register 1 */
+#define CCSR_SSI_SCR			0x10
-	__be32 scr;	/* 0x.0010 - SSI Control Register */
+#define CCSR_SSI_SISR			0x14
-	__be32 sisr;	/* 0x.0014 - SSI Interrupt Status Register Mixed */
+#define CCSR_SSI_SIER			0x18
-	__be32 sier;	/* 0x.0018 - SSI Interrupt Enable Register */
+#define CCSR_SSI_STCR			0x1c
-	__be32 stcr;	/* 0x.001C - SSI Transmit Configuration Register */
+#define CCSR_SSI_SRCR			0x20
-	__be32 srcr;	/* 0x.0020 - SSI Receive Configuration Register */
+#define CCSR_SSI_STCCR			0x24
-	__be32 stccr;	/* 0x.0024 - SSI Transmit Clock Control Register */
+#define CCSR_SSI_SRCCR			0x28
-	__be32 srccr;	/* 0x.0028 - SSI Receive Clock Control Register */
+#define CCSR_SSI_SFCSR			0x2c
-	__be32 sfcsr;	/* 0x.002C - SSI FIFO Control/Status Register */
+#define CCSR_SSI_STR			0x30
-	__be32 str;	/* 0x.0030 - SSI Test Register */
+#define CCSR_SSI_SOR			0x34
-	__be32 sor;	/* 0x.0034 - SSI Option Register */
+#define CCSR_SSI_SACNT			0x38
-	__be32 sacnt;	/* 0x.0038 - SSI AC97 Control Register */
+#define CCSR_SSI_SACADD			0x3c
-	__be32 sacadd;	/* 0x.003C - SSI AC97 Command Address Register */
+#define CCSR_SSI_SACDAT			0x40
-	__be32 sacdat;	/* 0x.0040 - SSI AC97 Command Data Register */
+#define CCSR_SSI_SATAG			0x44
-	__be32 satag;	/* 0x.0044 - SSI AC97 Tag Register */
+#define CCSR_SSI_STMSK			0x48
-	__be32 stmsk;	/* 0x.0048 - SSI Transmit Time Slot Mask Register */
+#define CCSR_SSI_SRMSK			0x4c
-	__be32 srmsk;	/* 0x.004C - SSI Receive Time Slot Mask Register */
+#define CCSR_SSI_SACCST			0x50
-	__be32 saccst;	/* 0x.0050 - SSI AC97 Channel Status Register */
+#define CCSR_SSI_SACCEN			0x54
-	__be32 saccen;	/* 0x.0054 - SSI AC97 Channel Enable Register */
+#define CCSR_SSI_SACCDIS		0x58
-	__be32 saccdis; /* 0x.0058 - SSI AC97 Channel Disable Register */
-};
 
 #define CCSR_SSI_SCR_SYNC_TX_FS		0x00001000
 #define CCSR_SSI_SCR_RFR_CLK_DIS	0x00000800