sh: intc - add support for x3
This patch converts the cpu specific interrupt setup code for x3 from intc2 to intc. New vectors are also added to match the preliminary information. Use plat_irq_setup_pins() to select between IRQ and IRL mode for IRQ0-3. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
Родитель
137b53b71c
Коммит
1ee010087e
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@ -58,28 +58,200 @@ static int __init shx3_devices_setup(void)
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}
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__initcall(shx3_devices_setup);
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static struct intc2_data intc2_irq_table[] = {
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{ 16, 0, 0, 0, 1, 2 }, /* TMU0 */
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{ 40, 4, 0, 0x20, 0, 3 }, /* SCIF0 ERI */
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{ 41, 4, 0, 0x20, 1, 3 }, /* SCIF0 RXI */
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{ 42, 4, 0, 0x20, 2, 3 }, /* SCIF0 BRI */
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{ 43, 4, 0, 0x20, 3, 3 }, /* SCIF0 TXI */
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
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IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
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IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
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IRL_HHLL, IRL_HHLH, IRL_HHHL,
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IRQ0, IRQ1, IRQ2, IRQ3,
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HUDII,
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TMU0, TMU1, TMU2, TMU3, TMU4, TMU5,
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PCII0, PCII1, PCII2, PCII3, PCII4,
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PCII5, PCII6, PCII7, PCII8, PCII9,
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SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
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SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
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SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
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SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI,
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DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
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DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
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DU,
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DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
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DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
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IIC, VIN0, VIN1, VCORE0, ATAPI,
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DTU0_TEND, DTU0_AE, DTU0_TMISS,
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DTU1_TEND, DTU1_AE, DTU1_TMISS,
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DTU2_TEND, DTU2_AE, DTU2_TMISS,
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DTU3_TEND, DTU3_AE, DTU3_TMISS,
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FE0, FE1,
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GPIO0, GPIO1, GPIO2, GPIO3,
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PAM, IRM,
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/* interrupt groups */
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IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3,
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DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3,
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};
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static struct intc2_desc intc2_irq_desc __read_mostly = {
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.prio_base = 0xfe410000,
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.msk_base = 0xfe410820,
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.mskclr_base = 0xfe410850,
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.intc2_data = intc2_irq_table,
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.nr_irqs = ARRAY_SIZE(intc2_irq_table),
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.chip = {
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.name = "INTC2-SHX3",
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},
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static struct intc_vect vectors[] = {
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INTC_VECT(HUDII, 0x3e0),
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INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
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INTC_VECT(TMU2, 0x440), INTC_VECT(TMU3, 0x460),
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INTC_VECT(TMU4, 0x480), INTC_VECT(TMU5, 0x4a0),
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INTC_VECT(PCII0, 0x500), INTC_VECT(PCII1, 0x520),
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INTC_VECT(PCII2, 0x540), INTC_VECT(PCII3, 0x560),
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INTC_VECT(PCII4, 0x580), INTC_VECT(PCII5, 0x5a0),
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INTC_VECT(PCII6, 0x5c0), INTC_VECT(PCII7, 0x5e0),
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INTC_VECT(PCII8, 0x600), INTC_VECT(PCII9, 0x620),
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INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
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INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
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INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
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INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
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INTC_VECT(SCIF2_ERI, 0x800), INTC_VECT(SCIF2_RXI, 0x820),
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INTC_VECT(SCIF2_BRI, 0x840), INTC_VECT(SCIF2_TXI, 0x860),
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INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0),
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INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0),
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INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920),
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INTC_VECT(DMAC0_DMINT2, 0x940), INTC_VECT(DMAC0_DMINT3, 0x960),
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INTC_VECT(DMAC0_DMINT4, 0x980), INTC_VECT(DMAC0_DMINT5, 0x9a0),
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INTC_VECT(DMAC0_DMAE, 0x9c0),
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INTC_VECT(DU, 0x9e0),
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INTC_VECT(DMAC1_DMINT6, 0xa00), INTC_VECT(DMAC1_DMINT7, 0xa20),
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INTC_VECT(DMAC1_DMINT8, 0xa40), INTC_VECT(DMAC1_DMINT9, 0xa60),
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INTC_VECT(DMAC1_DMINT10, 0xa80), INTC_VECT(DMAC1_DMINT11, 0xaa0),
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INTC_VECT(DMAC1_DMAE, 0xac0),
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INTC_VECT(IIC, 0xae0),
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INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20),
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INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60),
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INTC_VECT(DTU0_TEND, 0xc00), INTC_VECT(DTU0_AE, 0xc20),
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INTC_VECT(DTU0_TMISS, 0xc40),
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INTC_VECT(DTU1_TEND, 0xc60), INTC_VECT(DTU1_AE, 0xc80),
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INTC_VECT(DTU1_TMISS, 0xca0),
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INTC_VECT(DTU2_TEND, 0xcc0), INTC_VECT(DTU2_AE, 0xce0),
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INTC_VECT(DTU2_TMISS, 0xd00),
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INTC_VECT(DTU3_TEND, 0xd20), INTC_VECT(DTU3_AE, 0xd40),
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INTC_VECT(DTU3_TMISS, 0xd60),
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INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20),
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INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60),
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INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0),
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INTC_VECT(PAM, 0xec0), INTC_VECT(IRM, 0xee0),
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};
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static struct intc_group groups[] = {
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INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
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IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
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IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
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IRL_HHLL, IRL_HHLH, IRL_HHHL),
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INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9),
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INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
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INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
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INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
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INTC_GROUP(SCIF3, SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI),
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INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
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DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
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INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
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DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
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INTC_GROUP(DTU0, DTU0_TEND, DTU0_AE, DTU0_TMISS),
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INTC_GROUP(DTU1, DTU1_TEND, DTU1_AE, DTU1_TMISS),
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INTC_GROUP(DTU2, DTU2_TEND, DTU2_AE, DTU2_TMISS),
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INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS),
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};
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static struct intc_prio priorities[] = {
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INTC_PRIO(SCIF0, 3),
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INTC_PRIO(SCIF1, 3),
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INTC_PRIO(SCIF2, 3),
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INTC_PRIO(SCIF3, 3),
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};
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static struct intc_mask_reg mask_registers[] = {
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{ 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
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{ IRQ0, IRQ1, IRQ2, IRQ3 } },
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{ 0xfe410040, 0xfe410060, 32, /* CnINTMSK1 / CnINTMSKCLR1 */
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{ IRL } },
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{ 0xfe410820, 0xfe410850, 32, /* CnINT2MSK0 / CnINT2MSKCLR0 */
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{ FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC,
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DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */
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0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, } },
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{ 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */
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{ 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */
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PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2,
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PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11,
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DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7,
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DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4,
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DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 } },
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{ 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI,
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SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI,
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SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI,
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SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } },
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};
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static struct intc_prio_reg prio_registers[] = {
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{ 0xfe410010, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
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{ 0xfe410800, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4,
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TMU3, TMU2, TMU1, TMU0 } },
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{ 0xfe410804, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0,
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SCIF3, SCIF2, SCIF1, SCIF0 } },
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{ 0xfe410808, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0, PCII56789, PCII4,
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PCII3, PCII2, PCII1, PCII0 } },
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{ 0xfe41080c, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0,
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VIN1, VIN0, IIC, DU} },
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{ 0xfe410810, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3,
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GPIO2, GPIO1, GPIO0, IRM } },
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};
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static DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups, priorities,
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mask_registers, prio_registers, NULL);
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/* Support for external interrupt pins in IRQ mode */
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static struct intc_vect vectors_irq[] = {
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INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
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INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
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};
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static struct intc_sense_reg sense_registers[] = {
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{ 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
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};
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static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups,
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priorities, mask_registers, prio_registers,
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sense_registers);
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/* External interrupt pins in IRL mode */
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static struct intc_vect vectors_irl[] = {
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INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
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INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
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INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
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INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
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INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
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INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
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INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
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INTC_VECT(IRL_HHHL, 0x3c0),
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};
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static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,
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priorities, mask_registers, prio_registers, NULL);
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void __init plat_irq_setup_pins(int mode)
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{
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switch (mode) {
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case IRQ_MODE_IRQ:
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register_intc_controller(&intc_desc_irq);
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break;
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case IRQ_MODE_IRL3210:
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register_intc_controller(&intc_desc_irl);
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break;
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default:
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BUG();
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}
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}
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void __init plat_irq_setup(void)
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{
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register_intc2_controller(&intc2_irq_desc);
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register_intc_controller(&intc_desc);
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}
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@ -197,7 +197,7 @@ config CPU_SUBTYPE_SHX3
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bool "Support SH-X3 processor"
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select CPU_SH4A
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select CPU_SHX3
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select CPU_HAS_INTC2_IRQ
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select CPU_HAS_INTC_IRQ
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# SH4AL-DSP Processor Support
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