phy: mdio-octeon: Refactor into two files/modules
A follow-on patch uses PCI probing to find the Thunder MDIO hardware. In preparation for this, split out the common code into a new file mdio-cavium.c, which will be used by both the existing OCTEON driver, and the new Thunder PCI based driver. As part of the refactoring simplify the struct cavium_mdiobus by removing fields that are only ever used in the probe function and can just as well be local variables. Use readq/writeq in preference to readq_relaxed/writeq_relaxed as the relaxed form was an optimization for an early chip revision, and the MDIO drivers are not performance bottlenecks that need optimization in the first place. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David Daney
David S. Miller
Родитель
5fc7cf1794
Коммит
1eefee901f
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@ -183,15 +183,18 @@ config MDIO_GPIO
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To compile this driver as a module, choose M here: the module
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will be called mdio-gpio.
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config MDIO_CAVIUM
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tristate
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config MDIO_OCTEON
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tristate "Support for MDIO buses on Octeon and ThunderX SOCs"
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tristate "Support for MDIO buses on Octeon and some ThunderX SOCs"
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depends on 64BIT
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depends on HAS_IOMEM
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select MDIO_CAVIUM
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help
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This module provides a driver for the Octeon and ThunderX MDIO
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busses. It is required by the Octeon and ThunderX ethernet device
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drivers.
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buses. It is required by the Octeon and ThunderX ethernet device
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drivers on some systems.
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config MDIO_SUN4I
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tristate "Allwinner sun4i MDIO interface support"
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@ -31,6 +31,7 @@ obj-$(CONFIG_DP83867_PHY) += dp83867.o
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obj-$(CONFIG_STE10XP) += ste10Xp.o
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obj-$(CONFIG_MICREL_PHY) += micrel.o
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obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
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obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium.o
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obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
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obj-$(CONFIG_AT803X_PHY) += at803x.o
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obj-$(CONFIG_AMD_PHY) += amd.o
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@ -0,0 +1,149 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2009-2016 Cavium, Inc.
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*/
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/io.h>
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#include "mdio-cavium.h"
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static void cavium_mdiobus_set_mode(struct cavium_mdiobus *p,
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enum cavium_mdiobus_mode m)
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{
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union cvmx_smix_clk smi_clk;
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if (m == p->mode)
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return;
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smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK);
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smi_clk.s.mode = (m == C45) ? 1 : 0;
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smi_clk.s.preamble = 1;
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oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK);
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p->mode = m;
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}
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static int cavium_mdiobus_c45_addr(struct cavium_mdiobus *p,
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int phy_id, int regnum)
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{
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union cvmx_smix_cmd smi_cmd;
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union cvmx_smix_wr_dat smi_wr;
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int timeout = 1000;
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cavium_mdiobus_set_mode(p, C45);
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smi_wr.u64 = 0;
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smi_wr.s.dat = regnum & 0xffff;
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oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
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regnum = (regnum >> 16) & 0x1f;
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smi_cmd.u64 = 0;
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smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_45_ADDRESS */
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = regnum;
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oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
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do {
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/* Wait 1000 clocks so we don't saturate the RSL bus
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* doing reads.
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*/
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__delay(1000);
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smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
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} while (smi_wr.s.pending && --timeout);
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if (timeout <= 0)
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return -EIO;
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return 0;
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}
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int cavium_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
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{
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struct cavium_mdiobus *p = bus->priv;
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union cvmx_smix_cmd smi_cmd;
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union cvmx_smix_rd_dat smi_rd;
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unsigned int op = 1; /* MDIO_CLAUSE_22_READ */
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int timeout = 1000;
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if (regnum & MII_ADDR_C45) {
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int r = cavium_mdiobus_c45_addr(p, phy_id, regnum);
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if (r < 0)
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return r;
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regnum = (regnum >> 16) & 0x1f;
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op = 3; /* MDIO_CLAUSE_45_READ */
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} else {
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cavium_mdiobus_set_mode(p, C22);
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}
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smi_cmd.u64 = 0;
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smi_cmd.s.phy_op = op;
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = regnum;
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oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
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do {
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/* Wait 1000 clocks so we don't saturate the RSL bus
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* doing reads.
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*/
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__delay(1000);
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smi_rd.u64 = oct_mdio_readq(p->register_base + SMI_RD_DAT);
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} while (smi_rd.s.pending && --timeout);
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if (smi_rd.s.val)
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return smi_rd.s.dat;
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else
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return -EIO;
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}
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EXPORT_SYMBOL(cavium_mdiobus_read);
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int cavium_mdiobus_write(struct mii_bus *bus, int phy_id, int regnum, u16 val)
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{
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struct cavium_mdiobus *p = bus->priv;
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union cvmx_smix_cmd smi_cmd;
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union cvmx_smix_wr_dat smi_wr;
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unsigned int op = 0; /* MDIO_CLAUSE_22_WRITE */
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int timeout = 1000;
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if (regnum & MII_ADDR_C45) {
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int r = cavium_mdiobus_c45_addr(p, phy_id, regnum);
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if (r < 0)
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return r;
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regnum = (regnum >> 16) & 0x1f;
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op = 1; /* MDIO_CLAUSE_45_WRITE */
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} else {
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cavium_mdiobus_set_mode(p, C22);
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}
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smi_wr.u64 = 0;
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smi_wr.s.dat = val;
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oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
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smi_cmd.u64 = 0;
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smi_cmd.s.phy_op = op;
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = regnum;
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oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
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do {
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/* Wait 1000 clocks so we don't saturate the RSL bus
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* doing reads.
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*/
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__delay(1000);
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smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
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} while (smi_wr.s.pending && --timeout);
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if (timeout <= 0)
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return -EIO;
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return 0;
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}
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EXPORT_SYMBOL(cavium_mdiobus_write);
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@ -0,0 +1,119 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2009-2016 Cavium, Inc.
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*/
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enum cavium_mdiobus_mode {
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UNINIT = 0,
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C22,
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C45
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};
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#define SMI_CMD 0x0
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#define SMI_WR_DAT 0x8
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#define SMI_RD_DAT 0x10
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#define SMI_CLK 0x18
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#define SMI_EN 0x20
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#ifdef __BIG_ENDIAN_BITFIELD
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#define OCT_MDIO_BITFIELD_FIELD(field, more) \
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field; \
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more
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#else
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#define OCT_MDIO_BITFIELD_FIELD(field, more) \
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more \
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field;
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#endif
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union cvmx_smix_clk {
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u64 u64;
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struct cvmx_smix_clk_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_25_63:39,
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OCT_MDIO_BITFIELD_FIELD(u64 mode:1,
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
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OCT_MDIO_BITFIELD_FIELD(u64 sample_hi:5,
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OCT_MDIO_BITFIELD_FIELD(u64 sample_mode:1,
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_14_14:1,
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OCT_MDIO_BITFIELD_FIELD(u64 clk_idle:1,
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OCT_MDIO_BITFIELD_FIELD(u64 preamble:1,
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OCT_MDIO_BITFIELD_FIELD(u64 sample:4,
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OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
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;))))))))))
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} s;
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};
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union cvmx_smix_cmd {
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u64 u64;
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struct cvmx_smix_cmd_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
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OCT_MDIO_BITFIELD_FIELD(u64 phy_op:2,
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_13_15:3,
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OCT_MDIO_BITFIELD_FIELD(u64 phy_adr:5,
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_5_7:3,
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OCT_MDIO_BITFIELD_FIELD(u64 reg_adr:5,
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;))))))
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} s;
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};
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union cvmx_smix_en {
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u64 u64;
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struct cvmx_smix_en_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_1_63:63,
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OCT_MDIO_BITFIELD_FIELD(u64 en:1,
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;))
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} s;
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};
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union cvmx_smix_rd_dat {
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u64 u64;
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struct cvmx_smix_rd_dat_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
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OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
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OCT_MDIO_BITFIELD_FIELD(u64 val:1,
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OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
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;))))
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} s;
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};
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union cvmx_smix_wr_dat {
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u64 u64;
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struct cvmx_smix_wr_dat_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
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OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
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OCT_MDIO_BITFIELD_FIELD(u64 val:1,
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OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
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;))))
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} s;
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};
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struct cavium_mdiobus {
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struct mii_bus *mii_bus;
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u64 register_base;
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enum cavium_mdiobus_mode mode;
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};
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#ifdef CONFIG_CAVIUM_OCTEON_SOC
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#include <asm/octeon/octeon.h>
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static inline void oct_mdio_writeq(u64 val, u64 addr)
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{
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cvmx_write_csr(addr, val);
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}
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static inline u64 oct_mdio_readq(u64 addr)
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{
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return cvmx_read_csr(addr);
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}
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#else
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#define oct_mdio_writeq(val, addr) writeq(val, (void *)addr)
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#define oct_mdio_readq(addr) readq((void *)addr)
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#endif
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int cavium_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum);
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int cavium_mdiobus_write(struct mii_bus *bus, int phy_id, int regnum, u16 val);
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@ -3,272 +3,26 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2009-2012 Cavium, Inc.
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* Copyright (C) 2009-2015 Cavium, Inc.
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*/
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#include <linux/platform_device.h>
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#include <linux/of_address.h>
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#include <linux/of_mdio.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/gfp.h>
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#include <linux/phy.h>
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#include <linux/io.h>
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#ifdef CONFIG_CAVIUM_OCTEON_SOC
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#include <asm/octeon/octeon.h>
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#endif
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#define DRV_VERSION "1.1"
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#define DRV_DESCRIPTION "Cavium Networks Octeon/ThunderX SMI/MDIO driver"
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#define SMI_CMD 0x0
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#define SMI_WR_DAT 0x8
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#define SMI_RD_DAT 0x10
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#define SMI_CLK 0x18
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#define SMI_EN 0x20
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#ifdef __BIG_ENDIAN_BITFIELD
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#define OCT_MDIO_BITFIELD_FIELD(field, more) \
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field; \
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more
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#else
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#define OCT_MDIO_BITFIELD_FIELD(field, more) \
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more \
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field;
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#endif
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union cvmx_smix_clk {
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u64 u64;
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struct cvmx_smix_clk_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_25_63:39,
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OCT_MDIO_BITFIELD_FIELD(u64 mode:1,
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
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OCT_MDIO_BITFIELD_FIELD(u64 sample_hi:5,
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OCT_MDIO_BITFIELD_FIELD(u64 sample_mode:1,
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_14_14:1,
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OCT_MDIO_BITFIELD_FIELD(u64 clk_idle:1,
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OCT_MDIO_BITFIELD_FIELD(u64 preamble:1,
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OCT_MDIO_BITFIELD_FIELD(u64 sample:4,
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OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
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;))))))))))
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} s;
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};
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union cvmx_smix_cmd {
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u64 u64;
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struct cvmx_smix_cmd_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
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OCT_MDIO_BITFIELD_FIELD(u64 phy_op:2,
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_13_15:3,
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OCT_MDIO_BITFIELD_FIELD(u64 phy_adr:5,
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_5_7:3,
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OCT_MDIO_BITFIELD_FIELD(u64 reg_adr:5,
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;))))))
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} s;
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};
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union cvmx_smix_en {
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u64 u64;
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struct cvmx_smix_en_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_1_63:63,
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OCT_MDIO_BITFIELD_FIELD(u64 en:1,
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;))
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} s;
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};
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union cvmx_smix_rd_dat {
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u64 u64;
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struct cvmx_smix_rd_dat_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
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OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
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OCT_MDIO_BITFIELD_FIELD(u64 val:1,
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OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
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;))))
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} s;
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};
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union cvmx_smix_wr_dat {
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u64 u64;
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struct cvmx_smix_wr_dat_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
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OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
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OCT_MDIO_BITFIELD_FIELD(u64 val:1,
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OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
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;))))
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} s;
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};
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enum octeon_mdiobus_mode {
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UNINIT = 0,
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C22,
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C45
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};
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struct octeon_mdiobus {
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struct mii_bus *mii_bus;
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u64 register_base;
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resource_size_t mdio_phys;
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resource_size_t regsize;
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enum octeon_mdiobus_mode mode;
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};
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#ifdef CONFIG_CAVIUM_OCTEON_SOC
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static void oct_mdio_writeq(u64 val, u64 addr)
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{
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cvmx_write_csr(addr, val);
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}
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static u64 oct_mdio_readq(u64 addr)
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{
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return cvmx_read_csr(addr);
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}
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#else
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#define oct_mdio_writeq(val, addr) writeq_relaxed(val, (void *)addr)
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#define oct_mdio_readq(addr) readq_relaxed((void *)addr)
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#endif
|
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static void octeon_mdiobus_set_mode(struct octeon_mdiobus *p,
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enum octeon_mdiobus_mode m)
|
||||
{
|
||||
union cvmx_smix_clk smi_clk;
|
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|
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if (m == p->mode)
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return;
|
||||
|
||||
smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK);
|
||||
smi_clk.s.mode = (m == C45) ? 1 : 0;
|
||||
smi_clk.s.preamble = 1;
|
||||
oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK);
|
||||
p->mode = m;
|
||||
}
|
||||
|
||||
static int octeon_mdiobus_c45_addr(struct octeon_mdiobus *p,
|
||||
int phy_id, int regnum)
|
||||
{
|
||||
union cvmx_smix_cmd smi_cmd;
|
||||
union cvmx_smix_wr_dat smi_wr;
|
||||
int timeout = 1000;
|
||||
|
||||
octeon_mdiobus_set_mode(p, C45);
|
||||
|
||||
smi_wr.u64 = 0;
|
||||
smi_wr.s.dat = regnum & 0xffff;
|
||||
oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
|
||||
|
||||
regnum = (regnum >> 16) & 0x1f;
|
||||
|
||||
smi_cmd.u64 = 0;
|
||||
smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_45_ADDRESS */
|
||||
smi_cmd.s.phy_adr = phy_id;
|
||||
smi_cmd.s.reg_adr = regnum;
|
||||
oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
|
||||
|
||||
do {
|
||||
/* Wait 1000 clocks so we don't saturate the RSL bus
|
||||
* doing reads.
|
||||
*/
|
||||
__delay(1000);
|
||||
smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
|
||||
} while (smi_wr.s.pending && --timeout);
|
||||
|
||||
if (timeout <= 0)
|
||||
return -EIO;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
|
||||
{
|
||||
struct octeon_mdiobus *p = bus->priv;
|
||||
union cvmx_smix_cmd smi_cmd;
|
||||
union cvmx_smix_rd_dat smi_rd;
|
||||
unsigned int op = 1; /* MDIO_CLAUSE_22_READ */
|
||||
int timeout = 1000;
|
||||
|
||||
if (regnum & MII_ADDR_C45) {
|
||||
int r = octeon_mdiobus_c45_addr(p, phy_id, regnum);
|
||||
if (r < 0)
|
||||
return r;
|
||||
|
||||
regnum = (regnum >> 16) & 0x1f;
|
||||
op = 3; /* MDIO_CLAUSE_45_READ */
|
||||
} else {
|
||||
octeon_mdiobus_set_mode(p, C22);
|
||||
}
|
||||
|
||||
|
||||
smi_cmd.u64 = 0;
|
||||
smi_cmd.s.phy_op = op;
|
||||
smi_cmd.s.phy_adr = phy_id;
|
||||
smi_cmd.s.reg_adr = regnum;
|
||||
oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
|
||||
|
||||
do {
|
||||
/* Wait 1000 clocks so we don't saturate the RSL bus
|
||||
* doing reads.
|
||||
*/
|
||||
__delay(1000);
|
||||
smi_rd.u64 = oct_mdio_readq(p->register_base + SMI_RD_DAT);
|
||||
} while (smi_rd.s.pending && --timeout);
|
||||
|
||||
if (smi_rd.s.val)
|
||||
return smi_rd.s.dat;
|
||||
else
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id,
|
||||
int regnum, u16 val)
|
||||
{
|
||||
struct octeon_mdiobus *p = bus->priv;
|
||||
union cvmx_smix_cmd smi_cmd;
|
||||
union cvmx_smix_wr_dat smi_wr;
|
||||
unsigned int op = 0; /* MDIO_CLAUSE_22_WRITE */
|
||||
int timeout = 1000;
|
||||
|
||||
|
||||
if (regnum & MII_ADDR_C45) {
|
||||
int r = octeon_mdiobus_c45_addr(p, phy_id, regnum);
|
||||
if (r < 0)
|
||||
return r;
|
||||
|
||||
regnum = (regnum >> 16) & 0x1f;
|
||||
op = 1; /* MDIO_CLAUSE_45_WRITE */
|
||||
} else {
|
||||
octeon_mdiobus_set_mode(p, C22);
|
||||
}
|
||||
|
||||
smi_wr.u64 = 0;
|
||||
smi_wr.s.dat = val;
|
||||
oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
|
||||
|
||||
smi_cmd.u64 = 0;
|
||||
smi_cmd.s.phy_op = op;
|
||||
smi_cmd.s.phy_adr = phy_id;
|
||||
smi_cmd.s.reg_adr = regnum;
|
||||
oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
|
||||
|
||||
do {
|
||||
/* Wait 1000 clocks so we don't saturate the RSL bus
|
||||
* doing reads.
|
||||
*/
|
||||
__delay(1000);
|
||||
smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
|
||||
} while (smi_wr.s.pending && --timeout);
|
||||
|
||||
if (timeout <= 0)
|
||||
return -EIO;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#include "mdio-cavium.h"
|
||||
|
||||
static int octeon_mdiobus_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct octeon_mdiobus *bus;
|
||||
struct cavium_mdiobus *bus;
|
||||
struct mii_bus *mii_bus;
|
||||
struct resource *res_mem;
|
||||
resource_size_t mdio_phys;
|
||||
resource_size_t regsize;
|
||||
union cvmx_smix_en smi_en;
|
||||
int err = -ENOENT;
|
||||
|
||||
|
|
@ -284,17 +38,17 @@ static int octeon_mdiobus_probe(struct platform_device *pdev)
|
|||
|
||||
bus = mii_bus->priv;
|
||||
bus->mii_bus = mii_bus;
|
||||
bus->mdio_phys = res_mem->start;
|
||||
bus->regsize = resource_size(res_mem);
|
||||
mdio_phys = res_mem->start;
|
||||
regsize = resource_size(res_mem);
|
||||
|
||||
if (!devm_request_mem_region(&pdev->dev, bus->mdio_phys, bus->regsize,
|
||||
if (!devm_request_mem_region(&pdev->dev, mdio_phys, regsize,
|
||||
res_mem->name)) {
|
||||
dev_err(&pdev->dev, "request_mem_region failed\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
bus->register_base =
|
||||
(u64)devm_ioremap(&pdev->dev, bus->mdio_phys, bus->regsize);
|
||||
(u64)devm_ioremap(&pdev->dev, mdio_phys, regsize);
|
||||
if (!bus->register_base) {
|
||||
dev_err(&pdev->dev, "dev_ioremap failed\n");
|
||||
return -ENOMEM;
|
||||
|
|
@ -304,13 +58,12 @@ static int octeon_mdiobus_probe(struct platform_device *pdev)
|
|||
smi_en.s.en = 1;
|
||||
oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
|
||||
|
||||
bus->mii_bus->priv = bus;
|
||||
bus->mii_bus->name = "mdio-octeon";
|
||||
bus->mii_bus->name = KBUILD_MODNAME;
|
||||
snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%llx", bus->register_base);
|
||||
bus->mii_bus->parent = &pdev->dev;
|
||||
|
||||
bus->mii_bus->read = octeon_mdiobus_read;
|
||||
bus->mii_bus->write = octeon_mdiobus_write;
|
||||
bus->mii_bus->read = cavium_mdiobus_read;
|
||||
bus->mii_bus->write = cavium_mdiobus_write;
|
||||
|
||||
platform_set_drvdata(pdev, bus);
|
||||
|
||||
|
|
@ -318,7 +71,7 @@ static int octeon_mdiobus_probe(struct platform_device *pdev)
|
|||
if (err)
|
||||
goto fail_register;
|
||||
|
||||
dev_info(&pdev->dev, "Version " DRV_VERSION "\n");
|
||||
dev_info(&pdev->dev, "Probed\n");
|
||||
|
||||
return 0;
|
||||
fail_register:
|
||||
|
|
@ -330,7 +83,7 @@ fail_register:
|
|||
|
||||
static int octeon_mdiobus_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct octeon_mdiobus *bus;
|
||||
struct cavium_mdiobus *bus;
|
||||
union cvmx_smix_en smi_en;
|
||||
|
||||
bus = platform_get_drvdata(pdev);
|
||||
|
|
@ -352,7 +105,7 @@ MODULE_DEVICE_TABLE(of, octeon_mdiobus_match);
|
|||
|
||||
static struct platform_driver octeon_mdiobus_driver = {
|
||||
.driver = {
|
||||
.name = "mdio-octeon",
|
||||
.name = KBUILD_MODNAME,
|
||||
.of_match_table = octeon_mdiobus_match,
|
||||
},
|
||||
.probe = octeon_mdiobus_probe,
|
||||
|
|
@ -367,7 +120,6 @@ EXPORT_SYMBOL(octeon_mdiobus_force_mod_depencency);
|
|||
|
||||
module_platform_driver(octeon_mdiobus_driver);
|
||||
|
||||
MODULE_DESCRIPTION(DRV_DESCRIPTION);
|
||||
MODULE_VERSION(DRV_VERSION);
|
||||
MODULE_DESCRIPTION("Cavium OCTEON MDIO bus driver");
|
||||
MODULE_AUTHOR("David Daney");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
|
|||
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