sh: GUSA atomic rollback support.
This implements kernel-level atomic rollback built on top of gUSA, as an alternative non-IRQ based atomicity method. This is generally a faster method for platforms that are lacking the LL/SC pairs that SH-4A and later use, and is only supportable on legacy cores. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Stuart Menefy
Paul Mundt
Родитель
53ff09422e
Коммит
1efe4ce3ca
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@ -692,7 +692,7 @@ source "kernel/Kconfig.preempt"
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config GUSA
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def_bool y
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depends on !SMP
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depends on !SMP && SUPERH32
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help
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This enables support for gUSA (general UserSpace Atomicity).
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This is the default implementation for both UP and non-ll/sc
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@ -704,6 +704,16 @@ config GUSA
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This should only be disabled for special cases where alternate
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atomicity implementations exist.
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config GUSA_RB
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bool "Implement atomic operations by roll-back (gRB) (EXPERIMENTAL)"
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depends on GUSA && CPU_SH3 || (CPU_SH4 && !CPU_SH4A)
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help
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Enabling this option will allow the kernel to implement some
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atomic operations using a software implemention of load-locked/
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store-conditional (LLSC). On machines which do not have hardware
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LLSC, this should be more efficient than the other alternative of
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disabling insterrupts around the atomic sequence.
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endmenu
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menu "Boot options"
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@ -13,8 +13,9 @@
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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#include <asm/cpu/mmu_context.h>
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#include <asm/unistd.h>
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#include <asm/cpu/mmu_context.h>
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#include <asm/page.h>
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! NOTE:
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! GNU as (as of 2.9.1) changes bf/s into bt/s and bra, when the address
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@ -409,6 +410,27 @@ ENTRY(handle_exception)
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! Using k0, k1 for scratch registers (r0_bank1, r1_bank),
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! save all registers onto stack.
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!
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#ifdef CONFIG_GUSA
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! Check for roll back gRB (User and Kernel)
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mov r15, k0
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shll k0
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bf/s 1f
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shll k0
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bf/s 1f
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stc spc, k1
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stc r0_bank, k0
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cmp/hs k0, k1 ! test k1 (saved PC) >= k0 (saved r0)
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bt/s 2f
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stc r1_bank, k1
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add #-2, k0
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add r15, k0
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ldc k0, spc ! PC = saved r0 + r15 - 2
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2: mov k1, r15 ! SP = r1
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1:
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#endif
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stc ssr, k0 ! Is it from kernel space?
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shll k0 ! Check MD bit (bit30) by shifting it into...
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shll k0 ! ...the T bit
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@ -176,25 +176,6 @@ work_notifysig:
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jmp @r1
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lds r0, pr
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work_resched:
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#if defined(CONFIG_GUSA) && !defined(CONFIG_PREEMPT)
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! gUSA handling
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mov.l @(OFF_SP,r15), r0 ! get user space stack pointer
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mov r0, r1
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shll r0
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bf/s 1f
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shll r0
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bf/s 1f
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mov #OFF_PC, r0
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! SP >= 0xc0000000 : gUSA mark
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mov.l @(r0,r15), r2 ! get user space PC (program counter)
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mov.l @(OFF_R0,r15), r3 ! end point
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cmp/hs r3, r2 ! r2 >= r3?
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bt 1f
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add r3, r1 ! rewind point #2
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mov.l r1, @(r0,r15) ! reset PC to rewind point #2
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!
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1:
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#endif
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mov.l 1f, r1
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jsr @r1 ! schedule
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nop
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@ -322,25 +322,6 @@ struct task_struct *__switch_to(struct task_struct *prev,
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unlazy_fpu(prev, task_pt_regs(prev));
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#endif
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#if defined(CONFIG_GUSA) && defined(CONFIG_PREEMPT)
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{
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struct pt_regs *regs;
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preempt_disable();
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regs = task_pt_regs(prev);
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if (user_mode(regs) && regs->regs[15] >= 0xc0000000) {
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int offset = (int)regs->regs[15];
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/* Reset stack pointer: clear critical region mark */
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regs->regs[15] = regs->regs[1];
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if (regs->pc < regs->regs[0])
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/* Go to rewind point */
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regs->pc = regs->regs[0] + offset;
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}
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preempt_enable_no_resched();
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}
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#endif
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#ifdef CONFIG_MMU
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/*
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* Restore the kernel mode register
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@ -507,24 +507,6 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info,
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ctrl_inw(regs->pc - 4));
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break;
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}
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#ifdef CONFIG_GUSA
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} else {
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/* gUSA handling */
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preempt_disable();
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if (regs->regs[15] >= 0xc0000000) {
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int offset = (int)regs->regs[15];
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/* Reset stack pointer: clear critical region mark */
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regs->regs[15] = regs->regs[1];
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if (regs->pc < regs->regs[0])
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/* Go to rewind point #1 */
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regs->pc = regs->regs[0] + offset -
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instruction_size(ctrl_inw(regs->pc-4));
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}
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preempt_enable_no_resched();
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#endif
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}
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/* Set up the stack frame */
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@ -0,0 +1,169 @@
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#ifndef __ASM_SH_ATOMIC_GRB_H
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#define __ASM_SH_ATOMIC_GRB_H
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static inline void atomic_add(int i, atomic_t *v)
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{
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int tmp;
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__asm__ __volatile__ (
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" .align 2 \n\t"
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" mova 1f, r0 \n\t" /* r0 = end point */
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" mov r15, r1 \n\t" /* r1 = saved sp */
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" mov #-6, r15 \n\t" /* LOGIN: r15 = size */
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" mov.l @%1, %0 \n\t" /* load old value */
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" add %2, %0 \n\t" /* add */
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" mov.l %0, @%1 \n\t" /* store new value */
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"1: mov r1, r15 \n\t" /* LOGOUT */
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: "=&r" (tmp),
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"+r" (v)
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: "r" (i)
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: "memory" , "r0", "r1");
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}
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static inline void atomic_sub(int i, atomic_t *v)
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{
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int tmp;
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__asm__ __volatile__ (
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" .align 2 \n\t"
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" mova 1f, r0 \n\t" /* r0 = end point */
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" mov r15, r1 \n\t" /* r1 = saved sp */
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" mov #-6, r15 \n\t" /* LOGIN: r15 = size */
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" mov.l @%1, %0 \n\t" /* load old value */
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" sub %2, %0 \n\t" /* sub */
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" mov.l %0, @%1 \n\t" /* store new value */
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"1: mov r1, r15 \n\t" /* LOGOUT */
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: "=&r" (tmp),
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"+r" (v)
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: "r" (i)
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: "memory" , "r0", "r1");
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}
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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int tmp;
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__asm__ __volatile__ (
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" .align 2 \n\t"
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" mova 1f, r0 \n\t" /* r0 = end point */
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" mov r15, r1 \n\t" /* r1 = saved sp */
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" mov #-6, r15 \n\t" /* LOGIN: r15 = size */
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" mov.l @%1, %0 \n\t" /* load old value */
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" add %2, %0 \n\t" /* add */
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" mov.l %0, @%1 \n\t" /* store new value */
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"1: mov r1, r15 \n\t" /* LOGOUT */
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: "=&r" (tmp),
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"+r" (v)
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: "r" (i)
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: "memory" , "r0", "r1");
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return tmp;
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}
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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int tmp;
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__asm__ __volatile__ (
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" .align 2 \n\t"
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" mova 1f, r0 \n\t" /* r0 = end point */
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" mov r15, r1 \n\t" /* r1 = saved sp */
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" mov #-6, r15 \n\t" /* LOGIN: r15 = size */
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" mov.l @%1, %0 \n\t" /* load old value */
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" sub %2, %0 \n\t" /* sub */
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" mov.l %0, @%1 \n\t" /* store new value */
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"1: mov r1, r15 \n\t" /* LOGOUT */
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: "=&r" (tmp),
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"+r" (v)
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: "r" (i)
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: "memory", "r0", "r1");
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return tmp;
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}
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static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
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{
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int tmp;
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unsigned int _mask = ~mask;
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__asm__ __volatile__ (
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" .align 2 \n\t"
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" mova 1f, r0 \n\t" /* r0 = end point */
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" mov r15, r1 \n\t" /* r1 = saved sp */
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" mov #-6, r15 \n\t" /* LOGIN: r15 = size */
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" mov.l @%1, %0 \n\t" /* load old value */
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" and %2, %0 \n\t" /* add */
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" mov.l %0, @%1 \n\t" /* store new value */
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"1: mov r1, r15 \n\t" /* LOGOUT */
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: "=&r" (tmp),
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"+r" (v)
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: "r" (_mask)
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: "memory" , "r0", "r1");
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}
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static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
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{
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int tmp;
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__asm__ __volatile__ (
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" .align 2 \n\t"
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" mova 1f, r0 \n\t" /* r0 = end point */
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" mov r15, r1 \n\t" /* r1 = saved sp */
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" mov #-6, r15 \n\t" /* LOGIN: r15 = size */
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" mov.l @%1, %0 \n\t" /* load old value */
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" or %2, %0 \n\t" /* or */
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" mov.l %0, @%1 \n\t" /* store new value */
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"1: mov r1, r15 \n\t" /* LOGOUT */
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: "=&r" (tmp),
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"+r" (v)
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: "r" (mask)
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: "memory" , "r0", "r1");
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}
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static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
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{
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int ret;
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__asm__ __volatile__ (
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" .align 2 \n\t"
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" mova 1f, r0 \n\t"
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" nop \n\t"
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" mov r15, r1 \n\t"
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" mov #-8, r15 \n\t"
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" mov.l @%1, %0 \n\t"
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" cmp/eq %2, %0 \n\t"
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" bf 1f \n\t"
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" mov.l %3, @%1 \n\t"
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"1: mov r1, r15 \n\t"
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: "=&r" (ret)
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: "r" (v), "r" (old), "r" (new)
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: "memory" , "r0", "r1" , "t");
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return ret;
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}
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static inline int atomic_add_unless(atomic_t *v, int a, int u)
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{
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int ret;
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unsigned long tmp;
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__asm__ __volatile__ (
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" .align 2 \n\t"
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" mova 1f, r0 \n\t"
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" nop \n\t"
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" mov r15, r1 \n\t"
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" mov #-12, r15 \n\t"
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" mov.l @%2, %1 \n\t"
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" mov %1, %0 \n\t"
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" cmp/eq %4, %0 \n\t"
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" bt/s 1f \n\t"
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" add %3, %1 \n\t"
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" mov.l %1, @%2 \n\t"
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"1: mov r1, r15 \n\t"
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: "=&r" (ret), "=&r" (tmp)
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: "r" (v), "r" (a), "r" (u)
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: "memory" , "r0", "r1" , "t");
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return ret != u;
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}
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#endif /* __ASM_SH_ATOMIC_GRB_H */
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@ -17,7 +17,9 @@ typedef struct { volatile int counter; } atomic_t;
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#include <linux/compiler.h>
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#include <asm/system.h>
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#ifdef CONFIG_CPU_SH4A
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#if defined(CONFIG_GUSA_RB)
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#include <asm/atomic-grb.h>
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#elif defined(CONFIG_CPU_SH4A)
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#include <asm/atomic-llsc.h>
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#else
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#include <asm/atomic-irq.h>
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@ -44,6 +46,7 @@ typedef struct { volatile int counter; } atomic_t;
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#define atomic_inc(v) atomic_add(1,(v))
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#define atomic_dec(v) atomic_sub(1,(v))
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#ifndef CONFIG_GUSA_RB
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static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
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{
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int ret;
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@ -58,8 +61,6 @@ static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
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return ret;
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}
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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static inline int atomic_add_unless(atomic_t *v, int a, int u)
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{
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int ret;
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@ -73,6 +74,9 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u)
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return ret != u;
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}
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#endif
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
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/* Atomic operations are already serializing on SH */
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@ -0,0 +1,169 @@
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#ifndef __ASM_SH_BITOPS_GRB_H
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#define __ASM_SH_BITOPS_GRB_H
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static inline void set_bit(int nr, volatile void * addr)
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{
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int mask;
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volatile unsigned int *a = addr;
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unsigned long tmp;
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a += nr >> 5;
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mask = 1 << (nr & 0x1f);
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__asm__ __volatile__ (
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" .align 2 \n\t"
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" mova 1f, r0 \n\t" /* r0 = end point */
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" mov r15, r1 \n\t" /* r1 = saved sp */
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" mov #-6, r15 \n\t" /* LOGIN: r15 = size */
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" mov.l @%1, %0 \n\t" /* load old value */
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" or %2, %0 \n\t" /* or */
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" mov.l %0, @%1 \n\t" /* store new value */
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"1: mov r1, r15 \n\t" /* LOGOUT */
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: "=&r" (tmp),
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"+r" (a)
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: "r" (mask)
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: "memory" , "r0", "r1");
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}
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static inline void clear_bit(int nr, volatile void * addr)
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{
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int mask;
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volatile unsigned int *a = addr;
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unsigned long tmp;
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a += nr >> 5;
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mask = ~(1 << (nr & 0x1f));
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__asm__ __volatile__ (
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" .align 2 \n\t"
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" mova 1f, r0 \n\t" /* r0 = end point */
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" mov r15, r1 \n\t" /* r1 = saved sp */
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" mov #-6, r15 \n\t" /* LOGIN: r15 = size */
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" mov.l @%1, %0 \n\t" /* load old value */
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" and %2, %0 \n\t" /* and */
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" mov.l %0, @%1 \n\t" /* store new value */
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"1: mov r1, r15 \n\t" /* LOGOUT */
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: "=&r" (tmp),
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"+r" (a)
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: "r" (mask)
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: "memory" , "r0", "r1");
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}
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static inline void change_bit(int nr, volatile void * addr)
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{
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int mask;
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volatile unsigned int *a = addr;
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unsigned long tmp;
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a += nr >> 5;
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mask = 1 << (nr & 0x1f);
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__asm__ __volatile__ (
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" .align 2 \n\t"
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" mova 1f, r0 \n\t" /* r0 = end point */
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" mov r15, r1 \n\t" /* r1 = saved sp */
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" mov #-6, r15 \n\t" /* LOGIN: r15 = size */
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" mov.l @%1, %0 \n\t" /* load old value */
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" xor %2, %0 \n\t" /* xor */
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" mov.l %0, @%1 \n\t" /* store new value */
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"1: mov r1, r15 \n\t" /* LOGOUT */
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: "=&r" (tmp),
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"+r" (a)
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: "r" (mask)
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: "memory" , "r0", "r1");
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}
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static inline int test_and_set_bit(int nr, volatile void * addr)
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{
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int mask, retval;
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volatile unsigned int *a = addr;
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||||
unsigned long tmp;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
|
||||
__asm__ __volatile__ (
|
||||
" .align 2 \n\t"
|
||||
" mova 1f, r0 \n\t" /* r0 = end point */
|
||||
" mov r15, r1 \n\t" /* r1 = saved sp */
|
||||
" mov #-14, r15 \n\t" /* LOGIN: r15 = size */
|
||||
" mov.l @%2, %0 \n\t" /* load old value */
|
||||
" mov %0, %1 \n\t"
|
||||
" tst %1, %3 \n\t" /* T = ((*a & mask) == 0) */
|
||||
" mov #-1, %1 \n\t" /* retvat = -1 */
|
||||
" negc %1, %1 \n\t" /* retval = (mask & *a) != 0 */
|
||||
" or %3, %0 \n\t"
|
||||
" mov.l %0, @%2 \n\t" /* store new value */
|
||||
"1: mov r1, r15 \n\t" /* LOGOUT */
|
||||
: "=&r" (tmp),
|
||||
"=&r" (retval),
|
||||
"+r" (a)
|
||||
: "r" (mask)
|
||||
: "memory" , "r0", "r1" ,"t");
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static inline int test_and_clear_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask, retval,not_mask;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long tmp;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
|
||||
not_mask = ~mask;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
" .align 2 \n\t"
|
||||
" mova 1f, r0 \n\t" /* r0 = end point */
|
||||
" mov r15, r1 \n\t" /* r1 = saved sp */
|
||||
" mov #-14, r15 \n\t" /* LOGIN */
|
||||
" mov.l @%2, %0 \n\t" /* load old value */
|
||||
" mov %0, %1 \n\t" /* %1 = *a */
|
||||
" tst %1, %3 \n\t" /* T = ((*a & mask) == 0) */
|
||||
" mov #-1, %1 \n\t" /* retvat = -1 */
|
||||
" negc %1, %1 \n\t" /* retval = (mask & *a) != 0 */
|
||||
" and %4, %0 \n\t"
|
||||
" mov.l %0, @%2 \n\t" /* store new value */
|
||||
"1: mov r1, r15 \n\t" /* LOGOUT */
|
||||
: "=&r" (tmp),
|
||||
"=&r" (retval),
|
||||
"+r" (a)
|
||||
: "r" (mask),
|
||||
"r" (not_mask)
|
||||
: "memory" , "r0", "r1", "t");
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static inline int test_and_change_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long tmp;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
|
||||
__asm__ __volatile__ (
|
||||
" .align 2 \n\t"
|
||||
" mova 1f, r0 \n\t" /* r0 = end point */
|
||||
" mov r15, r1 \n\t" /* r1 = saved sp */
|
||||
" mov #-14, r15 \n\t" /* LOGIN */
|
||||
" mov.l @%2, %0 \n\t" /* load old value */
|
||||
" mov %0, %1 \n\t" /* %1 = *a */
|
||||
" tst %1, %3 \n\t" /* T = ((*a & mask) == 0) */
|
||||
" mov #-1, %1 \n\t" /* retvat = -1 */
|
||||
" negc %1, %1 \n\t" /* retval = (mask & *a) != 0 */
|
||||
" xor %3, %0 \n\t"
|
||||
" mov.l %0, @%2 \n\t" /* store new value */
|
||||
"1: mov r1, r15 \n\t" /* LOGOUT */
|
||||
: "=&r" (tmp),
|
||||
"=&r" (retval),
|
||||
"+r" (a)
|
||||
: "r" (mask)
|
||||
: "memory" , "r0", "r1", "t");
|
||||
|
||||
return retval;
|
||||
}
|
||||
#endif /* __ASM_SH_BITOPS_GRB_H */
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
#ifndef __ASM_SH_BITOPS_IRQ_H
|
||||
#define __ASM_SH_BITOPS_IRQ_H
|
||||
|
||||
static inline void set_bit(int nr, volatile void *addr)
|
||||
{
|
||||
int mask;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long flags;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
local_irq_save(flags);
|
||||
*a |= mask;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static inline void clear_bit(int nr, volatile void *addr)
|
||||
{
|
||||
int mask;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long flags;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
local_irq_save(flags);
|
||||
*a &= ~mask;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static inline void change_bit(int nr, volatile void *addr)
|
||||
{
|
||||
int mask;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long flags;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
local_irq_save(flags);
|
||||
*a ^= mask;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static inline int test_and_set_bit(int nr, volatile void *addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long flags;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
local_irq_save(flags);
|
||||
retval = (mask & *a) != 0;
|
||||
*a |= mask;
|
||||
local_irq_restore(flags);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static inline int test_and_clear_bit(int nr, volatile void *addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long flags;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
local_irq_save(flags);
|
||||
retval = (mask & *a) != 0;
|
||||
*a &= ~mask;
|
||||
local_irq_restore(flags);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static inline int test_and_change_bit(int nr, volatile void *addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long flags;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
local_irq_save(flags);
|
||||
retval = (mask & *a) != 0;
|
||||
*a ^= mask;
|
||||
local_irq_restore(flags);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
#endif /* __ASM_SH_BITOPS_IRQ_H */
|
||||
|
|
@ -11,97 +11,18 @@
|
|||
/* For __swab32 */
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
static inline void set_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long flags;
|
||||
#ifdef CONFIG_GUSA_RB
|
||||
#include <asm/bitops-grb.h>
|
||||
#else
|
||||
#include <asm/bitops-irq.h>
|
||||
#endif
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
local_irq_save(flags);
|
||||
*a |= mask;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
/*
|
||||
* clear_bit() doesn't provide any barrier for the compiler.
|
||||
*/
|
||||
#define smp_mb__before_clear_bit() barrier()
|
||||
#define smp_mb__after_clear_bit() barrier()
|
||||
static inline void clear_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long flags;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
local_irq_save(flags);
|
||||
*a &= ~mask;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static inline void change_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long flags;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
local_irq_save(flags);
|
||||
*a ^= mask;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static inline int test_and_set_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long flags;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
local_irq_save(flags);
|
||||
retval = (mask & *a) != 0;
|
||||
*a |= mask;
|
||||
local_irq_restore(flags);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static inline int test_and_clear_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long flags;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
local_irq_save(flags);
|
||||
retval = (mask & *a) != 0;
|
||||
*a &= ~mask;
|
||||
local_irq_restore(flags);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static inline int test_and_change_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long flags;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
local_irq_save(flags);
|
||||
retval = (mask & *a) != 0;
|
||||
*a ^= mask;
|
||||
local_irq_restore(flags);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
#include <asm-generic/bitops/non-atomic.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,70 @@
|
|||
#ifndef __ASM_SH_CMPXCHG_GRB_H
|
||||
#define __ASM_SH_CMPXCHG_GRB_H
|
||||
|
||||
static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
|
||||
{
|
||||
unsigned long retval;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
" .align 2 \n\t"
|
||||
" mova 1f, r0 \n\t" /* r0 = end point */
|
||||
" nop \n\t"
|
||||
" mov r15, r1 \n\t" /* r1 = saved sp */
|
||||
" mov #-4, r15 \n\t" /* LOGIN */
|
||||
" mov.l @%1, %0 \n\t" /* load old value */
|
||||
" mov.l %2, @%1 \n\t" /* store new value */
|
||||
"1: mov r1, r15 \n\t" /* LOGOUT */
|
||||
: "=&r" (retval),
|
||||
"+r" (m)
|
||||
: "r" (val)
|
||||
: "memory", "r0", "r1");
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
|
||||
{
|
||||
unsigned long retval;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
" .align 2 \n\t"
|
||||
" mova 1f, r0 \n\t" /* r0 = end point */
|
||||
" mov r15, r1 \n\t" /* r1 = saved sp */
|
||||
" mov #-6, r15 \n\t" /* LOGIN */
|
||||
" mov.b @%1, %0 \n\t" /* load old value */
|
||||
" extu.b %0, %0 \n\t" /* extend as unsigned */
|
||||
" mov.b %2, @%1 \n\t" /* store new value */
|
||||
"1: mov r1, r15 \n\t" /* LOGOUT */
|
||||
: "=&r" (retval),
|
||||
"+r" (m)
|
||||
: "r" (val)
|
||||
: "memory" , "r0", "r1");
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static inline unsigned long __cmpxchg_u32(volatile int *m, unsigned long old,
|
||||
unsigned long new)
|
||||
{
|
||||
unsigned long retval;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
" .align 2 \n\t"
|
||||
" mova 1f, r0 \n\t" /* r0 = end point */
|
||||
" nop \n\t"
|
||||
" mov r15, r1 \n\t" /* r1 = saved sp */
|
||||
" mov #-8, r15 \n\t" /* LOGIN */
|
||||
" mov.l @%1, %0 \n\t" /* load old value */
|
||||
" cmp/eq %0, %2 \n\t"
|
||||
" bf 1f \n\t" /* if not equal */
|
||||
" mov.l %2, @%1 \n\t" /* store new value */
|
||||
"1: mov r1, r15 \n\t" /* LOGOUT */
|
||||
: "=&r" (retval),
|
||||
"+r" (m)
|
||||
: "r" (new)
|
||||
: "memory" , "r0", "r1", "t");
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
#endif /* __ASM_SH_CMPXCHG_GRB_H */
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
#ifndef __ASM_SH_CMPXCHG_IRQ_H
|
||||
#define __ASM_SH_CMPXCHG_IRQ_H
|
||||
|
||||
static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
|
||||
{
|
||||
unsigned long flags, retval;
|
||||
|
||||
local_irq_save(flags);
|
||||
retval = *m;
|
||||
*m = val;
|
||||
local_irq_restore(flags);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
|
||||
{
|
||||
unsigned long flags, retval;
|
||||
|
||||
local_irq_save(flags);
|
||||
retval = *m;
|
||||
*m = val & 0xff;
|
||||
local_irq_restore(flags);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static inline unsigned long __cmpxchg_u32(volatile int *m, unsigned long old,
|
||||
unsigned long new)
|
||||
{
|
||||
__u32 retval;
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
retval = *m;
|
||||
if (retval == old)
|
||||
*m = new;
|
||||
local_irq_restore(flags); /* implies memory barrier */
|
||||
return retval;
|
||||
}
|
||||
|
||||
#endif /* __ASM_SH_CMPXCHG_IRQ_H */
|
||||
|
|
@ -68,27 +68,11 @@
|
|||
|
||||
#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
|
||||
|
||||
static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
|
||||
{
|
||||
unsigned long flags, retval;
|
||||
|
||||
local_irq_save(flags);
|
||||
retval = *m;
|
||||
*m = val;
|
||||
local_irq_restore(flags);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
|
||||
{
|
||||
unsigned long flags, retval;
|
||||
|
||||
local_irq_save(flags);
|
||||
retval = *m;
|
||||
*m = val & 0xff;
|
||||
local_irq_restore(flags);
|
||||
return retval;
|
||||
}
|
||||
#ifdef CONFIG_GUSA_RB
|
||||
#include <asm/cmpxchg-grb.h>
|
||||
#else
|
||||
#include <asm/cmpxchg-irq.h>
|
||||
#endif
|
||||
|
||||
extern void __xchg_called_with_bad_pointer(void);
|
||||
|
||||
|
|
@ -115,20 +99,6 @@ extern void __xchg_called_with_bad_pointer(void);
|
|||
#define xchg(ptr,x) \
|
||||
((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
|
||||
|
||||
static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
|
||||
unsigned long new)
|
||||
{
|
||||
__u32 retval;
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
retval = *m;
|
||||
if (retval == old)
|
||||
*m = new;
|
||||
local_irq_restore(flags); /* implies memory barrier */
|
||||
return retval;
|
||||
}
|
||||
|
||||
/* This function doesn't exist, so you'll get a linker error
|
||||
* if something tries to do an invalid cmpxchg(). */
|
||||
extern void __cmpxchg_called_with_bad_pointer(void);
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче