[ARM] pxa: move AC97 register definitions into dedicated regs-ac97.h
The optimal change would be to move the AC97 register definitions into the AC97 driver, unfortunately, the registers are shared between several files. Move them into a dedicated regs-ac97.h first. Signed-off-by: Eric Miao <eric.miao@marvell.com>
This commit is contained in:
Eric Miao
Родитель
02f652626a
Коммит
1f017a9964
|
|
@ -131,102 +131,6 @@
|
|||
* Serial Audio Controller - moved into sound/soc/pxa/pxa2xx-i2s.c
|
||||
*/
|
||||
|
||||
/*
|
||||
* AC97 Controller registers
|
||||
*/
|
||||
|
||||
#define POCR __REG(0x40500000) /* PCM Out Control Register */
|
||||
#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
|
||||
#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
|
||||
|
||||
#define PICR __REG(0x40500004) /* PCM In Control Register */
|
||||
#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
|
||||
#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
|
||||
|
||||
#define MCCR __REG(0x40500008) /* Mic In Control Register */
|
||||
#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
|
||||
#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
|
||||
|
||||
#define GCR __REG(0x4050000C) /* Global Control Register */
|
||||
#ifdef CONFIG_PXA3xx
|
||||
#define GCR_CLKBPB (1 << 31) /* Internal clock enable */
|
||||
#endif
|
||||
#define GCR_nDMAEN (1 << 24) /* non DMA Enable */
|
||||
#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
|
||||
#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
|
||||
#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
|
||||
#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
|
||||
#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
|
||||
#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
|
||||
#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
|
||||
#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
|
||||
#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
|
||||
#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
|
||||
|
||||
#define POSR __REG(0x40500010) /* PCM Out Status Register */
|
||||
#define POSR_FIFOE (1 << 4) /* FIFO error */
|
||||
#define POSR_FSR (1 << 2) /* FIFO Service Request */
|
||||
|
||||
#define PISR __REG(0x40500014) /* PCM In Status Register */
|
||||
#define PISR_FIFOE (1 << 4) /* FIFO error */
|
||||
#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
|
||||
#define PISR_FSR (1 << 2) /* FIFO Service Request */
|
||||
|
||||
#define MCSR __REG(0x40500018) /* Mic In Status Register */
|
||||
#define MCSR_FIFOE (1 << 4) /* FIFO error */
|
||||
#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
|
||||
#define MCSR_FSR (1 << 2) /* FIFO Service Request */
|
||||
|
||||
#define GSR __REG(0x4050001C) /* Global Status Register */
|
||||
#define GSR_CDONE (1 << 19) /* Command Done */
|
||||
#define GSR_SDONE (1 << 18) /* Status Done */
|
||||
#define GSR_RDCS (1 << 15) /* Read Completion Status */
|
||||
#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
|
||||
#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
|
||||
#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
|
||||
#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
|
||||
#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
|
||||
#define GSR_SCR (1 << 9) /* Secondary Codec Ready */
|
||||
#define GSR_PCR (1 << 8) /* Primary Codec Ready */
|
||||
#define GSR_MCINT (1 << 7) /* Mic In Interrupt */
|
||||
#define GSR_POINT (1 << 6) /* PCM Out Interrupt */
|
||||
#define GSR_PIINT (1 << 5) /* PCM In Interrupt */
|
||||
#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */
|
||||
#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
|
||||
#define GSR_MIINT (1 << 1) /* Modem In Interrupt */
|
||||
#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
|
||||
|
||||
#define CAR __REG(0x40500020) /* CODEC Access Register */
|
||||
#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
|
||||
|
||||
#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
|
||||
#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
|
||||
|
||||
#define MOCR __REG(0x40500100) /* Modem Out Control Register */
|
||||
#define MOCR_FEIE (1 << 3) /* FIFO Error */
|
||||
#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
|
||||
|
||||
#define MICR __REG(0x40500108) /* Modem In Control Register */
|
||||
#define MICR_FEIE (1 << 3) /* FIFO Error */
|
||||
#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
|
||||
|
||||
#define MOSR __REG(0x40500110) /* Modem Out Status Register */
|
||||
#define MOSR_FIFOE (1 << 4) /* FIFO error */
|
||||
#define MOSR_FSR (1 << 2) /* FIFO Service Request */
|
||||
|
||||
#define MISR __REG(0x40500118) /* Modem In Status Register */
|
||||
#define MISR_FIFOE (1 << 4) /* FIFO error */
|
||||
#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
|
||||
#define MISR_FSR (1 << 2) /* FIFO Service Request */
|
||||
|
||||
#define MODR __REG(0x40500140) /* Modem FIFO Data Register */
|
||||
|
||||
#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
|
||||
#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
|
||||
#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
|
||||
#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
|
||||
|
||||
|
||||
/*
|
||||
* Fast Infrared Communication Port - moved into drivers/net/irda/pxaficp_ir.c
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -0,0 +1,99 @@
|
|||
#ifndef __ASM_ARCH_REGS_AC97_H
|
||||
#define __ASM_ARCH_REGS_AC97_H
|
||||
|
||||
/*
|
||||
* AC97 Controller registers
|
||||
*/
|
||||
|
||||
#define POCR __REG(0x40500000) /* PCM Out Control Register */
|
||||
#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
|
||||
#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
|
||||
|
||||
#define PICR __REG(0x40500004) /* PCM In Control Register */
|
||||
#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
|
||||
#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
|
||||
|
||||
#define MCCR __REG(0x40500008) /* Mic In Control Register */
|
||||
#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
|
||||
#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
|
||||
|
||||
#define GCR __REG(0x4050000C) /* Global Control Register */
|
||||
#ifdef CONFIG_PXA3xx
|
||||
#define GCR_CLKBPB (1 << 31) /* Internal clock enable */
|
||||
#endif
|
||||
#define GCR_nDMAEN (1 << 24) /* non DMA Enable */
|
||||
#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
|
||||
#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
|
||||
#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
|
||||
#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
|
||||
#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
|
||||
#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
|
||||
#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
|
||||
#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
|
||||
#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
|
||||
#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
|
||||
|
||||
#define POSR __REG(0x40500010) /* PCM Out Status Register */
|
||||
#define POSR_FIFOE (1 << 4) /* FIFO error */
|
||||
#define POSR_FSR (1 << 2) /* FIFO Service Request */
|
||||
|
||||
#define PISR __REG(0x40500014) /* PCM In Status Register */
|
||||
#define PISR_FIFOE (1 << 4) /* FIFO error */
|
||||
#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
|
||||
#define PISR_FSR (1 << 2) /* FIFO Service Request */
|
||||
|
||||
#define MCSR __REG(0x40500018) /* Mic In Status Register */
|
||||
#define MCSR_FIFOE (1 << 4) /* FIFO error */
|
||||
#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
|
||||
#define MCSR_FSR (1 << 2) /* FIFO Service Request */
|
||||
|
||||
#define GSR __REG(0x4050001C) /* Global Status Register */
|
||||
#define GSR_CDONE (1 << 19) /* Command Done */
|
||||
#define GSR_SDONE (1 << 18) /* Status Done */
|
||||
#define GSR_RDCS (1 << 15) /* Read Completion Status */
|
||||
#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
|
||||
#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
|
||||
#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
|
||||
#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
|
||||
#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
|
||||
#define GSR_SCR (1 << 9) /* Secondary Codec Ready */
|
||||
#define GSR_PCR (1 << 8) /* Primary Codec Ready */
|
||||
#define GSR_MCINT (1 << 7) /* Mic In Interrupt */
|
||||
#define GSR_POINT (1 << 6) /* PCM Out Interrupt */
|
||||
#define GSR_PIINT (1 << 5) /* PCM In Interrupt */
|
||||
#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */
|
||||
#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
|
||||
#define GSR_MIINT (1 << 1) /* Modem In Interrupt */
|
||||
#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
|
||||
|
||||
#define CAR __REG(0x40500020) /* CODEC Access Register */
|
||||
#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
|
||||
|
||||
#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
|
||||
#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
|
||||
|
||||
#define MOCR __REG(0x40500100) /* Modem Out Control Register */
|
||||
#define MOCR_FEIE (1 << 3) /* FIFO Error */
|
||||
#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
|
||||
|
||||
#define MICR __REG(0x40500108) /* Modem In Control Register */
|
||||
#define MICR_FEIE (1 << 3) /* FIFO Error */
|
||||
#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
|
||||
|
||||
#define MOSR __REG(0x40500110) /* Modem Out Status Register */
|
||||
#define MOSR_FIFOE (1 << 4) /* FIFO error */
|
||||
#define MOSR_FSR (1 << 2) /* FIFO Service Request */
|
||||
|
||||
#define MISR __REG(0x40500118) /* Modem In Status Register */
|
||||
#define MISR_FIFOE (1 << 4) /* FIFO error */
|
||||
#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
|
||||
#define MISR_FSR (1 << 2) /* FIFO Service Request */
|
||||
|
||||
#define MODR __REG(0x40500140) /* Modem FIFO Data Register */
|
||||
|
||||
#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
|
||||
#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
|
||||
#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
|
||||
#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_AC97_H */
|
||||
|
|
@ -31,7 +31,7 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/wm97xx.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/pxa-regs.h>
|
||||
#include <mach/regs-ac97.h>
|
||||
|
||||
#define VERSION "0.13"
|
||||
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
|
||||
#include <asm/irq.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/pxa-regs.h>
|
||||
#include <mach/regs-ac97.h>
|
||||
#include <mach/pxa2xx-gpio.h>
|
||||
#include <mach/audio.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/pxa-regs.h>
|
||||
#include <mach/regs-ac97.h>
|
||||
#include <mach/audio.h>
|
||||
|
||||
#include "pxa2xx-pcm.h"
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/pxa-regs.h>
|
||||
#include <mach/regs-ac97.h>
|
||||
|
||||
#include "pxa2xx-pcm.h"
|
||||
#include "pxa2xx-ac97.h"
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче