powerpc: Fix some 6xx/7xxx CPU setup functions
Some of those functions try to adjust the CPU features, for example to remove NAP support on some revisions. However, they seem to use r5 as an index into the CPU table entry, which might have been right a long time ago but no longer is. r4 is the right register to use. This probably caused some off behaviours on some PowerMac variants using 750cx or 7455 processor revisions. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> CC: stable@kernel.org
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@ -18,7 +18,7 @@
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#include <asm/mmu.h>
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_GLOBAL(__setup_cpu_603)
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mflr r4
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mflr r5
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BEGIN_MMU_FTR_SECTION
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li r10,0
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mtspr SPRN_SPRG_603_LRU,r10 /* init SW LRU tracking */
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@ -27,60 +27,60 @@ BEGIN_FTR_SECTION
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bl __init_fpu_registers
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END_FTR_SECTION_IFCLR(CPU_FTR_FPU_UNAVAILABLE)
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bl setup_common_caches
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mtlr r4
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mtlr r5
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blr
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_GLOBAL(__setup_cpu_604)
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mflr r4
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mflr r5
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bl setup_common_caches
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bl setup_604_hid0
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mtlr r4
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mtlr r5
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blr
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_GLOBAL(__setup_cpu_750)
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mflr r4
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mflr r5
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bl __init_fpu_registers
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bl setup_common_caches
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bl setup_750_7400_hid0
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mtlr r4
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mtlr r5
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blr
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_GLOBAL(__setup_cpu_750cx)
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mflr r4
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mflr r5
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bl __init_fpu_registers
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bl setup_common_caches
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bl setup_750_7400_hid0
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bl setup_750cx
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mtlr r4
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mtlr r5
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blr
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_GLOBAL(__setup_cpu_750fx)
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mflr r4
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mflr r5
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bl __init_fpu_registers
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bl setup_common_caches
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bl setup_750_7400_hid0
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bl setup_750fx
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mtlr r4
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mtlr r5
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blr
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_GLOBAL(__setup_cpu_7400)
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mflr r4
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mflr r5
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bl __init_fpu_registers
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bl setup_7400_workarounds
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bl setup_common_caches
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bl setup_750_7400_hid0
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mtlr r4
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mtlr r5
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blr
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_GLOBAL(__setup_cpu_7410)
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mflr r4
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mflr r5
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bl __init_fpu_registers
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bl setup_7410_workarounds
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bl setup_common_caches
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bl setup_750_7400_hid0
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li r3,0
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mtspr SPRN_L2CR2,r3
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mtlr r4
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mtlr r5
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blr
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_GLOBAL(__setup_cpu_745x)
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mflr r4
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mflr r5
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bl setup_common_caches
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bl setup_745x_specifics
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mtlr r4
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mtlr r5
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blr
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/* Enable caches for 603's, 604, 750 & 7400 */
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@ -194,10 +194,10 @@ setup_750cx:
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cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
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cror 4*cr0+eq,4*cr0+eq,4*cr2+eq
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bnelr
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lwz r6,CPU_SPEC_FEATURES(r5)
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lwz r6,CPU_SPEC_FEATURES(r4)
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li r7,CPU_FTR_CAN_NAP
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andc r6,r6,r7
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stw r6,CPU_SPEC_FEATURES(r5)
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stw r6,CPU_SPEC_FEATURES(r4)
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blr
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/* 750fx specific
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@ -225,12 +225,12 @@ BEGIN_FTR_SECTION
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andis. r11,r11,L3CR_L3E@h
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beq 1f
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END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
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lwz r6,CPU_SPEC_FEATURES(r5)
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lwz r6,CPU_SPEC_FEATURES(r4)
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andi. r0,r6,CPU_FTR_L3_DISABLE_NAP
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beq 1f
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li r7,CPU_FTR_CAN_NAP
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andc r6,r6,r7
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stw r6,CPU_SPEC_FEATURES(r5)
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stw r6,CPU_SPEC_FEATURES(r4)
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1:
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mfspr r11,SPRN_HID0
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