[netdrvr] Remove long-unused bits from Becker template drivers
Symbols such as PCI_USES_IO, PCI_ADDR0, etc. originated from Donald Becker's net driver template, but have been long unused. Remove. In a few drivers, this allows the further eliminate of the pci_flags (or just plain flags) member in the template driver probe structure. Most of this logic is simply open-coded in most drivers, since it never changes. Made a few other cleanups while I was in there, too: * constify, __devinitdata several PCI ID tables * replace table terminating entries such as "{0,}," and "{NULL}," with a more-clean "{ }". Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Родитель
a2b524b2ec
Коммит
1f1bd5fc32
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@ -375,8 +375,7 @@ limit of 4K.
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of the drivers, and will likely be provided by some future kernel.
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*/
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enum pci_flags_bit {
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PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
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PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
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PCI_USES_MASTER=4,
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};
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enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
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@ -446,95 +445,95 @@ static struct vortex_chip_info {
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int io_size;
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} vortex_info_tbl[] __devinitdata = {
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{"3c590 Vortex 10Mbps",
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PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
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PCI_USES_MASTER, IS_VORTEX, 32, },
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{"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
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PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
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PCI_USES_MASTER, IS_VORTEX, 32, },
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{"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
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PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
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PCI_USES_MASTER, IS_VORTEX, 32, },
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{"3c595 Vortex 100baseTx",
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PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
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PCI_USES_MASTER, IS_VORTEX, 32, },
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{"3c595 Vortex 100baseT4",
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PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
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PCI_USES_MASTER, IS_VORTEX, 32, },
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{"3c595 Vortex 100base-MII",
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PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
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PCI_USES_MASTER, IS_VORTEX, 32, },
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{"3c900 Boomerang 10baseT",
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PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
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PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
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{"3c900 Boomerang 10Mbps Combo",
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PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
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PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
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{"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
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PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
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PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
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{"3c900 Cyclone 10Mbps Combo",
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PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
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PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
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{"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
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PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
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PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
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{"3c900B-FL Cyclone 10base-FL",
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PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
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PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
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{"3c905 Boomerang 100baseTx",
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PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
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PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
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{"3c905 Boomerang 100baseT4",
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PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
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PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
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{"3c905B Cyclone 100baseTx",
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PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
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PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
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{"3c905B Cyclone 10/100/BNC",
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PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
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PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
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{"3c905B-FX Cyclone 100baseFx",
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PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
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PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
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{"3c905C Tornado",
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PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
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PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
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{"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
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PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
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PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
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{"3c980 Cyclone",
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PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
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PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
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{"3c980C Python-T",
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PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
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PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
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{"3cSOHO100-TX Hurricane",
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PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
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PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
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{"3c555 Laptop Hurricane",
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PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
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PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
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{"3c556 Laptop Tornado",
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PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
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PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
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HAS_HWCKSM, 128, },
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{"3c556B Laptop Hurricane",
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PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
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PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
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WNO_XCVR_PWR|HAS_HWCKSM, 128, },
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{"3c575 [Megahertz] 10/100 LAN CardBus",
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PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
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PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
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{"3c575 Boomerang CardBus",
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PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
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PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
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{"3CCFE575BT Cyclone CardBus",
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PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
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PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
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INVERT_LED_PWR|HAS_HWCKSM, 128, },
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{"3CCFE575CT Tornado CardBus",
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PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
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PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
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MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
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{"3CCFE656 Cyclone CardBus",
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PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
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PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
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INVERT_LED_PWR|HAS_HWCKSM, 128, },
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{"3CCFEM656B Cyclone+Winmodem CardBus",
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PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
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PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
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INVERT_LED_PWR|HAS_HWCKSM, 128, },
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{"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
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PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
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PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
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MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
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{"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
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PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
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PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
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{"3c920 Tornado",
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PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
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PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
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{"3c982 Hydra Dual Port A",
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PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
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PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
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{"3c982 Hydra Dual Port B",
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PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
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PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
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{"3c905B-T4",
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PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
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PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
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{"3c920B-EMB-WNM Tornado",
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PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
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PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
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{NULL,}, /* NULL terminated list. */
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};
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@ -683,11 +683,6 @@ struct netdev_private {
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};
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/* The station address location in the EEPROM. */
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#ifdef MEM_MAPPING
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#define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_MEM | PCI_ADDR1)
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#else
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#define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_IO | PCI_ADDR0)
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#endif
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/* The struct pci_device_id consist of:
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vendor, device Vendor and device ID to match (or PCI_ANY_ID)
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subvendor, subdevice Subsystem vendor and device ID to match (or PCI_ANY_ID)
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@ -695,9 +690,10 @@ struct netdev_private {
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class_mask of the class are honored during the comparison.
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driver_data Data private to the driver.
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*/
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static struct pci_device_id rio_pci_tbl[] = {
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{0x1186, 0x4000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
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{0,}
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static const struct pci_device_id rio_pci_tbl[] = {
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{0x1186, 0x4000, PCI_ANY_ID, PCI_ANY_ID, },
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{ }
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};
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MODULE_DEVICE_TABLE (pci, rio_pci_tbl);
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#define TX_TIMEOUT (4*HZ)
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@ -278,11 +278,6 @@ having to sign an Intel NDA when I'm helping Intel sell their own product!
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static int speedo_found1(struct pci_dev *pdev, void __iomem *ioaddr, int fnd_cnt, int acpi_idle_state);
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enum pci_flags_bit {
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PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
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PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
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};
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/* Offsets to the various registers.
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All accesses need not be longword aligned. */
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enum speedo_offsets {
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@ -191,23 +191,10 @@ IVc. Errata
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*/
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enum pci_id_flags_bits {
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/* Set PCI command register bits before calling probe1(). */
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PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
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/* Read and map the single following PCI BAR. */
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PCI_ADDR0=0<<4, PCI_ADDR1=1<<4, PCI_ADDR2=2<<4, PCI_ADDR3=3<<4,
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PCI_ADDR_64BITS=0x100, PCI_NO_ACPI_WAKE=0x200, PCI_NO_MIN_LATENCY=0x400,
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};
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enum chip_capability_flags { MII_PWRDWN=1, TYPE2_INTR=2, NO_MII=4 };
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#define EPIC_TOTAL_SIZE 0x100
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#define USE_IO_OPS 1
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#ifdef USE_IO_OPS
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#define EPIC_IOTYPE PCI_USES_MASTER|PCI_USES_IO|PCI_ADDR0
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#else
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#define EPIC_IOTYPE PCI_USES_MASTER|PCI_USES_MEM|PCI_ADDR1
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#endif
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typedef enum {
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SMSC_83C170_0,
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@ -218,7 +205,6 @@ typedef enum {
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struct epic_chip_info {
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const char *name;
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enum pci_id_flags_bits pci_flags;
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int io_size; /* Needed for I/O region check or ioremap(). */
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int drv_flags; /* Driver use, intended as capability flags. */
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};
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@ -227,11 +213,11 @@ struct epic_chip_info {
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/* indexed by chip_t */
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static const struct epic_chip_info pci_id_tbl[] = {
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{ "SMSC EPIC/100 83c170",
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EPIC_IOTYPE, EPIC_TOTAL_SIZE, TYPE2_INTR | NO_MII | MII_PWRDWN },
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EPIC_TOTAL_SIZE, TYPE2_INTR | NO_MII | MII_PWRDWN },
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{ "SMSC EPIC/100 83c170",
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EPIC_IOTYPE, EPIC_TOTAL_SIZE, TYPE2_INTR },
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EPIC_TOTAL_SIZE, TYPE2_INTR },
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{ "SMSC EPIC/C 83c175",
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EPIC_IOTYPE, EPIC_TOTAL_SIZE, TYPE2_INTR | MII_PWRDWN },
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EPIC_TOTAL_SIZE, TYPE2_INTR | MII_PWRDWN },
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};
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@ -126,16 +126,6 @@ MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)");
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#define MIN_REGION_SIZE 136
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enum pci_flags_bit {
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PCI_USES_IO = 1,
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PCI_USES_MEM = 2,
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PCI_USES_MASTER = 4,
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PCI_ADDR0 = 0x10 << 0,
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PCI_ADDR1 = 0x10 << 1,
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PCI_ADDR2 = 0x10 << 2,
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PCI_ADDR3 = 0x10 << 3,
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};
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/* A chip capabilities table, matching the entries in pci_tbl[] above. */
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enum chip_capability_flags {
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HAS_MII_XCVR,
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@ -309,12 +309,6 @@ static int pcnet32_alloc_ring(struct net_device *dev, char *name);
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static void pcnet32_free_ring(struct net_device *dev);
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static void pcnet32_check_media(struct net_device *dev, int verbose);
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enum pci_flags_bit {
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PCI_USES_IO = 1, PCI_USES_MEM = 2, PCI_USES_MASTER = 4,
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PCI_ADDR0 = 0x10 << 0, PCI_ADDR1 = 0x10 << 1, PCI_ADDR2 =
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0x10 << 2, PCI_ADDR3 = 0x10 << 3,
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};
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static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
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{
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outw(index, addr + PCNET32_WIO_RAP);
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@ -212,26 +212,15 @@ Test with 'ping -s 10000' on a fast computer.
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/*
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PCI probe table.
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*/
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enum pci_id_flags_bits {
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/* Set PCI command register bits before calling probe1(). */
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PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
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/* Read and map the single following PCI BAR. */
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PCI_ADDR0=0<<4, PCI_ADDR1=1<<4, PCI_ADDR2=2<<4, PCI_ADDR3=3<<4,
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PCI_ADDR_64BITS=0x100, PCI_NO_ACPI_WAKE=0x200, PCI_NO_MIN_LATENCY=0x400,
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};
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enum chip_capability_flags {
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CanHaveMII=1, HasBrokenTx=2, AlwaysFDX=4, FDXOnNoMII=8,};
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#ifdef USE_IO_OPS
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#define W840_FLAGS (PCI_USES_IO | PCI_ADDR0 | PCI_USES_MASTER)
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#else
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#define W840_FLAGS (PCI_USES_MEM | PCI_ADDR1 | PCI_USES_MASTER)
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#endif
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CanHaveMII=1, HasBrokenTx=2, AlwaysFDX=4, FDXOnNoMII=8,
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};
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static struct pci_device_id w840_pci_tbl[] = {
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static const struct pci_device_id w840_pci_tbl[] = {
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{ 0x1050, 0x0840, PCI_ANY_ID, 0x8153, 0, 0, 0 },
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{ 0x1050, 0x0840, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
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{ 0x11f6, 0x2011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
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{ 0, }
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{ }
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};
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MODULE_DEVICE_TABLE(pci, w840_pci_tbl);
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@ -241,18 +230,17 @@ struct pci_id_info {
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int pci, pci_mask, subsystem, subsystem_mask;
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int revision, revision_mask; /* Only 8 bits. */
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} id;
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enum pci_id_flags_bits pci_flags;
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int io_size; /* Needed for I/O region check or ioremap(). */
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int drv_flags; /* Driver use, intended as capability flags. */
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};
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static struct pci_id_info pci_id_tbl[] = {
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{"Winbond W89c840", /* Sometime a Level-One switch card. */
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{ 0x08401050, 0xffffffff, 0x81530000, 0xffff0000 },
|
||||
W840_FLAGS, 128, CanHaveMII | HasBrokenTx | FDXOnNoMII},
|
||||
128, CanHaveMII | HasBrokenTx | FDXOnNoMII},
|
||||
{"Winbond W89c840", { 0x08401050, 0xffffffff, },
|
||||
W840_FLAGS, 128, CanHaveMII | HasBrokenTx},
|
||||
128, CanHaveMII | HasBrokenTx},
|
||||
{"Compex RL100-ATX", { 0x201111F6, 0xffffffff,},
|
||||
W840_FLAGS, 128, CanHaveMII | HasBrokenTx},
|
||||
128, CanHaveMII | HasBrokenTx},
|
||||
{NULL,}, /* 0 terminated list. */
|
||||
};
|
||||
|
||||
|
|
|
@ -234,14 +234,6 @@ See Packet Engines confidential appendix (prototype chips only).
|
|||
|
||||
|
||||
|
||||
enum pci_id_flags_bits {
|
||||
/* Set PCI command register bits before calling probe1(). */
|
||||
PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
|
||||
/* Read and map the single following PCI BAR. */
|
||||
PCI_ADDR0=0<<4, PCI_ADDR1=1<<4, PCI_ADDR2=2<<4, PCI_ADDR3=3<<4,
|
||||
PCI_ADDR_64BITS=0x100, PCI_NO_ACPI_WAKE=0x200, PCI_NO_MIN_LATENCY=0x400,
|
||||
PCI_UNUSED_IRQ=0x800,
|
||||
};
|
||||
enum capability_flags {
|
||||
HasMII=1, FullTxStatus=2, IsGigabit=4, HasMulticastBug=8, FullRxStatus=16,
|
||||
HasMACAddrBug=32, /* Only on early revs. */
|
||||
|
@ -249,11 +241,6 @@ enum capability_flags {
|
|||
};
|
||||
/* The PCI I/O space extent. */
|
||||
#define YELLOWFIN_SIZE 0x100
|
||||
#ifdef USE_IO_OPS
|
||||
#define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_IO | PCI_ADDR0)
|
||||
#else
|
||||
#define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_MEM | PCI_ADDR1)
|
||||
#endif
|
||||
|
||||
struct pci_id_info {
|
||||
const char *name;
|
||||
|
@ -261,24 +248,23 @@ struct pci_id_info {
|
|||
int pci, pci_mask, subsystem, subsystem_mask;
|
||||
int revision, revision_mask; /* Only 8 bits. */
|
||||
} id;
|
||||
enum pci_id_flags_bits pci_flags;
|
||||
int io_size; /* Needed for I/O region check or ioremap(). */
|
||||
int drv_flags; /* Driver use, intended as capability flags. */
|
||||
};
|
||||
|
||||
static const struct pci_id_info pci_id_tbl[] = {
|
||||
{"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff},
|
||||
PCI_IOTYPE, YELLOWFIN_SIZE,
|
||||
YELLOWFIN_SIZE,
|
||||
FullTxStatus | IsGigabit | HasMulticastBug | HasMACAddrBug | DontUseEeprom},
|
||||
{"Symbios SYM83C885", { 0x07011000, 0xffffffff},
|
||||
PCI_IOTYPE, YELLOWFIN_SIZE, HasMII | DontUseEeprom },
|
||||
{NULL,},
|
||||
YELLOWFIN_SIZE, HasMII | DontUseEeprom },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct pci_device_id yellowfin_pci_tbl[] = {
|
||||
static const struct pci_device_id yellowfin_pci_tbl[] = {
|
||||
{ 0x1000, 0x0702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
|
||||
{ 0x1000, 0x0701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
|
||||
{ 0, }
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE (pci, yellowfin_pci_tbl);
|
||||
|
||||
|
|
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