MIPS: MSA: Fix big-endian FPR_IDX implementation
The maximum word size is 64-bits since MSA state is saved using st.d which stores two 64-bit words, therefore reimplement FPR_IDX using xor, and only within each 64-bit word. Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9169/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -105,7 +105,7 @@ union fpureg {
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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# define FPR_IDX(width, idx) (idx)
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#else
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# define FPR_IDX(width, idx) ((FPU_REG_WIDTH / (width)) - 1 - (idx))
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# define FPR_IDX(width, idx) ((idx) ^ ((64 / (width)) - 1))
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#endif
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#define BUILD_FPR_ACCESS(width) \
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