Merge tag 'drm-intel-fixes-2018-11-15' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
- Fix Bugzilla #108712: Fix incorrect EU count report from kernel - Fix to account for scale factor when calculating initial phase on scaled output - Avoid too trigger-happy HPD storm detection and fix a race and an OOPS for MST systems. - Relocation race fix for Gen4/5 - A couple ICL fixes and dependencies for above Fixes:. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181115164709.GA13430@jlahtine-desk.ger.corp.intel.com
This commit is contained in:
Dave Airlie
Коммит
20325e8a61
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@ -474,7 +474,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
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u8 eu_disabled_mask;
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u32 n_disabled;
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if (!(sseu->subslice_mask[ss] & BIT(ss)))
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if (!(sseu->subslice_mask[s] & BIT(ss)))
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/* skip disabled subslice */
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continue;
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@ -4850,8 +4850,31 @@ static void cpt_verify_modeset(struct drm_device *dev, int pipe)
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* chroma samples for both of the luma samples, and thus we don't
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* actually get the expected MPEG2 chroma siting convention :(
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* The same behaviour is observed on pre-SKL platforms as well.
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*
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* Theory behind the formula (note that we ignore sub-pixel
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* source coordinates):
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* s = source sample position
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* d = destination sample position
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*
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* Downscaling 4:1:
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* -0.5
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* | 0.0
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* | | 1.5 (initial phase)
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* | | |
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* v v v
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* | s | s | s | s |
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* | d |
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*
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* Upscaling 1:4:
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* -0.5
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* | -0.375 (initial phase)
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* | | 0.0
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* | | |
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* v v v
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* | s |
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* | d | d | d | d |
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*/
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u16 skl_scaler_calc_phase(int sub, bool chroma_cosited)
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u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
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{
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int phase = -0x8000;
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u16 trip = 0;
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@ -4859,6 +4882,15 @@ u16 skl_scaler_calc_phase(int sub, bool chroma_cosited)
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if (chroma_cosited)
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phase += (sub - 1) * 0x8000 / sub;
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phase += scale / (2 * sub);
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/*
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* Hardware initial phase limited to [-0.5:1.5].
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* Since the max hardware scale factor is 3.0, we
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* should never actually excdeed 1.0 here.
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*/
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WARN_ON(phase < -0x8000 || phase > 0x18000);
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if (phase < 0)
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phase = 0x10000 + phase;
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else
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@ -5067,13 +5099,20 @@ static void skylake_pfit_enable(struct intel_crtc *crtc)
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if (crtc->config->pch_pfit.enabled) {
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u16 uv_rgb_hphase, uv_rgb_vphase;
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int pfit_w, pfit_h, hscale, vscale;
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int id;
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if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
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return;
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uv_rgb_hphase = skl_scaler_calc_phase(1, false);
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uv_rgb_vphase = skl_scaler_calc_phase(1, false);
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pfit_w = (crtc->config->pch_pfit.size >> 16) & 0xFFFF;
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pfit_h = crtc->config->pch_pfit.size & 0xFFFF;
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hscale = (crtc->config->pipe_src_w << 16) / pfit_w;
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vscale = (crtc->config->pipe_src_h << 16) / pfit_h;
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uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
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uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
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id = scaler_state->scaler_id;
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I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
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@ -452,6 +452,10 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
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if (!intel_connector)
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return NULL;
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intel_connector->get_hw_state = intel_dp_mst_get_hw_state;
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intel_connector->mst_port = intel_dp;
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intel_connector->port = port;
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connector = &intel_connector->base;
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ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,
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DRM_MODE_CONNECTOR_DisplayPort);
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@ -462,10 +466,6 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
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drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs);
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intel_connector->get_hw_state = intel_dp_mst_get_hw_state;
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intel_connector->mst_port = intel_dp;
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intel_connector->port = port;
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for_each_pipe(dev_priv, pipe) {
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struct drm_encoder *enc =
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&intel_dp->mst_encoders[pipe]->base.base;
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@ -1646,7 +1646,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
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void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state);
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u16 skl_scaler_calc_phase(int sub, bool chroma_center);
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u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
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int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
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int skl_max_scale(const struct intel_crtc_state *crtc_state,
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u32 pixel_format);
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@ -228,7 +228,9 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
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drm_for_each_connector_iter(connector, &conn_iter) {
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struct intel_connector *intel_connector = to_intel_connector(connector);
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if (intel_connector->encoder->hpd_pin == pin) {
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/* Don't check MST ports, they don't have pins */
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if (!intel_connector->mst_port &&
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intel_connector->encoder->hpd_pin == pin) {
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if (connector->polled != intel_connector->polled)
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DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
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connector->name);
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@ -395,37 +397,54 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
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struct intel_encoder *encoder;
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bool storm_detected = false;
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bool queue_dig = false, queue_hp = false;
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u32 long_hpd_pulse_mask = 0;
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u32 short_hpd_pulse_mask = 0;
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enum hpd_pin pin;
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if (!pin_mask)
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return;
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spin_lock(&dev_priv->irq_lock);
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for_each_intel_encoder(&dev_priv->drm, encoder) {
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enum hpd_pin pin = encoder->hpd_pin;
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bool has_hpd_pulse = intel_encoder_has_hpd_pulse(encoder);
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/*
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* Determine whether ->hpd_pulse() exists for each pin, and
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* whether we have a short or a long pulse. This is needed
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* as each pin may have up to two encoders (HDMI and DP) and
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* only the one of them (DP) will have ->hpd_pulse().
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*/
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for_each_intel_encoder(&dev_priv->drm, encoder) {
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bool has_hpd_pulse = intel_encoder_has_hpd_pulse(encoder);
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enum port port = encoder->port;
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bool long_hpd;
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pin = encoder->hpd_pin;
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if (!(BIT(pin) & pin_mask))
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continue;
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if (has_hpd_pulse) {
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bool long_hpd = long_mask & BIT(pin);
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enum port port = encoder->port;
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if (!has_hpd_pulse)
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continue;
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long_hpd = long_mask & BIT(pin);
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DRM_DEBUG_DRIVER("digital hpd port %c - %s\n", port_name(port),
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long_hpd ? "long" : "short");
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/*
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* For long HPD pulses we want to have the digital queue happen,
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* but we still want HPD storm detection to function.
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*/
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queue_dig = true;
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if (long_hpd) {
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dev_priv->hotplug.long_port_mask |= (1 << port);
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long_hpd_pulse_mask |= BIT(pin);
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dev_priv->hotplug.long_port_mask |= BIT(port);
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} else {
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/* for short HPD just trigger the digital queue */
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dev_priv->hotplug.short_port_mask |= (1 << port);
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short_hpd_pulse_mask |= BIT(pin);
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dev_priv->hotplug.short_port_mask |= BIT(port);
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}
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}
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/* Now process each pin just once */
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for_each_hpd_pin(pin) {
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bool long_hpd;
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if (!(BIT(pin) & pin_mask))
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continue;
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}
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}
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if (dev_priv->hotplug.stats[pin].state == HPD_DISABLED) {
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/*
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@ -442,11 +461,22 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
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if (dev_priv->hotplug.stats[pin].state != HPD_ENABLED)
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continue;
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if (!has_hpd_pulse) {
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/*
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* Delegate to ->hpd_pulse() if one of the encoders for this
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* pin has it, otherwise let the hotplug_work deal with this
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* pin directly.
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*/
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if (((short_hpd_pulse_mask | long_hpd_pulse_mask) & BIT(pin))) {
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long_hpd = long_hpd_pulse_mask & BIT(pin);
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} else {
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dev_priv->hotplug.event_bits |= BIT(pin);
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long_hpd = true;
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queue_hp = true;
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}
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if (!long_hpd)
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continue;
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if (intel_hpd_irq_storm_detect(dev_priv, pin)) {
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dev_priv->hotplug.event_bits &= ~BIT(pin);
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storm_detected = true;
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@ -424,7 +424,8 @@ static u64 execlists_update_context(struct i915_request *rq)
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reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
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/* True 32b PPGTT with dynamic page allocation: update PDP
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/*
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* True 32b PPGTT with dynamic page allocation: update PDP
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* registers and point the unallocated PDPs to scratch page.
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* PML4 is allocated during ppgtt init, so this is not needed
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* in 48-bit mode.
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@ -432,6 +433,17 @@ static u64 execlists_update_context(struct i915_request *rq)
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if (ppgtt && !i915_vm_is_48bit(&ppgtt->vm))
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execlists_update_context_pdps(ppgtt, reg_state);
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/*
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* Make sure the context image is complete before we submit it to HW.
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*
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* Ostensibly, writes (including the WCB) should be flushed prior to
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* an uncached write such as our mmio register access, the empirical
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* evidence (esp. on Braswell) suggests that the WC write into memory
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* may not be visible to the HW prior to the completion of the UC
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* register write and that we may begin execution from the context
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* before its image is complete leading to invalid PD chasing.
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*/
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wmb();
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return ce->lrc_desc;
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}
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|
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@ -91,6 +91,7 @@ static int
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gen4_render_ring_flush(struct i915_request *rq, u32 mode)
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{
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u32 cmd, *cs;
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int i;
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/*
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* read/write caches:
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|
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@ -127,12 +128,45 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode)
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cmd |= MI_INVALIDATE_ISP;
|
||||
}
|
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|
||||
cs = intel_ring_begin(rq, 2);
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i = 2;
|
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if (mode & EMIT_INVALIDATE)
|
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i += 20;
|
||||
|
||||
cs = intel_ring_begin(rq, i);
|
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if (IS_ERR(cs))
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return PTR_ERR(cs);
|
||||
|
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*cs++ = cmd;
|
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*cs++ = MI_NOOP;
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|
||||
/*
|
||||
* A random delay to let the CS invalidate take effect? Without this
|
||||
* delay, the GPU relocation path fails as the CS does not see
|
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* the updated contents. Just as important, if we apply the flushes
|
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* to the EMIT_FLUSH branch (i.e. immediately after the relocation
|
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* write and before the invalidate on the next batch), the relocations
|
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* still fail. This implies that is a delay following invalidation
|
||||
* that is required to reset the caches as opposed to a delay to
|
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* ensure the memory is written.
|
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*/
|
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if (mode & EMIT_INVALIDATE) {
|
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*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
|
||||
*cs++ = i915_ggtt_offset(rq->engine->scratch) |
|
||||
PIPE_CONTROL_GLOBAL_GTT;
|
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*cs++ = 0;
|
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*cs++ = 0;
|
||||
|
||||
for (i = 0; i < 12; i++)
|
||||
*cs++ = MI_FLUSH;
|
||||
|
||||
*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
|
||||
*cs++ = i915_ggtt_offset(rq->engine->scratch) |
|
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PIPE_CONTROL_GLOBAL_GTT;
|
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*cs++ = 0;
|
||||
*cs++ = 0;
|
||||
}
|
||||
|
||||
*cs++ = cmd;
|
||||
|
||||
intel_ring_advance(rq, cs);
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -2748,6 +2748,12 @@ static const struct i915_power_well_desc icl_power_wells[] = {
|
|||
.hsw.has_fuses = true,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "DC off",
|
||||
.domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
|
||||
.ops = &gen9_dc_off_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
},
|
||||
{
|
||||
.name = "power well 2",
|
||||
.domains = ICL_PW_2_POWER_DOMAINS,
|
||||
|
|
@ -2759,12 +2765,6 @@ static const struct i915_power_well_desc icl_power_wells[] = {
|
|||
.hsw.has_fuses = true,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "DC off",
|
||||
.domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
|
||||
.ops = &gen9_dc_off_power_well_ops,
|
||||
.id = DISP_PW_ID_NONE,
|
||||
},
|
||||
{
|
||||
.name = "power well 3",
|
||||
.domains = ICL_PW_3_POWER_DOMAINS,
|
||||
|
|
@ -3176,8 +3176,7 @@ static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
|
|||
void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
|
||||
u8 req_slices)
|
||||
{
|
||||
u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
|
||||
u32 val;
|
||||
const u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
|
||||
bool ret;
|
||||
|
||||
if (req_slices > intel_dbuf_max_slices(dev_priv)) {
|
||||
|
|
@ -3188,7 +3187,6 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
|
|||
if (req_slices == hw_enabled_slices || req_slices == 0)
|
||||
return;
|
||||
|
||||
val = I915_READ(DBUF_CTL_S2);
|
||||
if (req_slices > hw_enabled_slices)
|
||||
ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true);
|
||||
else
|
||||
|
|
|
|||
|
|
@ -302,13 +302,65 @@ skl_plane_max_stride(struct intel_plane *plane,
|
|||
return min(8192 * cpp, 32768);
|
||||
}
|
||||
|
||||
static void
|
||||
skl_program_scaler(struct intel_plane *plane,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
const struct intel_plane_state *plane_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
|
||||
enum pipe pipe = plane->pipe;
|
||||
int scaler_id = plane_state->scaler_id;
|
||||
const struct intel_scaler *scaler =
|
||||
&crtc_state->scaler_state.scalers[scaler_id];
|
||||
int crtc_x = plane_state->base.dst.x1;
|
||||
int crtc_y = plane_state->base.dst.y1;
|
||||
uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
|
||||
uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
|
||||
u16 y_hphase, uv_rgb_hphase;
|
||||
u16 y_vphase, uv_rgb_vphase;
|
||||
int hscale, vscale;
|
||||
|
||||
hscale = drm_rect_calc_hscale(&plane_state->base.src,
|
||||
&plane_state->base.dst,
|
||||
0, INT_MAX);
|
||||
vscale = drm_rect_calc_vscale(&plane_state->base.src,
|
||||
&plane_state->base.dst,
|
||||
0, INT_MAX);
|
||||
|
||||
/* TODO: handle sub-pixel coordinates */
|
||||
if (plane_state->base.fb->format->format == DRM_FORMAT_NV12) {
|
||||
y_hphase = skl_scaler_calc_phase(1, hscale, false);
|
||||
y_vphase = skl_scaler_calc_phase(1, vscale, false);
|
||||
|
||||
/* MPEG2 chroma siting convention */
|
||||
uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
|
||||
uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
|
||||
} else {
|
||||
/* not used */
|
||||
y_hphase = 0;
|
||||
y_vphase = 0;
|
||||
|
||||
uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
|
||||
uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
|
||||
}
|
||||
|
||||
I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
|
||||
PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode);
|
||||
I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
|
||||
I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
|
||||
PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
|
||||
I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
|
||||
PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
|
||||
I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
|
||||
I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h);
|
||||
}
|
||||
|
||||
void
|
||||
skl_update_plane(struct intel_plane *plane,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
const struct intel_plane_state *plane_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
|
||||
const struct drm_framebuffer *fb = plane_state->base.fb;
|
||||
enum plane_id plane_id = plane->id;
|
||||
enum pipe pipe = plane->pipe;
|
||||
u32 plane_ctl = plane_state->ctl;
|
||||
|
|
@ -318,8 +370,6 @@ skl_update_plane(struct intel_plane *plane,
|
|||
u32 aux_stride = skl_plane_stride(plane_state, 1);
|
||||
int crtc_x = plane_state->base.dst.x1;
|
||||
int crtc_y = plane_state->base.dst.y1;
|
||||
uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
|
||||
uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
|
||||
uint32_t x = plane_state->color_plane[0].x;
|
||||
uint32_t y = plane_state->color_plane[0].y;
|
||||
uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
|
||||
|
|
@ -329,8 +379,6 @@ skl_update_plane(struct intel_plane *plane,
|
|||
/* Sizes are 0 based */
|
||||
src_w--;
|
||||
src_h--;
|
||||
crtc_w--;
|
||||
crtc_h--;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
|
||||
|
||||
|
|
@ -353,41 +401,8 @@ skl_update_plane(struct intel_plane *plane,
|
|||
(plane_state->color_plane[1].y << 16) |
|
||||
plane_state->color_plane[1].x);
|
||||
|
||||
/* program plane scaler */
|
||||
if (plane_state->scaler_id >= 0) {
|
||||
int scaler_id = plane_state->scaler_id;
|
||||
const struct intel_scaler *scaler =
|
||||
&crtc_state->scaler_state.scalers[scaler_id];
|
||||
u16 y_hphase, uv_rgb_hphase;
|
||||
u16 y_vphase, uv_rgb_vphase;
|
||||
|
||||
/* TODO: handle sub-pixel coordinates */
|
||||
if (fb->format->format == DRM_FORMAT_NV12) {
|
||||
y_hphase = skl_scaler_calc_phase(1, false);
|
||||
y_vphase = skl_scaler_calc_phase(1, false);
|
||||
|
||||
/* MPEG2 chroma siting convention */
|
||||
uv_rgb_hphase = skl_scaler_calc_phase(2, true);
|
||||
uv_rgb_vphase = skl_scaler_calc_phase(2, false);
|
||||
} else {
|
||||
/* not used */
|
||||
y_hphase = 0;
|
||||
y_vphase = 0;
|
||||
|
||||
uv_rgb_hphase = skl_scaler_calc_phase(1, false);
|
||||
uv_rgb_vphase = skl_scaler_calc_phase(1, false);
|
||||
}
|
||||
|
||||
I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
|
||||
PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
|
||||
I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
|
||||
I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
|
||||
PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
|
||||
I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
|
||||
PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
|
||||
I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
|
||||
I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
|
||||
((crtc_w + 1) << 16)|(crtc_h + 1));
|
||||
skl_program_scaler(plane, crtc_state, plane_state);
|
||||
|
||||
I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
|
||||
} else {
|
||||
|
|
|
|||
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