ARM: SoC fixes for 4.17-rc
A handful of fixes. I've been queuing them up a bit too long so the list is longer than it otherwise would have been spread out across a few -rcs. In general, it's a scattering of fixes across several platforms, nothing truly serious enough to point out. There's a slightly larger batch of them for the Davinci platforms due to work to bring them back to life after some time, so there's a handful of regressions, some of them going back very far, others more recent. There's also a few patches fixing DT on Renesas platforms since they changed some bindings without remaining backwards compatible, splitting up describing LVDS as a proper bridge instead of having it as part of the display unit. We could push for them to be backwards compatible with old device trees, but it's likely to regress eventually if nobody's actually using said compatibility. -----BEGIN PGP SIGNATURE----- iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAlsAzEkPHG9sb2ZAbGl4 b20ubmV0AAoJEIwa5zzehBx34V0P/1EEUPSF6o3lplpAFHAnXGaaRyHDF07TXkEj zjceoOPLljrynQJ23HdjRlfh2f51rWD2XjGzlScsTJ8HXYe+auMSCRBRYjwl1RVt zAQs2+png4pPbrxw6AUJ9CTSmCUPna0dGdySEl3FfxSt7+UdonldEJr+ZvNESiW7 +jSF3twZ/hb6iOxq7xFSnh8GU0ckTm11/HUCxQ/8z4xRfGvENs66Z7cyaStkzLop cD7wUmwe1I0HsRWkDsGUUQwu6i445edVoELWmooZByXuGWjb3Vu9xmc+yrgQTLkW 4Y3R4kx5VfDfvdN3i2z+W7ZpN47dSkAOMIbjQYl0wELdk0UPaMFTse6mDfIBmC02 dSK2FLpZYsBQX95KxQijh4jBPs+lJsekJd1qxL3ZGpSK0VF1etGhSWrkRQ0pXNmT 4VahLoEY8KBvGKZo1QJ4U2pmAIZS3oMrK9AdJANdpyN0cEiYFl1JTM9PkZfytnLU haagJL3BJESD36vuAhhvXVWy7vuI5jXnATn9V2WH8yZVMCPh3vsPA+d9Knh3ZqXk Vv1yZriJyX3zV6kbFoXJsOqg0TgGsyICBSpnjfuQPTtWSdSvlrUuIINFPOqE5Z3E uFywFEkw1L8ZXxbQn8m92+VqiqeFjyhqWmK2OolQfWlDJlJrmF8ltmkeMv9EQaig +wh8OuSw =qPpk -----END PGP SIGNATURE----- Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "A handful of fixes. I've been queuing them up a bit too long so the list is longer than it otherwise would have been spread out across a few -rcs. In general, it's a scattering of fixes across several platforms, nothing truly serious enough to point out. There's a slightly larger batch of them for the Davinci platforms due to work to bring them back to life after some time, so there's a handful of regressions, some of them going back very far, others more recent. There's also a few patches fixing DT on Renesas platforms since they changed some bindings without remaining backwards compatible, splitting up describing LVDS as a proper bridge instead of having it as part of the display unit. We could push for them to be backwards compatible with old device trees, but it's likely to regress eventually if nobody's actually using said compatibility" * tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (36 commits) ARM: davinci: board-dm646x-evm: set VPIF capture card name ARM: davinci: board-dm646x-evm: pass correct I2C adapter id for VPIF ARM: davinci: dm646x: fix timer interrupt generation ARM: keystone: fix platform_domain_notifier array overrun arm64: dts: exynos: Fix interrupt type for I2S1 device on Exynos5433 ARM: dts: imx51-zii-rdu1: fix touchscreen bindings firmware: arm_scmi: Use after free in scmi_create_protocol_device() ARM: dts: cygnus: fix irq type for arm global timer Revert "ARM: dts: logicpd-som-lv: Fix pinmux controller references" tee: check shm references are consistent in offset/size tee: shm: fix use-after-free via temporarily dropped reference ARM: dts: imx7s: Pass the 'fsl,sec-era' property ARM: dts: tegra20: Revert "Fix ULPI regression on Tegra20" ARM: dts: correct missing "compatible" entry for ti81xx SoCs ARM: OMAP1: ams-delta: fix deferred_fiq handler arm64: tegra: Make BCM89610 PHY interrupt as active low ARM: davinci: fix GPIO lookup for I2C ARM: dts: logicpd-som-lv: Fix pinmux controller references ARM: dts: logicpd-som-lv: Fix Audio Mute ARM: dts: logicpd-som-lv: Fix WL127x Startup Issues ...
This commit is contained in:
Коммит
203ec2fed1
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@ -21,9 +21,10 @@ Required properties:
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- main controller clock (for both armada-375-pp2 and armada-7k-pp2)
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- GOP clock (for both armada-375-pp2 and armada-7k-pp2)
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- MG clock (only for armada-7k-pp2)
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- MG Core clock (only for armada-7k-pp2)
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- AXI clock (only for armada-7k-pp2)
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- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk"
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and "axi_clk" (the 2 latter only for armada-7k-pp2).
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- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk",
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"mg_core_clk" and "axi_clk" (the 3 latter only for armada-7k-pp2).
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The ethernet ports are represented by subnodes. At least one port is
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required.
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@ -80,8 +81,8 @@ cpm_ethernet: ethernet@0 {
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compatible = "marvell,armada-7k-pp22";
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reg = <0x0 0x100000>, <0x129000 0xb000>;
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clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>,
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<&cpm_syscon0 1 5>, <&cpm_syscon0 1 18>;
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clock-names = "pp_clk", "gop_clk", "gp_clk", "axi_clk";
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<&cpm_syscon0 1 5>, <&cpm_syscon0 1 6>, <&cpm_syscon0 1 18>;
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clock-names = "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_clk";
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eth0: eth0 {
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interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
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@ -69,7 +69,7 @@
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timer@20200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x20200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
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clocks = <&periph_clk>;
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};
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@ -21,8 +21,8 @@
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stdout-path = "serial2:115200n8";
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};
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memory {
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device_type = "memory";
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memory@c0000000 {
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/* 128 MB DDR2 SDRAM @ 0xc0000000 */
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reg = <0xc0000000 0x08000000>;
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};
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@ -7,10 +7,19 @@
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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chosen { };
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aliases { };
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memory@c0000000 {
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device_type = "memory";
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reg = <0xc0000000 0x0>;
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};
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arm {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -46,8 +55,6 @@
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pmx_core: pinmux@14120 {
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compatible = "pinctrl-single";
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reg = <0x14120 0x50>;
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#address-cells = <1>;
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#size-cells = <0>;
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#pinctrl-cells = <2>;
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pinctrl-single,bit-per-mux;
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pinctrl-single,register-width = <32>;
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@ -10,7 +10,7 @@
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/ {
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model = "DM8148 EVM";
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compatible = "ti,dm8148-evm", "ti,dm8148";
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compatible = "ti,dm8148-evm", "ti,dm8148", "ti,dm814";
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memory@80000000 {
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device_type = "memory";
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|
|
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@ -9,7 +9,7 @@
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/ {
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model = "HP t410 Smart Zero Client";
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compatible = "hp,t410", "ti,dm8148";
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compatible = "hp,t410", "ti,dm8148", "ti,dm814";
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memory@80000000 {
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device_type = "memory";
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|
|
|
@ -10,7 +10,7 @@
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/ {
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model = "DM8168 EVM";
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compatible = "ti,dm8168-evm", "ti,dm8168";
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compatible = "ti,dm8168-evm", "ti,dm8168", "ti,dm816";
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memory@80000000 {
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device_type = "memory";
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|
|
|
@ -10,7 +10,7 @@
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/ {
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model = "DRA62x J5 Eco EVM";
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compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148";
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compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148", "ti,dm814";
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memory@80000000 {
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device_type = "memory";
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|
|
|
@ -523,7 +523,7 @@
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};
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touchscreen@20 {
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compatible = "syna,rmi4_i2c";
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compatible = "syna,rmi4-i2c";
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reg = <0x20>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ts>;
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@ -541,8 +541,8 @@
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rmi4-f11@11 {
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reg = <0x11>;
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touch-inverted-y;
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touch-swapped-x-y;
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touchscreen-inverted-y;
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touchscreen-swapped-x-y;
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syna,sensor-type = <1>;
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};
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};
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|
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@ -868,6 +868,7 @@
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crypto: caam@30900000 {
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compatible = "fsl,sec-v4.0";
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fsl,sec-era = <8>;
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x30900000 0x40000>;
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@ -26,7 +26,7 @@
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gpio = <&gpio1 3 0>; /* gpio_3 */
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startup-delay-us = <70000>;
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enable-active-high;
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vin-supply = <&vmmc2>;
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vin-supply = <&vaux3>;
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};
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/* HS USB Host PHY on PORT 1 */
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@ -82,6 +82,7 @@
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twl_audio: audio {
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compatible = "ti,twl4030-audio";
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codec {
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ti,hs_extmute_gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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@ -199,6 +200,7 @@
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
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OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
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OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */
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>;
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};
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};
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@ -213,7 +215,7 @@
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};
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wl127x_gpio: pinmux_wl127x_gpio_pin {
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pinctrl-single,pins = <
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OMAP3_WKUP_IOPAD(0x2a0c, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */
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OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */
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OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
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>;
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};
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@ -260,6 +262,11 @@
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#include "twl4030.dtsi"
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#include "twl4030_omap3.dtsi"
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&vaux3 {
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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};
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&twl {
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twl_power: power {
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compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";
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@ -379,7 +379,7 @@
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port@0 {
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reg = <0>;
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adv7511_in: endpoint {
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remote-endpoint = <&du_out_lvds0>;
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remote-endpoint = <&lvds0_out>;
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};
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};
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@ -467,10 +467,8 @@
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status = "okay";
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clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
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<&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
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<&x13_clk>, <&x2_clk>;
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clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1",
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"dclkin.0", "dclkin.1";
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clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1";
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ports {
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port@0 {
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@ -478,12 +476,26 @@
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remote-endpoint = <&adv7123_in>;
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};
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};
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};
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};
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&lvds0 {
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status = "okay";
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ports {
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port@1 {
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endpoint {
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remote-endpoint = <&adv7511_in>;
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};
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};
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port@2 {
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};
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};
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&lvds1 {
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status = "okay";
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ports {
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port@1 {
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lvds_connector: endpoint {
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};
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};
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@ -1627,18 +1627,13 @@
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du: display@feb00000 {
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compatible = "renesas,du-r8a7790";
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reg = <0 0xfeb00000 0 0x70000>,
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<0 0xfeb90000 0 0x1c>,
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<0 0xfeb94000 0 0x1c>;
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reg-names = "du", "lvds.0", "lvds.1";
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reg = <0 0xfeb00000 0 0x70000>;
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interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
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<&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>,
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<&cpg CPG_MOD 725>;
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clock-names = "du.0", "du.1", "du.2", "lvds.0",
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"lvds.1";
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<&cpg CPG_MOD 722>;
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clock-names = "du.0", "du.1", "du.2";
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status = "disabled";
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ports {
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@ -1653,11 +1648,65 @@
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port@1 {
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reg = <1>;
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du_out_lvds0: endpoint {
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remote-endpoint = <&lvds0_in>;
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};
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};
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port@2 {
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reg = <2>;
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du_out_lvds1: endpoint {
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remote-endpoint = <&lvds1_in>;
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};
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};
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};
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};
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lvds0: lvds@feb90000 {
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compatible = "renesas,r8a7790-lvds";
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reg = <0 0xfeb90000 0 0x1c>;
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clocks = <&cpg CPG_MOD 726>;
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power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
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resets = <&cpg 726>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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|
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port@0 {
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reg = <0>;
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lvds0_in: endpoint {
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remote-endpoint = <&du_out_lvds0>;
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};
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};
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port@1 {
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reg = <1>;
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lvds0_out: endpoint {
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};
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};
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};
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};
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lvds1: lvds@feb94000 {
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compatible = "renesas,r8a7790-lvds";
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reg = <0 0xfeb94000 0 0x1c>;
|
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clocks = <&cpg CPG_MOD 725>;
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power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
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resets = <&cpg 725>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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|
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port@0 {
|
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reg = <0>;
|
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lvds1_in: endpoint {
|
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remote-endpoint = <&du_out_lvds1>;
|
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};
|
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};
|
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port@1 {
|
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reg = <1>;
|
||||
lvds1_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -468,10 +468,9 @@
|
|||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
|
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clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
|
||||
<&x13_clk>, <&x2_clk>;
|
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clock-names = "du.0", "du.1", "lvds.0",
|
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"dclkin.0", "dclkin.1";
|
||||
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
|
@ -479,6 +478,13 @@
|
|||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
lvds_connector: endpoint {
|
||||
};
|
||||
|
|
|
@ -441,10 +441,9 @@
|
|||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
|
||||
<&x3_clk>, <&x16_clk>;
|
||||
clock-names = "du.0", "du.1", "lvds.0",
|
||||
"dclkin.0", "dclkin.1";
|
||||
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
|
@ -455,6 +454,17 @@
|
|||
};
|
||||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
lvds_connector: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&ssi_pins &audio_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
|
@ -1633,15 +1633,12 @@
|
|||
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a7791";
|
||||
reg = <0 0xfeb00000 0 0x40000>,
|
||||
<0 0xfeb90000 0 0x1c>;
|
||||
reg-names = "du", "lvds.0";
|
||||
reg = <0 0xfeb00000 0 0x40000>;
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 726>;
|
||||
clock-names = "du.0", "du.1", "lvds.0";
|
||||
<&cpg CPG_MOD 723>;
|
||||
clock-names = "du.0", "du.1";
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
|
@ -1656,6 +1653,33 @@
|
|||
port@1 {
|
||||
reg = <1>;
|
||||
du_out_lvds0: endpoint {
|
||||
remote-endpoint = <&lvds0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds0: lvds@feb90000 {
|
||||
compatible = "renesas,r8a7791-lvds";
|
||||
reg = <0 0xfeb90000 0 0x1c>;
|
||||
clocks = <&cpg CPG_MOD 726>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 726>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
lvds0_in: endpoint {
|
||||
remote-endpoint = <&du_out_lvds0>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -447,10 +447,9 @@
|
|||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
|
||||
<&x13_clk>, <&x2_clk>;
|
||||
clock-names = "du.0", "du.1", "lvds.0",
|
||||
"dclkin.0", "dclkin.1";
|
||||
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
|
@ -458,6 +457,11 @@
|
|||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lvds0 {
|
||||
ports {
|
||||
port@1 {
|
||||
lvds_connector: endpoint {
|
||||
};
|
||||
|
|
|
@ -1292,15 +1292,12 @@
|
|||
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a7793";
|
||||
reg = <0 0xfeb00000 0 0x40000>,
|
||||
<0 0xfeb90000 0 0x1c>;
|
||||
reg-names = "du", "lvds.0";
|
||||
reg = <0 0xfeb00000 0 0x40000>;
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 726>;
|
||||
clock-names = "du.0", "du.1", "lvds.0";
|
||||
<&cpg CPG_MOD 723>;
|
||||
clock-names = "du.0", "du.1";
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
|
@ -1315,6 +1312,34 @@
|
|||
port@1 {
|
||||
reg = <1>;
|
||||
du_out_lvds0: endpoint {
|
||||
remote-endpoint = <&lvds0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds0: lvds@feb90000 {
|
||||
compatible = "renesas,r8a7793-lvds";
|
||||
reg = <0 0xfeb90000 0 0x1c>;
|
||||
clocks = <&cpg CPG_MOD 726>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 726>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
lvds0_in: endpoint {
|
||||
remote-endpoint = <&du_out_lvds0>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -741,7 +741,7 @@
|
|||
phy_type = "ulpi";
|
||||
clocks = <&tegra_car TEGRA20_CLK_USB2>,
|
||||
<&tegra_car TEGRA20_CLK_PLL_U>,
|
||||
<&tegra_car TEGRA20_CLK_PLL_P_OUT4>;
|
||||
<&tegra_car TEGRA20_CLK_CDEV2>;
|
||||
clock-names = "reg", "pll_u", "ulpi-link";
|
||||
resets = <&tegra_car 58>, <&tegra_car 22>;
|
||||
reset-names = "usb", "utmi-pads";
|
||||
|
|
|
@ -205,12 +205,17 @@ static const short da830_evm_mmc_sd_pins[] = {
|
|||
-1
|
||||
};
|
||||
|
||||
#define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1)
|
||||
#define DA830_MMCSD_CD_PIN GPIO_TO_PIN(2, 2)
|
||||
|
||||
static struct gpiod_lookup_table mmc_gpios_table = {
|
||||
.dev_id = "da830-mmc.0",
|
||||
.table = {
|
||||
/* gpio chip 1 contains gpio range 32-63 */
|
||||
GPIO_LOOKUP("davinci_gpio.1", 2, "cd", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("davinci_gpio.1", 1, "wp", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("davinci_gpio.0", DA830_MMCSD_CD_PIN, "cd",
|
||||
GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("davinci_gpio.0", DA830_MMCSD_WP_PIN, "wp",
|
||||
GPIO_ACTIVE_LOW),
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
@ -763,12 +763,17 @@ static const short da850_evm_mcasp_pins[] __initconst = {
|
|||
-1
|
||||
};
|
||||
|
||||
#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0)
|
||||
#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1)
|
||||
|
||||
static struct gpiod_lookup_table mmc_gpios_table = {
|
||||
.dev_id = "da830-mmc.0",
|
||||
.table = {
|
||||
/* gpio chip 2 contains gpio range 64-95 */
|
||||
GPIO_LOOKUP("davinci_gpio.2", 0, "cd", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("davinci_gpio.2", 1, "wp", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("davinci_gpio.0", DA850_MMCSD_CD_PIN, "cd",
|
||||
GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("davinci_gpio.0", DA850_MMCSD_WP_PIN, "wp",
|
||||
GPIO_ACTIVE_LOW),
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/gpio.h>
|
||||
#include <linux/gpio/machine.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/dm9000.h>
|
||||
#include <linux/videodev2.h>
|
||||
#include <media/i2c/tvp514x.h>
|
||||
#include <linux/spi/spi.h>
|
||||
|
@ -109,12 +110,15 @@ static struct platform_device davinci_nand_device = {
|
|||
},
|
||||
};
|
||||
|
||||
#define DM355_I2C_SDA_PIN GPIO_TO_PIN(0, 15)
|
||||
#define DM355_I2C_SCL_PIN GPIO_TO_PIN(0, 14)
|
||||
|
||||
static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
|
||||
.dev_id = "i2c_davinci",
|
||||
.dev_id = "i2c_davinci.1",
|
||||
.table = {
|
||||
GPIO_LOOKUP("davinci_gpio", 15, "sda",
|
||||
GPIO_LOOKUP("davinci_gpio.0", DM355_I2C_SDA_PIN, "sda",
|
||||
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
|
||||
GPIO_LOOKUP("davinci_gpio", 14, "scl",
|
||||
GPIO_LOOKUP("davinci_gpio.0", DM355_I2C_SCL_PIN, "scl",
|
||||
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
|
||||
},
|
||||
};
|
||||
|
@ -179,11 +183,16 @@ static struct resource dm355evm_dm9000_rsrc[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct dm9000_plat_data dm335evm_dm9000_platdata;
|
||||
|
||||
static struct platform_device dm355evm_dm9000 = {
|
||||
.name = "dm9000",
|
||||
.id = -1,
|
||||
.resource = dm355evm_dm9000_rsrc,
|
||||
.num_resources = ARRAY_SIZE(dm355evm_dm9000_rsrc),
|
||||
.dev = {
|
||||
.platform_data = &dm335evm_dm9000_platdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct tvp514x_platform_data tvp5146_pdata = {
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/i2c.h>
|
||||
#include <linux/platform_data/pcf857x.h>
|
||||
#include <linux/platform_data/at24.h>
|
||||
#include <linux/platform_data/gpio-davinci.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/rawnand.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
|
@ -596,12 +597,15 @@ static struct i2c_board_info __initdata i2c_info[] = {
|
|||
},
|
||||
};
|
||||
|
||||
#define DM644X_I2C_SDA_PIN GPIO_TO_PIN(2, 12)
|
||||
#define DM644X_I2C_SCL_PIN GPIO_TO_PIN(2, 11)
|
||||
|
||||
static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
|
||||
.dev_id = "i2c_davinci",
|
||||
.dev_id = "i2c_davinci.1",
|
||||
.table = {
|
||||
GPIO_LOOKUP("davinci_gpio", 44, "sda",
|
||||
GPIO_LOOKUP("davinci_gpio.0", DM644X_I2C_SDA_PIN, "sda",
|
||||
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
|
||||
GPIO_LOOKUP("davinci_gpio", 43, "scl",
|
||||
GPIO_LOOKUP("davinci_gpio.0", DM644X_I2C_SCL_PIN, "scl",
|
||||
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
|
||||
},
|
||||
};
|
||||
|
|
|
@ -532,11 +532,12 @@ static struct vpif_display_config dm646x_vpif_display_config = {
|
|||
.set_clock = set_vpif_clock,
|
||||
.subdevinfo = dm646x_vpif_subdev,
|
||||
.subdev_count = ARRAY_SIZE(dm646x_vpif_subdev),
|
||||
.i2c_adapter_id = 1,
|
||||
.chan_config[0] = {
|
||||
.outputs = dm6467_ch0_outputs,
|
||||
.output_count = ARRAY_SIZE(dm6467_ch0_outputs),
|
||||
},
|
||||
.card_name = "DM646x EVM",
|
||||
.card_name = "DM646x EVM Video Display",
|
||||
};
|
||||
|
||||
/**
|
||||
|
@ -674,6 +675,7 @@ static struct vpif_capture_config dm646x_vpif_capture_cfg = {
|
|||
.setup_input_channel_mode = setup_vpif_input_channel_mode,
|
||||
.subdev_info = vpif_capture_sdev_info,
|
||||
.subdev_count = ARRAY_SIZE(vpif_capture_sdev_info),
|
||||
.i2c_adapter_id = 1,
|
||||
.chan_config[0] = {
|
||||
.inputs = dm6467_ch0_inputs,
|
||||
.input_count = ARRAY_SIZE(dm6467_ch0_inputs),
|
||||
|
@ -694,6 +696,7 @@ static struct vpif_capture_config dm646x_vpif_capture_cfg = {
|
|||
.fid_pol = 0,
|
||||
},
|
||||
},
|
||||
.card_name = "DM646x EVM Video Capture",
|
||||
};
|
||||
|
||||
static void __init evm_init_video(void)
|
||||
|
|
|
@ -123,12 +123,16 @@ static const short hawk_mmcsd0_pins[] = {
|
|||
-1
|
||||
};
|
||||
|
||||
#define DA850_HAWK_MMCSD_CD_PIN GPIO_TO_PIN(3, 12)
|
||||
#define DA850_HAWK_MMCSD_WP_PIN GPIO_TO_PIN(3, 13)
|
||||
|
||||
static struct gpiod_lookup_table mmc_gpios_table = {
|
||||
.dev_id = "da830-mmc.0",
|
||||
.table = {
|
||||
/* CD: gpio3_12: gpio60: chip 1 contains gpio range 32-63*/
|
||||
GPIO_LOOKUP("davinci_gpio.0", 28, "cd", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("davinci_gpio.0", 29, "wp", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("davinci_gpio.0", DA850_HAWK_MMCSD_CD_PIN, "cd",
|
||||
GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("davinci_gpio.0", DA850_HAWK_MMCSD_WP_PIN, "wp",
|
||||
GPIO_ACTIVE_LOW),
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
@ -488,7 +488,8 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
|
|||
[IRQ_DM646X_MCASP0TXINT] = 7,
|
||||
[IRQ_DM646X_MCASP0RXINT] = 7,
|
||||
[IRQ_DM646X_RESERVED_3] = 7,
|
||||
[IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
|
||||
[IRQ_DM646X_MCASP1TXINT] = 7,
|
||||
[IRQ_TINT0_TINT12] = 7, /* clockevent */
|
||||
[IRQ_TINT0_TINT34] = 7, /* clocksource */
|
||||
[IRQ_TINT1_TINT12] = 7, /* DSP timer */
|
||||
[IRQ_TINT1_TINT34] = 7, /* system tick */
|
||||
|
|
|
@ -29,6 +29,7 @@ static struct dev_pm_domain keystone_pm_domain = {
|
|||
|
||||
static struct pm_clk_notifier_block platform_domain_notifier = {
|
||||
.pm_domain = &keystone_pm_domain,
|
||||
.con_ids = { NULL },
|
||||
};
|
||||
|
||||
static const struct of_device_id of_keystone_table[] = {
|
||||
|
|
|
@ -58,22 +58,24 @@ static irqreturn_t deferred_fiq(int irq, void *dev_id)
|
|||
irq_num = gpio_to_irq(gpio);
|
||||
fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio];
|
||||
|
||||
while (irq_counter[gpio] < fiq_count) {
|
||||
if (gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
|
||||
struct irq_data *d = irq_get_irq_data(irq_num);
|
||||
if (irq_counter[gpio] < fiq_count &&
|
||||
gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
|
||||
struct irq_data *d = irq_get_irq_data(irq_num);
|
||||
|
||||
/*
|
||||
* It looks like handle_edge_irq() that
|
||||
* OMAP GPIO edge interrupts default to,
|
||||
* expects interrupt already unmasked.
|
||||
*/
|
||||
if (irq_chip && irq_chip->irq_unmask)
|
||||
/*
|
||||
* handle_simple_irq() that OMAP GPIO edge
|
||||
* interrupts default to since commit 80ac93c27441
|
||||
* requires interrupt already acked and unmasked.
|
||||
*/
|
||||
if (irq_chip) {
|
||||
if (irq_chip->irq_ack)
|
||||
irq_chip->irq_ack(d);
|
||||
if (irq_chip->irq_unmask)
|
||||
irq_chip->irq_unmask(d);
|
||||
}
|
||||
generic_handle_irq(irq_num);
|
||||
|
||||
irq_counter[gpio]++;
|
||||
}
|
||||
for (; irq_counter[gpio] < fiq_count; irq_counter[gpio]++)
|
||||
generic_handle_irq(irq_num);
|
||||
}
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
|
|
@ -188,7 +188,7 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
|
|||
((prev & OMAP_POWERSTATE_MASK) << 0));
|
||||
trace_power_domain_target_rcuidle(pwrdm->name,
|
||||
trace_state,
|
||||
smp_processor_id());
|
||||
raw_smp_processor_id());
|
||||
}
|
||||
break;
|
||||
default:
|
||||
|
@ -518,7 +518,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
|
|||
if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
|
||||
/* Trace the pwrdm desired target state */
|
||||
trace_power_domain_target_rcuidle(pwrdm->name, pwrst,
|
||||
smp_processor_id());
|
||||
raw_smp_processor_id());
|
||||
/* Program the pwrdm desired target state */
|
||||
ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst);
|
||||
}
|
||||
|
|
|
@ -1317,7 +1317,7 @@
|
|||
reg = <0x14d60000 0x100>;
|
||||
dmas = <&pdma0 31 &pdma0 30>;
|
||||
dma-names = "tx", "rx";
|
||||
interrupts = <GIC_SPI 435 IRQ_TYPE_NONE>;
|
||||
interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_peric CLK_PCLK_I2S1>,
|
||||
<&cmu_peric CLK_PCLK_I2S1>,
|
||||
<&cmu_peric CLK_SCLK_I2S1>;
|
||||
|
|
|
@ -38,9 +38,10 @@
|
|||
compatible = "marvell,armada-7k-pp22";
|
||||
reg = <0x0 0x100000>, <0x129000 0xb000>;
|
||||
clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
|
||||
<&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 18>;
|
||||
<&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
|
||||
<&CP110_LABEL(clk) 1 18>;
|
||||
clock-names = "pp_clk", "gop_clk",
|
||||
"mg_clk", "axi_clk";
|
||||
"mg_clk", "mg_core_clk", "axi_clk";
|
||||
marvell,system-controller = <&CP110_LABEL(syscon0)>;
|
||||
status = "disabled";
|
||||
dma-coherent;
|
||||
|
@ -141,6 +142,8 @@
|
|||
#size-cells = <0>;
|
||||
compatible = "marvell,xmdio";
|
||||
reg = <0x12a600 0x10>;
|
||||
clocks = <&CP110_LABEL(clk) 1 5>,
|
||||
<&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
@ -46,7 +46,7 @@
|
|||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <TEGRA_MAIN_GPIO(M, 5) IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <TEGRA_MAIN_GPIO(M, 5) IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -414,7 +414,7 @@
|
|||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-pwrseq = <&emmc_pwrseq>;
|
||||
cdns,phy-input-delay-legacy = <4>;
|
||||
cdns,phy-input-delay-legacy = <9>;
|
||||
cdns,phy-input-delay-mmc-highspeed = <2>;
|
||||
cdns,phy-input-delay-mmc-ddr = <3>;
|
||||
cdns,phy-dll-delay-sdclk = <21>;
|
||||
|
|
|
@ -67,3 +67,11 @@
|
|||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_ether_rgmii {
|
||||
tx {
|
||||
pins = "RGMII_TXCLK", "RGMII_TXD0", "RGMII_TXD1",
|
||||
"RGMII_TXD2", "RGMII_TXD3", "RGMII_TXCTL";
|
||||
drive-strength = <9>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -519,7 +519,7 @@
|
|||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-pwrseq = <&emmc_pwrseq>;
|
||||
cdns,phy-input-delay-legacy = <4>;
|
||||
cdns,phy-input-delay-legacy = <9>;
|
||||
cdns,phy-input-delay-mmc-highspeed = <2>;
|
||||
cdns,phy-input-delay-mmc-ddr = <3>;
|
||||
cdns,phy-dll-delay-sdclk = <21>;
|
||||
|
|
|
@ -334,7 +334,7 @@
|
|||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-pwrseq = <&emmc_pwrseq>;
|
||||
cdns,phy-input-delay-legacy = <4>;
|
||||
cdns,phy-input-delay-legacy = <9>;
|
||||
cdns,phy-input-delay-mmc-highspeed = <2>;
|
||||
cdns,phy-input-delay-mmc-ddr = <3>;
|
||||
cdns,phy-dll-delay-sdclk = <21>;
|
||||
|
|
|
@ -778,6 +778,7 @@ scmi_create_protocol_device(struct device_node *np, struct scmi_info *info,
|
|||
if (scmi_mbox_chan_setup(info, &sdev->dev, prot_id)) {
|
||||
dev_err(&sdev->dev, "failed to setup transport\n");
|
||||
scmi_device_destroy(sdev);
|
||||
return;
|
||||
}
|
||||
|
||||
/* setup handle now as the transport is ready */
|
||||
|
|
|
@ -110,7 +110,7 @@ static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
|
|||
UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
|
||||
UNIPHIER_RESETX(6, 0x200c, 6), /* Ether */
|
||||
UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC (HSC) */
|
||||
UNIPHIER_RESETX(12, 0x200c, 5), /* GIO (PCIe, USB3) */
|
||||
UNIPHIER_RESETX(14, 0x200c, 5), /* USB30 */
|
||||
UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
|
||||
UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */
|
||||
UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */
|
||||
|
@ -127,8 +127,8 @@ static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = {
|
|||
UNIPHIER_RESETX(6, 0x200c, 9), /* Ether0 */
|
||||
UNIPHIER_RESETX(7, 0x200c, 10), /* Ether1 */
|
||||
UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */
|
||||
UNIPHIER_RESETX(12, 0x200c, 4), /* USB30 link (GIO0) */
|
||||
UNIPHIER_RESETX(13, 0x200c, 5), /* USB31 link (GIO1) */
|
||||
UNIPHIER_RESETX(12, 0x200c, 4), /* USB30 link */
|
||||
UNIPHIER_RESETX(13, 0x200c, 5), /* USB31 link */
|
||||
UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY0 */
|
||||
UNIPHIER_RESETX(17, 0x200c, 18), /* USB30-PHY1 */
|
||||
UNIPHIER_RESETX(18, 0x200c, 20), /* USB30-PHY2 */
|
||||
|
|
|
@ -238,6 +238,17 @@ static int params_from_user(struct tee_context *ctx, struct tee_param *params,
|
|||
if (IS_ERR(shm))
|
||||
return PTR_ERR(shm);
|
||||
|
||||
/*
|
||||
* Ensure offset + size does not overflow offset
|
||||
* and does not overflow the size of the referred
|
||||
* shared memory object.
|
||||
*/
|
||||
if ((ip.a + ip.b) < ip.a ||
|
||||
(ip.a + ip.b) > shm->size) {
|
||||
tee_shm_put(shm);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
params[n].u.memref.shm_offs = ip.a;
|
||||
params[n].u.memref.size = ip.b;
|
||||
params[n].u.memref.shm = shm;
|
||||
|
|
|
@ -360,9 +360,10 @@ int tee_shm_get_fd(struct tee_shm *shm)
|
|||
if (!(shm->flags & TEE_SHM_DMA_BUF))
|
||||
return -EINVAL;
|
||||
|
||||
get_dma_buf(shm->dmabuf);
|
||||
fd = dma_buf_fd(shm->dmabuf, O_CLOEXEC);
|
||||
if (fd >= 0)
|
||||
get_dma_buf(shm->dmabuf);
|
||||
if (fd < 0)
|
||||
dma_buf_put(shm->dmabuf);
|
||||
return fd;
|
||||
}
|
||||
|
||||
|
|
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