perf list: Document precise event sampling for AMD IBS
Updating man perf-list. Signed-off-by: Robert Richter <robert.richter@amd.com> Cc: Ingo Molnar <mingo@kernel.org> Link: http://lkml.kernel.org/r/1344361396-7237-7-git-send-email-robert.richter@amd.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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@ -20,20 +20,38 @@ EVENT MODIFIERS
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---------------
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Events can optionally have a modifer by appending a colon and one or
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more modifiers. Modifiers allow the user to restrict when events are
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counted with 'u' for user-space, 'k' for kernel, 'h' for hypervisor.
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Additional modifiers are 'G' for guest counting (in KVM guests) and 'H'
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for host counting (not in KVM guests).
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more modifiers. Modifiers allow the user to restrict the events to be
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counted. The following modifiers exist:
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u - user-space counting
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k - kernel counting
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h - hypervisor counting
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G - guest counting (in KVM guests)
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H - host counting (not in KVM guests)
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p - precise level
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The 'p' modifier can be used for specifying how precise the instruction
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address should be. The 'p' modifier is currently only implemented for
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Intel PEBS and can be specified multiple times:
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0 - SAMPLE_IP can have arbitrary skid
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1 - SAMPLE_IP must have constant skid
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2 - SAMPLE_IP requested to have 0 skid
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3 - SAMPLE_IP must have 0 skid
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address should be. The 'p' modifier can be specified multiple times:
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The PEBS implementation now supports up to 2.
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0 - SAMPLE_IP can have arbitrary skid
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1 - SAMPLE_IP must have constant skid
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2 - SAMPLE_IP requested to have 0 skid
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3 - SAMPLE_IP must have 0 skid
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For Intel systems precise event sampling is implemented with PEBS
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which supports up to precise-level 2.
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On AMD systems it is implemented using IBS (up to precise-level 2).
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The precise modifier works with event types 0x76 (cpu-cycles, CPU
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clocks not halted) and 0xC1 (micro-ops retired). Both events map to
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IBS execution sampling (IBS op) with the IBS Op Counter Control bit
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(IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
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Manual Volume 2: System Programming, 13.3 Instruction-Based
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Sampling). Examples to use IBS:
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perf record -a -e cpu-cycles:p ... # use ibs op counting cycles
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perf record -a -e r076:p ... # same as -e cpu-cycles:p
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perf record -a -e r0C1:p ... # use ibs op counting micro-ops
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RAW HARDWARE EVENT DESCRIPTOR
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-----------------------------
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@ -97,4 +115,4 @@ SEE ALSO
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linkperf:perf-stat[1], linkperf:perf-top[1],
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linkperf:perf-record[1],
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http://www.intel.com/Assets/PDF/manual/253669.pdf[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
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http://support.amd.com/us/Processor_TechDocs/24593.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]
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http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]
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