Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Thomas Gleixner: - a bugfix which prevents a divide by 0 panic when the newly introduced try_msr_calibrate_tsc() fails - enablement of the Baytrail platform to utilize the newfangled msr based calibration * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86: tsc: Add missing Baytrail frequency to the table x86, tsc: Fallback to normal calibration if fast MSR calibration fails
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Коммит
208937fdcf
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@ -66,6 +66,6 @@ extern void tsc_save_sched_clock_state(void);
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extern void tsc_restore_sched_clock_state(void);
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/* MSR based TSC calibration for Intel Atom SoC platforms */
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int try_msr_calibrate_tsc(unsigned long *fast_calibrate);
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unsigned long try_msr_calibrate_tsc(void);
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#endif /* _ASM_X86_TSC_H */
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@ -653,13 +653,10 @@ unsigned long native_calibrate_tsc(void)
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/* Calibrate TSC using MSR for Intel Atom SoCs */
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local_irq_save(flags);
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i = try_msr_calibrate_tsc(&fast_calibrate);
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fast_calibrate = try_msr_calibrate_tsc();
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local_irq_restore(flags);
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if (i >= 0) {
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if (i == 0)
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pr_warn("Fast TSC calibration using MSR failed\n");
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if (fast_calibrate)
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return fast_calibrate;
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}
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local_irq_save(flags);
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fast_calibrate = quick_pit_calibrate();
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@ -53,7 +53,7 @@ static struct freq_desc freq_desc_tables[] = {
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/* TNG */
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{ 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
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/* VLV2 */
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{ 6, 0x37, 1, { 0, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
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{ 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
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/* ANN */
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{ 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
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};
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@ -77,21 +77,18 @@ static int match_cpu(u8 family, u8 model)
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/*
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* Do MSR calibration only for known/supported CPUs.
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* Return values:
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* -1: CPU is unknown/unsupported for MSR based calibration
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* 0: CPU is known/supported, but calibration failed
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* 1: CPU is known/supported, and calibration succeeded
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*
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* Returns the calibration value or 0 if MSR calibration failed.
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*/
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int try_msr_calibrate_tsc(unsigned long *fast_calibrate)
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unsigned long try_msr_calibrate_tsc(void)
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{
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int cpu_index;
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u32 lo, hi, ratio, freq_id, freq;
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unsigned long res;
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int cpu_index;
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cpu_index = match_cpu(boot_cpu_data.x86, boot_cpu_data.x86_model);
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if (cpu_index < 0)
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return -1;
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*fast_calibrate = 0;
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return 0;
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if (freq_desc_tables[cpu_index].msr_plat) {
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rdmsr(MSR_PLATFORM_INFO, lo, hi);
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@ -103,7 +100,7 @@ int try_msr_calibrate_tsc(unsigned long *fast_calibrate)
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pr_info("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
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if (!ratio)
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return 0;
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goto fail;
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/* Get FSB FREQ ID */
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rdmsr(MSR_FSB_FREQ, lo, hi);
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@ -112,16 +109,19 @@ int try_msr_calibrate_tsc(unsigned long *fast_calibrate)
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pr_info("Resolved frequency ID: %u, frequency: %u KHz\n",
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freq_id, freq);
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if (!freq)
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return 0;
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goto fail;
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/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
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*fast_calibrate = freq * ratio;
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pr_info("TSC runs at %lu KHz\n", *fast_calibrate);
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res = freq * ratio;
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pr_info("TSC runs at %lu KHz\n", res);
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#ifdef CONFIG_X86_LOCAL_APIC
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lapic_timer_frequency = (freq * 1000) / HZ;
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pr_info("lapic_timer_frequency = %d\n", lapic_timer_frequency);
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#endif
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return res;
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return 1;
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fail:
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pr_warn("Fast TSC calibration using MSR failed\n");
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return 0;
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}
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