[PATCH] libata: Marvell SATA support (PIO mode)
This is my libata compatible low level driver for the Marvell SATA family. Currently it successfully runs in PIO mode on a 6081 chip. EDMA support is in the works and should be done shortly. Review, testing (especially on other flavors of Marvell), comments welcome. Signed-off-by: Brett Russ <russb@emc.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This commit is contained in:
Brett Russ
Jeff Garzik
Родитель
7da7931283
Коммит
20f733e7d7
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@ -459,6 +459,15 @@ config SCSI_ATA_PIIX
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If unsure, say N.
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config SCSI_SATA_MV
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tristate "Marvell SATA support"
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depends on SCSI_SATA && PCI && EXPERIMENTAL
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help
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This option enables support for the Marvell Serial ATA family.
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Currently supports 88SX[56]0[48][01] chips.
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If unsure, say N.
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config SCSI_SATA_NV
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tristate "NVIDIA SATA support"
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depends on SCSI_SATA && PCI && EXPERIMENTAL
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@ -132,6 +132,7 @@ obj-$(CONFIG_SCSI_SATA_SIS) += libata.o sata_sis.o
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obj-$(CONFIG_SCSI_SATA_SX4) += libata.o sata_sx4.o
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obj-$(CONFIG_SCSI_SATA_NV) += libata.o sata_nv.o
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obj-$(CONFIG_SCSI_SATA_ULI) += libata.o sata_uli.o
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obj-$(CONFIG_SCSI_SATA_MV) += libata.o sata_mv.o
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obj-$(CONFIG_ARM) += arm/
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@ -0,0 +1,827 @@
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/*
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* sata_mv.c - Marvell SATA support
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*
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* Copyright 2005: EMC Corporation, all rights reserved.
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*
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* Please ALWAYS copy linux-ide@vger.kernel.org on emails.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/dma-mapping.h>
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#include "scsi.h"
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include <asm/io.h>
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#define DRV_NAME "sata_mv"
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#define DRV_VERSION "0.12"
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enum {
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/* BAR's are enumerated in terms of pci_resource_start() terms */
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MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
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MV_IO_BAR = 2, /* offset 0x18: IO space */
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MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
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MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
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MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
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MV_PCI_REG_BASE = 0,
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MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
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MV_SATAHC0_REG_BASE = 0x20000,
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MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
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MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
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MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
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MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
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MV_Q_CT = 32,
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MV_CRQB_SZ = 32,
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MV_CRPB_SZ = 8,
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MV_DMA_BOUNDARY = 0xffffffffU,
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SATAHC_MASK = (~(MV_SATAHC_REG_SZ - 1)),
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MV_PORTS_PER_HC = 4,
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/* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
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MV_PORT_HC_SHIFT = 2,
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/* == (port % MV_PORTS_PER_HC) to determine port from 0-7 port */
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MV_PORT_MASK = 3,
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/* Host Flags */
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MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
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MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
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MV_FLAG_BDMA = (1 << 28), /* Basic DMA */
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chip_504x = 0,
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chip_508x = 1,
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chip_604x = 2,
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chip_608x = 3,
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/* PCI interface registers */
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PCI_MAIN_CMD_STS_OFS = 0xd30,
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STOP_PCI_MASTER = (1 << 2),
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PCI_MASTER_EMPTY = (1 << 3),
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GLOB_SFT_RST = (1 << 4),
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PCI_IRQ_CAUSE_OFS = 0x1d58,
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PCI_IRQ_MASK_OFS = 0x1d5c,
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PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
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HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
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HC_MAIN_IRQ_MASK_OFS = 0x1d64,
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PORT0_ERR = (1 << 0), /* shift by port # */
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PORT0_DONE = (1 << 1), /* shift by port # */
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HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
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HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
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PCI_ERR = (1 << 18),
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TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
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TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
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PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
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GPIO_INT = (1 << 22),
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SELF_INT = (1 << 23),
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TWSI_INT = (1 << 24),
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HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
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HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
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PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
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HC_MAIN_RSVD),
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/* SATAHC registers */
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HC_CFG_OFS = 0,
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HC_IRQ_CAUSE_OFS = 0x14,
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CRBP_DMA_DONE = (1 << 0), /* shift by port # */
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HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
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DEV_IRQ = (1 << 8), /* shift by port # */
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/* Shadow block registers */
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SHD_PIO_DATA_OFS = 0x100,
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SHD_FEA_ERR_OFS = 0x104,
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SHD_SECT_CNT_OFS = 0x108,
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SHD_LBA_L_OFS = 0x10C,
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SHD_LBA_M_OFS = 0x110,
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SHD_LBA_H_OFS = 0x114,
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SHD_DEV_HD_OFS = 0x118,
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SHD_CMD_STA_OFS = 0x11C,
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SHD_CTL_AST_OFS = 0x120,
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/* SATA registers */
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SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
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SATA_ACTIVE_OFS = 0x350,
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/* Port registers */
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EDMA_CFG_OFS = 0,
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EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
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EDMA_ERR_IRQ_MASK_OFS = 0xc,
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EDMA_ERR_D_PAR = (1 << 0),
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EDMA_ERR_PRD_PAR = (1 << 1),
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EDMA_ERR_DEV = (1 << 2),
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EDMA_ERR_DEV_DCON = (1 << 3),
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EDMA_ERR_DEV_CON = (1 << 4),
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EDMA_ERR_SERR = (1 << 5),
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EDMA_ERR_SELF_DIS = (1 << 7),
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EDMA_ERR_BIST_ASYNC = (1 << 8),
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EDMA_ERR_CRBQ_PAR = (1 << 9),
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EDMA_ERR_CRPB_PAR = (1 << 10),
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EDMA_ERR_INTRL_PAR = (1 << 11),
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EDMA_ERR_IORDY = (1 << 12),
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EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
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EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
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EDMA_ERR_LNK_DATA_RX = (0xf << 17),
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EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
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EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
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EDMA_ERR_TRANS_PROTO = (1 << 31),
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EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
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EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
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EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
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EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
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EDMA_ERR_LNK_DATA_RX |
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EDMA_ERR_LNK_DATA_TX |
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EDMA_ERR_TRANS_PROTO),
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EDMA_CMD_OFS = 0x28,
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EDMA_EN = (1 << 0),
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EDMA_DS = (1 << 1),
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ATA_RST = (1 << 2),
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/* BDMA is 6xxx part only */
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BDMA_CMD_OFS = 0x224,
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BDMA_START = (1 << 0),
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MV_UNDEF = 0,
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};
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struct mv_port_priv {
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};
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struct mv_host_priv {
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};
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static void mv_irq_clear(struct ata_port *ap);
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static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
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static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
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static void mv_phy_reset(struct ata_port *ap);
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static int mv_master_reset(void __iomem *mmio_base);
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static irqreturn_t mv_interrupt(int irq, void *dev_instance,
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struct pt_regs *regs);
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static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
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static Scsi_Host_Template mv_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.eh_strategy_handler = ata_scsi_error,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = MV_UNDEF,
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.max_sectors = ATA_MAX_SECTORS,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = MV_UNDEF,
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.proc_name = DRV_NAME,
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.dma_boundary = MV_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.bios_param = ata_std_bios_param,
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.ordered_flush = 1,
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};
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static struct ata_port_operations mv_ops = {
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.port_disable = ata_port_disable,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.phy_reset = mv_phy_reset,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.eng_timeout = ata_eng_timeout,
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.irq_handler = mv_interrupt,
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.irq_clear = mv_irq_clear,
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.scr_read = mv_scr_read,
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.scr_write = mv_scr_write,
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.port_start = ata_port_start,
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.port_stop = ata_port_stop,
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.host_stop = ata_host_stop,
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};
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static struct ata_port_info mv_port_info[] = {
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{ /* chip_504x */
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.sht = &mv_sht,
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.host_flags = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO),
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.pio_mask = 0x1f, /* pio4-0 */
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.udma_mask = 0, /* 0x7f (udma6-0 disabled for now) */
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.port_ops = &mv_ops,
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},
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{ /* chip_508x */
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.sht = &mv_sht,
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.host_flags = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
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MV_FLAG_DUAL_HC),
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.pio_mask = 0x1f, /* pio4-0 */
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.udma_mask = 0, /* 0x7f (udma6-0 disabled for now) */
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.port_ops = &mv_ops,
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},
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{ /* chip_604x */
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.sht = &mv_sht,
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.host_flags = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
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MV_FLAG_IRQ_COALESCE | MV_FLAG_BDMA),
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.pio_mask = 0x1f, /* pio4-0 */
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.udma_mask = 0, /* 0x7f (udma6-0 disabled for now) */
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.port_ops = &mv_ops,
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},
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{ /* chip_608x */
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.sht = &mv_sht,
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.host_flags = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
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MV_FLAG_IRQ_COALESCE | MV_FLAG_DUAL_HC |
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MV_FLAG_BDMA),
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.pio_mask = 0x1f, /* pio4-0 */
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.udma_mask = 0, /* 0x7f (udma6-0 disabled for now) */
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.port_ops = &mv_ops,
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},
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};
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static struct pci_device_id mv_pci_tbl[] = {
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{PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
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{PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
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{PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_508x},
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{PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
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{PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
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{PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x},
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{PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x},
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{PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x},
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{} /* terminate list */
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};
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static struct pci_driver mv_pci_driver = {
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.name = DRV_NAME,
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.id_table = mv_pci_tbl,
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.probe = mv_init_one,
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.remove = ata_pci_remove_one,
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};
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/*
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* Functions
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*/
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static inline void writelfl(unsigned long data, void __iomem *addr)
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{
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writel(data, addr);
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(void) readl(addr); /* flush to avoid PCI posted write */
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}
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static inline void __iomem *mv_port_addr_to_hc_base(void __iomem *port_mmio)
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{
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return ((void __iomem *)((unsigned long)port_mmio &
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(unsigned long)SATAHC_MASK));
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}
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static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
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{
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return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
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}
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static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
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{
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return (mv_hc_base(base, port >> MV_PORT_HC_SHIFT) +
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MV_SATAHC_ARBTR_REG_SZ +
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((port & MV_PORT_MASK) * MV_PORT_REG_SZ));
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}
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static inline void __iomem *mv_ap_base(struct ata_port *ap)
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{
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return mv_port_base(ap->host_set->mmio_base, ap->port_no);
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}
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static inline int mv_get_hc_count(unsigned long flags)
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{
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return ((flags & MV_FLAG_DUAL_HC) ? 2 : 1);
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}
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static inline int mv_is_edma_active(struct ata_port *ap)
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{
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void __iomem *port_mmio = mv_ap_base(ap);
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return (EDMA_EN & readl(port_mmio + EDMA_CMD_OFS));
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}
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static inline int mv_port_bdma_capable(struct ata_port *ap)
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{
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return (ap->flags & MV_FLAG_BDMA);
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}
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static void mv_irq_clear(struct ata_port *ap)
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{
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}
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static unsigned int mv_scr_offset(unsigned int sc_reg_in)
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{
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unsigned int ofs;
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switch (sc_reg_in) {
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case SCR_STATUS:
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case SCR_CONTROL:
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case SCR_ERROR:
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ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
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break;
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case SCR_ACTIVE:
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ofs = SATA_ACTIVE_OFS; /* active is not with the others */
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break;
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default:
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ofs = 0xffffffffU;
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break;
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}
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return ofs;
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}
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static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
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{
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unsigned int ofs = mv_scr_offset(sc_reg_in);
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if (0xffffffffU != ofs) {
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return readl(mv_ap_base(ap) + ofs);
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} else {
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return (u32) ofs;
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}
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}
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||||
|
||||
static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
|
||||
{
|
||||
unsigned int ofs = mv_scr_offset(sc_reg_in);
|
||||
|
||||
if (0xffffffffU != ofs) {
|
||||
writelfl(val, mv_ap_base(ap) + ofs);
|
||||
}
|
||||
}
|
||||
|
||||
static int mv_master_reset(void __iomem *mmio_base)
|
||||
{
|
||||
void __iomem *reg = mmio_base + PCI_MAIN_CMD_STS_OFS;
|
||||
int i, rc = 0;
|
||||
u32 t;
|
||||
|
||||
VPRINTK("ENTER\n");
|
||||
|
||||
/* Following procedure defined in PCI "main command and status
|
||||
* register" table.
|
||||
*/
|
||||
t = readl(reg);
|
||||
writel(t | STOP_PCI_MASTER, reg);
|
||||
|
||||
for (i = 0; i < 100; i++) {
|
||||
msleep(10);
|
||||
t = readl(reg);
|
||||
if (PCI_MASTER_EMPTY & t) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!(PCI_MASTER_EMPTY & t)) {
|
||||
printk(KERN_ERR DRV_NAME "PCI master won't flush\n");
|
||||
rc = 1; /* broken HW? */
|
||||
goto done;
|
||||
}
|
||||
|
||||
/* set reset */
|
||||
i = 5;
|
||||
do {
|
||||
writel(t | GLOB_SFT_RST, reg);
|
||||
t = readl(reg);
|
||||
udelay(1);
|
||||
} while (!(GLOB_SFT_RST & t) && (i-- > 0));
|
||||
|
||||
if (!(GLOB_SFT_RST & t)) {
|
||||
printk(KERN_ERR DRV_NAME "can't set global reset\n");
|
||||
rc = 1; /* broken HW? */
|
||||
goto done;
|
||||
}
|
||||
|
||||
/* clear reset */
|
||||
i = 5;
|
||||
do {
|
||||
writel(t & ~GLOB_SFT_RST, reg);
|
||||
t = readl(reg);
|
||||
udelay(1);
|
||||
} while ((GLOB_SFT_RST & t) && (i-- > 0));
|
||||
|
||||
if (GLOB_SFT_RST & t) {
|
||||
printk(KERN_ERR DRV_NAME "can't clear global reset\n");
|
||||
rc = 1; /* broken HW? */
|
||||
}
|
||||
|
||||
done:
|
||||
VPRINTK("EXIT, rc = %i\n", rc);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void mv_err_intr(struct ata_port *ap)
|
||||
{
|
||||
void __iomem *port_mmio;
|
||||
u32 edma_err_cause, serr = 0;
|
||||
|
||||
/* bug here b/c we got an err int on a port we don't know about,
|
||||
* so there's no way to clear it
|
||||
*/
|
||||
BUG_ON(NULL == ap);
|
||||
port_mmio = mv_ap_base(ap);
|
||||
|
||||
edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
|
||||
|
||||
if (EDMA_ERR_SERR & edma_err_cause) {
|
||||
serr = scr_read(ap, SCR_ERROR);
|
||||
scr_write_flush(ap, SCR_ERROR, serr);
|
||||
}
|
||||
DPRINTK("port %u error; EDMA err cause: 0x%08x SERR: 0x%08x\n",
|
||||
ap->port_no, edma_err_cause, serr);
|
||||
|
||||
/* Clear EDMA now that SERR cleanup done */
|
||||
writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
|
||||
|
||||
/* check for fatal here and recover if needed */
|
||||
if (EDMA_ERR_FATAL & edma_err_cause) {
|
||||
mv_phy_reset(ap);
|
||||
}
|
||||
}
|
||||
|
||||
/* Handle any outstanding interrupts in a single SATAHC
|
||||
*/
|
||||
static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
|
||||
unsigned int hc)
|
||||
{
|
||||
void __iomem *mmio = host_set->mmio_base;
|
||||
void __iomem *hc_mmio = mv_hc_base(mmio, hc);
|
||||
struct ata_port *ap;
|
||||
struct ata_queued_cmd *qc;
|
||||
u32 hc_irq_cause;
|
||||
int shift, port, port0, hard_port;
|
||||
u8 ata_status;
|
||||
|
||||
if (hc == 0) {
|
||||
port0 = 0;
|
||||
} else {
|
||||
port0 = MV_PORTS_PER_HC;
|
||||
}
|
||||
|
||||
/* we'll need the HC success int register in most cases */
|
||||
hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
|
||||
if (hc_irq_cause) {
|
||||
writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
|
||||
}
|
||||
|
||||
VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
|
||||
hc,relevant,hc_irq_cause);
|
||||
|
||||
for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
|
||||
ap = host_set->ports[port];
|
||||
hard_port = port & MV_PORT_MASK; /* range 0-3 */
|
||||
ata_status = 0xffU;
|
||||
|
||||
if (((CRBP_DMA_DONE | DEV_IRQ) << hard_port) & hc_irq_cause) {
|
||||
BUG_ON(NULL == ap);
|
||||
/* rcv'd new resp, basic DMA complete, or ATA IRQ */
|
||||
/* This is needed to clear the ATA INTRQ.
|
||||
* FIXME: don't read the status reg in EDMA mode!
|
||||
*/
|
||||
ata_status = readb((void __iomem *)
|
||||
ap->ioaddr.status_addr);
|
||||
}
|
||||
|
||||
shift = port * 2;
|
||||
if (port >= MV_PORTS_PER_HC) {
|
||||
shift++; /* skip bit 8 in the HC Main IRQ reg */
|
||||
}
|
||||
if ((PORT0_ERR << shift) & relevant) {
|
||||
mv_err_intr(ap);
|
||||
/* FIXME: smart to OR in ATA_ERR? */
|
||||
ata_status = readb((void __iomem *)
|
||||
ap->ioaddr.status_addr) | ATA_ERR;
|
||||
}
|
||||
|
||||
if (ap) {
|
||||
qc = ata_qc_from_tag(ap, ap->active_tag);
|
||||
if (NULL != qc) {
|
||||
VPRINTK("port %u IRQ found for qc, "
|
||||
"ata_status 0x%x\n", port,ata_status);
|
||||
BUG_ON(0xffU == ata_status);
|
||||
/* mark qc status appropriately */
|
||||
ata_qc_complete(qc, ata_status);
|
||||
}
|
||||
}
|
||||
}
|
||||
VPRINTK("EXIT\n");
|
||||
}
|
||||
|
||||
static irqreturn_t mv_interrupt(int irq, void *dev_instance,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
struct ata_host_set *host_set = dev_instance;
|
||||
unsigned int hc, handled = 0, n_hcs;
|
||||
void __iomem *mmio;
|
||||
u32 irq_stat;
|
||||
|
||||
mmio = host_set->mmio_base;
|
||||
irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
|
||||
n_hcs = mv_get_hc_count(host_set->ports[0]->flags);
|
||||
|
||||
/* check the cases where we either have nothing pending or have read
|
||||
* a bogus register value which can indicate HW removal or PCI fault
|
||||
*/
|
||||
if (!irq_stat || (0xffffffffU == irq_stat)) {
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
spin_lock(&host_set->lock);
|
||||
|
||||
for (hc = 0; hc < n_hcs; hc++) {
|
||||
u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
|
||||
if (relevant) {
|
||||
mv_host_intr(host_set, relevant, hc);
|
||||
handled = 1;
|
||||
}
|
||||
}
|
||||
if (PCI_ERR & irq_stat) {
|
||||
/* FIXME: these are all masked by default, but still need
|
||||
* to recover from them properly.
|
||||
*/
|
||||
}
|
||||
|
||||
spin_unlock(&host_set->lock);
|
||||
|
||||
return IRQ_RETVAL(handled);
|
||||
}
|
||||
|
||||
static void mv_phy_reset(struct ata_port *ap)
|
||||
{
|
||||
void __iomem *port_mmio = mv_ap_base(ap);
|
||||
struct ata_taskfile tf;
|
||||
struct ata_device *dev = &ap->device[0];
|
||||
u32 edma = 0, bdma;
|
||||
|
||||
VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
|
||||
|
||||
edma = readl(port_mmio + EDMA_CMD_OFS);
|
||||
if (EDMA_EN & edma) {
|
||||
/* disable EDMA if active */
|
||||
edma &= ~EDMA_EN;
|
||||
writelfl(edma | EDMA_DS, port_mmio + EDMA_CMD_OFS);
|
||||
udelay(1);
|
||||
} else if (mv_port_bdma_capable(ap) &&
|
||||
(bdma = readl(port_mmio + BDMA_CMD_OFS)) & BDMA_START) {
|
||||
/* disable BDMA if active */
|
||||
writelfl(bdma & ~BDMA_START, port_mmio + BDMA_CMD_OFS);
|
||||
}
|
||||
|
||||
writelfl(edma | ATA_RST, port_mmio + EDMA_CMD_OFS);
|
||||
udelay(25); /* allow reset propagation */
|
||||
|
||||
/* Spec never mentions clearing the bit. Marvell's driver does
|
||||
* clear the bit, however.
|
||||
*/
|
||||
writelfl(edma & ~ATA_RST, port_mmio + EDMA_CMD_OFS);
|
||||
|
||||
VPRINTK("Done. Now calling __sata_phy_reset()\n");
|
||||
|
||||
/* proceed to init communications via the scr_control reg */
|
||||
__sata_phy_reset(ap);
|
||||
|
||||
if (ap->flags & ATA_FLAG_PORT_DISABLED) {
|
||||
VPRINTK("Port disabled pre-sig. Exiting.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
|
||||
tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
|
||||
tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
|
||||
tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr);
|
||||
|
||||
dev->class = ata_dev_classify(&tf);
|
||||
if (!ata_dev_present(dev)) {
|
||||
VPRINTK("Port disabled post-sig: No device present.\n");
|
||||
ata_port_disable(ap);
|
||||
}
|
||||
VPRINTK("EXIT\n");
|
||||
}
|
||||
|
||||
static void mv_port_init(struct ata_ioports *port, unsigned long base)
|
||||
{
|
||||
/* PIO related setup */
|
||||
port->data_addr = base + SHD_PIO_DATA_OFS;
|
||||
port->error_addr = port->feature_addr = base + SHD_FEA_ERR_OFS;
|
||||
port->nsect_addr = base + SHD_SECT_CNT_OFS;
|
||||
port->lbal_addr = base + SHD_LBA_L_OFS;
|
||||
port->lbam_addr = base + SHD_LBA_M_OFS;
|
||||
port->lbah_addr = base + SHD_LBA_H_OFS;
|
||||
port->device_addr = base + SHD_DEV_HD_OFS;
|
||||
port->status_addr = port->command_addr = base + SHD_CMD_STA_OFS;
|
||||
port->altstatus_addr = port->ctl_addr = base + SHD_CTL_AST_OFS;
|
||||
/* unused */
|
||||
port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
|
||||
|
||||
/* unmask all EDMA error interrupts */
|
||||
writel(~0, (void __iomem *)base + EDMA_ERR_IRQ_MASK_OFS);
|
||||
|
||||
VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
|
||||
readl((void __iomem *)base + EDMA_CFG_OFS),
|
||||
readl((void __iomem *)base + EDMA_ERR_IRQ_CAUSE_OFS),
|
||||
readl((void __iomem *)base + EDMA_ERR_IRQ_MASK_OFS));
|
||||
}
|
||||
|
||||
static int mv_host_init(struct ata_probe_ent *probe_ent)
|
||||
{
|
||||
int rc = 0, n_hc, port, hc;
|
||||
void __iomem *mmio = probe_ent->mmio_base;
|
||||
void __iomem *port_mmio;
|
||||
|
||||
if (mv_master_reset(probe_ent->mmio_base)) {
|
||||
rc = 1;
|
||||
goto done;
|
||||
}
|
||||
|
||||
n_hc = mv_get_hc_count(probe_ent->host_flags);
|
||||
probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
|
||||
|
||||
for (port = 0; port < probe_ent->n_ports; port++) {
|
||||
port_mmio = mv_port_base(mmio, port);
|
||||
mv_port_init(&probe_ent->port[port], (unsigned long)port_mmio);
|
||||
}
|
||||
|
||||
for (hc = 0; hc < n_hc; hc++) {
|
||||
VPRINTK("HC%i: HC config=0x%08x HC IRQ cause=0x%08x\n", hc,
|
||||
readl(mv_hc_base(mmio, hc) + HC_CFG_OFS),
|
||||
readl(mv_hc_base(mmio, hc) + HC_IRQ_CAUSE_OFS));
|
||||
}
|
||||
|
||||
writel(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
|
||||
writel(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
|
||||
|
||||
VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
|
||||
"PCI int cause/mask=0x%08x/0x%08x\n",
|
||||
readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
|
||||
readl(mmio + HC_MAIN_IRQ_MASK_OFS),
|
||||
readl(mmio + PCI_IRQ_CAUSE_OFS),
|
||||
readl(mmio + PCI_IRQ_MASK_OFS));
|
||||
|
||||
done:
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
static int printed_version = 0;
|
||||
struct ata_probe_ent *probe_ent = NULL;
|
||||
struct mv_host_priv *hpriv;
|
||||
unsigned int board_idx = (unsigned int)ent->driver_data;
|
||||
void __iomem *mmio_base;
|
||||
int pci_dev_busy = 0;
|
||||
int rc;
|
||||
|
||||
if (!printed_version++) {
|
||||
printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
|
||||
}
|
||||
|
||||
VPRINTK("ENTER for PCI Bus:Slot.Func=%u:%u.%u\n", pdev->bus->number,
|
||||
PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
|
||||
|
||||
rc = pci_enable_device(pdev);
|
||||
if (rc) {
|
||||
return rc;
|
||||
}
|
||||
|
||||
rc = pci_request_regions(pdev, DRV_NAME);
|
||||
if (rc) {
|
||||
pci_dev_busy = 1;
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
pci_intx(pdev, 1);
|
||||
|
||||
probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
|
||||
if (probe_ent == NULL) {
|
||||
rc = -ENOMEM;
|
||||
goto err_out_regions;
|
||||
}
|
||||
|
||||
memset(probe_ent, 0, sizeof(*probe_ent));
|
||||
probe_ent->dev = pci_dev_to_dev(pdev);
|
||||
INIT_LIST_HEAD(&probe_ent->node);
|
||||
|
||||
mmio_base = ioremap_nocache(pci_resource_start(pdev, MV_PRIMARY_BAR),
|
||||
pci_resource_len(pdev, MV_PRIMARY_BAR));
|
||||
if (mmio_base == NULL) {
|
||||
rc = -ENOMEM;
|
||||
goto err_out_free_ent;
|
||||
}
|
||||
|
||||
hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
|
||||
if (!hpriv) {
|
||||
rc = -ENOMEM;
|
||||
goto err_out_iounmap;
|
||||
}
|
||||
memset(hpriv, 0, sizeof(*hpriv));
|
||||
|
||||
probe_ent->sht = mv_port_info[board_idx].sht;
|
||||
probe_ent->host_flags = mv_port_info[board_idx].host_flags;
|
||||
probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
|
||||
probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
|
||||
probe_ent->port_ops = mv_port_info[board_idx].port_ops;
|
||||
|
||||
probe_ent->irq = pdev->irq;
|
||||
probe_ent->irq_flags = SA_SHIRQ;
|
||||
probe_ent->mmio_base = mmio_base;
|
||||
probe_ent->private_data = hpriv;
|
||||
|
||||
/* initialize adapter */
|
||||
rc = mv_host_init(probe_ent);
|
||||
if (rc) {
|
||||
goto err_out_hpriv;
|
||||
}
|
||||
/* mv_print_info(probe_ent); */
|
||||
|
||||
{
|
||||
int b, w;
|
||||
u32 dw[4]; /* hold a line of 16b */
|
||||
VPRINTK("PCI config space:\n");
|
||||
for (b = 0; b < 0x40; ) {
|
||||
for (w = 0; w < 4; w++) {
|
||||
(void) pci_read_config_dword(pdev,b,&dw[w]);
|
||||
b += sizeof(*dw);
|
||||
}
|
||||
VPRINTK("%08x %08x %08x %08x\n",
|
||||
dw[0],dw[1],dw[2],dw[3]);
|
||||
}
|
||||
}
|
||||
|
||||
/* FIXME: check ata_device_add return value */
|
||||
ata_device_add(probe_ent);
|
||||
kfree(probe_ent);
|
||||
|
||||
return 0;
|
||||
|
||||
err_out_hpriv:
|
||||
kfree(hpriv);
|
||||
err_out_iounmap:
|
||||
iounmap(mmio_base);
|
||||
err_out_free_ent:
|
||||
kfree(probe_ent);
|
||||
err_out_regions:
|
||||
pci_release_regions(pdev);
|
||||
err_out:
|
||||
if (!pci_dev_busy) {
|
||||
pci_disable_device(pdev);
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int __init mv_init(void)
|
||||
{
|
||||
return pci_module_init(&mv_pci_driver);
|
||||
}
|
||||
|
||||
static void __exit mv_exit(void)
|
||||
{
|
||||
pci_unregister_driver(&mv_pci_driver);
|
||||
}
|
||||
|
||||
MODULE_AUTHOR("Brett Russ");
|
||||
MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
|
||||
MODULE_VERSION(DRV_VERSION);
|
||||
|
||||
module_init(mv_init);
|
||||
module_exit(mv_exit);
|
||||
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