irqchip/gic-v3: Add ESPI range support
Add the required support for the ESPI range, which behave exactly like the SPIs of old, only with new funky INTIDs. Signed-off-by: Marc Zyngier <maz@kernel.org>
This commit is contained in:
Marc Zyngier
Родитель
8662465348
Коммит
211bddd210
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@ -51,13 +51,16 @@ struct gic_chip_data {
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u32 nr_redist_regions;
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u64 flags;
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bool has_rss;
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unsigned int irq_nr;
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struct partition_desc *ppi_descs[16];
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};
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static struct gic_chip_data gic_data __read_mostly;
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static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
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#define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
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#define GIC_LINE_NR max(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U)
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#define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer)
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/*
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* The behaviours of RPR and PMR registers differ depending on the value of
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* SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
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@ -100,6 +103,7 @@ static DEFINE_PER_CPU(bool, has_rss);
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enum gic_intid_range {
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PPI_RANGE,
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SPI_RANGE,
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ESPI_RANGE,
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LPI_RANGE,
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__INVALID_RANGE__
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};
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@ -111,6 +115,8 @@ static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq)
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return PPI_RANGE;
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case 32 ... 1019:
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return SPI_RANGE;
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case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023):
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return ESPI_RANGE;
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case 8192 ... GENMASK(23, 0):
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return LPI_RANGE;
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default:
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@ -141,6 +147,7 @@ static inline void __iomem *gic_dist_base(struct irq_data *d)
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return gic_data_rdist_sgi_base();
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case SPI_RANGE:
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case ESPI_RANGE:
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/* SPI -> dist_base */
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return gic_data.dist_base;
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@ -234,6 +241,31 @@ static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index)
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case SPI_RANGE:
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*index = d->hwirq;
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return offset;
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case ESPI_RANGE:
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*index = d->hwirq - ESPI_BASE_INTID;
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switch (offset) {
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case GICD_ISENABLER:
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return GICD_ISENABLERnE;
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case GICD_ICENABLER:
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return GICD_ICENABLERnE;
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case GICD_ISPENDR:
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return GICD_ISPENDRnE;
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case GICD_ICPENDR:
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return GICD_ICPENDRnE;
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case GICD_ISACTIVER:
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return GICD_ISACTIVERnE;
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case GICD_ICACTIVER:
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return GICD_ICACTIVERnE;
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case GICD_IPRIORITYR:
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return GICD_IPRIORITYRnE;
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case GICD_ICFGR:
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return GICD_ICFGRnE;
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case GICD_IROUTER:
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return GICD_IROUTERnE;
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default:
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break;
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}
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break;
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default:
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break;
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}
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@ -316,7 +348,7 @@ static int gic_irq_set_irqchip_state(struct irq_data *d,
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{
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u32 reg;
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if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
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if (d->hwirq >= 8192) /* PPI/SPI only */
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return -EINVAL;
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switch (which) {
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@ -343,7 +375,7 @@ static int gic_irq_set_irqchip_state(struct irq_data *d,
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static int gic_irq_get_irqchip_state(struct irq_data *d,
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enum irqchip_irq_state which, bool *val)
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{
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if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
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if (d->hwirq >= 8192) /* PPI/SPI only */
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return -EINVAL;
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switch (which) {
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@ -567,7 +599,12 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs
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gic_arch_enable_irqs();
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}
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if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) {
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/* Check for special IDs first */
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if ((irqnr >= 1020 && irqnr <= 1023))
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return;
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/* Treat anything but SGIs in a uniform way */
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if (likely(irqnr > 15)) {
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int err;
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if (static_branch_likely(&supports_deactivate_key))
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@ -655,10 +692,26 @@ static void __init gic_dist_init(void)
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* do the right thing if the kernel is running in secure mode,
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* but that's not the intended use case anyway.
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*/
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for (i = 32; i < gic_data.irq_nr; i += 32)
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for (i = 32; i < GIC_LINE_NR; i += 32)
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writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
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gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
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/* Extended SPI range, not handled by the GICv2/GICv3 common code */
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for (i = 0; i < GIC_ESPI_NR; i += 32) {
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writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8);
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writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8);
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}
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for (i = 0; i < GIC_ESPI_NR; i += 32)
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writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8);
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for (i = 0; i < GIC_ESPI_NR; i += 16)
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writel_relaxed(0, base + GICD_ICFGRnE + i / 4);
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for (i = 0; i < GIC_ESPI_NR; i += 4)
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writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i);
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/* Now do the common stuff, and wait for the distributor to drain */
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gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp);
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/* Enable distributor with ARE, Group1 */
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writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
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@ -669,8 +722,11 @@ static void __init gic_dist_init(void)
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* enabled.
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*/
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affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
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for (i = 32; i < gic_data.irq_nr; i++)
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for (i = 32; i < GIC_LINE_NR; i++)
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gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
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for (i = 0; i < GIC_ESPI_NR; i++)
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gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8);
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}
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static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *))
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@ -1134,8 +1190,6 @@ static struct irq_chip gic_eoimode1_chip = {
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IRQCHIP_MASK_ON_SUSPEND,
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};
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#define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
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static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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@ -1153,6 +1207,7 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
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break;
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case SPI_RANGE:
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case ESPI_RANGE:
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irq_domain_set_info(d, irq, hw, chip, d->host_data,
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handle_fasteoi_irq, NULL, NULL);
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irq_set_probe(irq);
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@ -1192,6 +1247,9 @@ static int gic_irq_domain_translate(struct irq_domain *d,
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case GIC_IRQ_TYPE_PARTITION:
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*hwirq = fwspec->param[1] + 16;
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break;
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case 2: /* ESPI */
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*hwirq = fwspec->param[1] + ESPI_BASE_INTID;
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break;
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case GIC_IRQ_TYPE_LPI: /* LPI */
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*hwirq = fwspec->param[1];
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break;
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@ -1346,7 +1404,6 @@ static int __init gic_init_bases(void __iomem *dist_base,
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struct fwnode_handle *handle)
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{
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u32 typer;
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int gic_irqs;
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int err;
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if (!is_hyp_mode_available())
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@ -1363,15 +1420,11 @@ static int __init gic_init_bases(void __iomem *dist_base,
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/*
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* Find out how many interrupts are supported.
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* The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
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*/
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typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
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gic_data.rdists.gicd_typer = typer;
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gic_irqs = GICD_TYPER_IRQS(typer);
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if (gic_irqs > 1020)
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gic_irqs = 1020;
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gic_data.irq_nr = gic_irqs;
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pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);
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pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR);
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gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
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&gic_data);
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irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED);
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@ -30,10 +30,22 @@
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#define GICD_ICFGR 0x0C00
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#define GICD_IGRPMODR 0x0D00
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#define GICD_NSACR 0x0E00
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#define GICD_IGROUPRnE 0x1000
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#define GICD_ISENABLERnE 0x1200
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#define GICD_ICENABLERnE 0x1400
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#define GICD_ISPENDRnE 0x1600
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#define GICD_ICPENDRnE 0x1800
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#define GICD_ISACTIVERnE 0x1A00
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#define GICD_ICACTIVERnE 0x1C00
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#define GICD_IPRIORITYRnE 0x2000
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#define GICD_ICFGRnE 0x3000
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#define GICD_IROUTER 0x6000
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#define GICD_IROUTERnE 0x8000
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#define GICD_IDREGS 0xFFD0
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#define GICD_PIDR2 0xFFE8
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#define ESPI_BASE_INTID 4096
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/*
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* Those registers are actually from GICv2, but the spec demands that they
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* are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3).
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@ -69,10 +81,13 @@
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#define GICD_TYPER_RSS (1U << 26)
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#define GICD_TYPER_LPIS (1U << 17)
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#define GICD_TYPER_MBIS (1U << 16)
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#define GICD_TYPER_ESPI (1U << 8)
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#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
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#define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1)
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#define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32)
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#define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32)
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#define GICD_TYPER_ESPIS(typer) \
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(((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0)
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#define GICD_IROUTER_SPI_MODE_ONE (0U << 31)
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#define GICD_IROUTER_SPI_MODE_ANY (1U << 31)
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