cirrusfb: add Laguna additional overflow register
Add additional overflow register setting for Laguna chips. Also, simplify some code in the cirrusfb_pan_display() and cirrusfb_blank(). Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Krzysztof Helt
Linus Torvalds
Родитель
55a4ea6ab0
Коммит
213d4bdd8c
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@ -1259,13 +1259,32 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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/* screen start addr #16-18, fastpagemode cycles */
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vga_wcrt(regbase, CL_CRT1B, tmp);
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if (cinfo->btype == BT_SD64 ||
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cinfo->btype == BT_PICASSO4 ||
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cinfo->btype == BT_ALPINE ||
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cinfo->btype == BT_GD5480)
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/* screen start address bit 19 */
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/* screen start address bit 19 */
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if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
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vga_wcrt(regbase, CL_CRT1D, 0x00);
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if (cinfo->btype == BT_LAGUNA ||
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cinfo->btype == BT_GD5480) {
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tmp = 0;
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if ((htotal + 5) & 256)
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tmp |= 128;
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if (hdispend & 256)
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tmp |= 64;
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if (hsyncstart & 256)
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tmp |= 48;
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if (vtotal & 1024)
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tmp |= 8;
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if (vdispend & 1024)
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tmp |= 4;
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if (vsyncstart & 1024)
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tmp |= 3;
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vga_wcrt(regbase, CL_CRT1E, tmp);
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dev_dbg(info->device, "CRT1e: %d\n", tmp);
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}
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/* text cursor location high */
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vga_wcrt(regbase, VGA_CRTC_CURSOR_HI, 0);
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/* text cursor location low */
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@ -1383,7 +1402,7 @@ static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
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int xoffset = 0;
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int yoffset = 0;
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unsigned long base;
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unsigned char tmp = 0, tmp2 = 0, xpix;
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unsigned char tmp, xpix;
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struct cirrusfb_info *cinfo = info->par;
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dev_dbg(info->device,
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@ -1418,6 +1437,8 @@ static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
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vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI,
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(unsigned char) (base >> 8));
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/* 0xf2 is %11110010, exclude tmp bits */
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tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2;
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/* construct bits 16, 17 and 18 of screen start address */
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if (base & 0x10000)
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tmp |= 0x01;
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@ -1426,9 +1447,7 @@ static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
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if (base & 0x40000)
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tmp |= 0x08;
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/* 0xf2 is %11110010, exclude tmp bits */
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tmp2 = (vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2) | tmp;
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vga_wcrt(cinfo->regbase, CL_CRT1B, tmp2);
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vga_wcrt(cinfo->regbase, CL_CRT1B, tmp);
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/* construct bit 19 of screen start address */
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if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
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@ -1473,47 +1492,44 @@ static int cirrusfb_blank(int blank_mode, struct fb_info *info)
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/* Undo current */
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if (current_mode == FB_BLANK_NORMAL ||
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current_mode == FB_BLANK_UNBLANK) {
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/* unblank the screen */
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val = vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE);
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current_mode == FB_BLANK_UNBLANK)
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/* clear "FullBandwidth" bit */
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vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val & 0xdf);
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/* and undo VESA suspend trickery */
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vga_wgfx(cinfo->regbase, CL_GRE, 0x00);
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}
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/* set new */
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if (blank_mode > FB_BLANK_NORMAL) {
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/* blank the screen */
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val = vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE);
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val = 0;
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else
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/* set "FullBandwidth" bit */
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vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val | 0x20);
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}
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val = 0x20;
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val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf;
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vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val);
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switch (blank_mode) {
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case FB_BLANK_UNBLANK:
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case FB_BLANK_NORMAL:
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val = 0x00;
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break;
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case FB_BLANK_VSYNC_SUSPEND:
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vga_wgfx(cinfo->regbase, CL_GRE, 0x04);
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val = 0x04;
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break;
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case FB_BLANK_HSYNC_SUSPEND:
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vga_wgfx(cinfo->regbase, CL_GRE, 0x02);
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val = 0x02;
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break;
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case FB_BLANK_POWERDOWN:
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vga_wgfx(cinfo->regbase, CL_GRE, 0x06);
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val = 0x06;
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break;
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default:
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dev_dbg(info->device, "EXIT, returning 1\n");
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return 1;
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}
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vga_wgfx(cinfo->regbase, CL_GRE, val);
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cinfo->blank_mode = blank_mode;
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dev_dbg(info->device, "EXIT, returning 0\n");
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/* Let fbcon do a soft blank for us */
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return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
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}
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/**** END Hardware specific Routines **************************************/
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/****************************************************************************/
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/**** BEGIN Internal Routines ***********************************************/
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@ -71,6 +71,7 @@
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#define CL_CRT1B 0x1b /* Extended Display Controls */
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#define CL_CRT1C 0x1c /* Sync adjust and genlock register */
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#define CL_CRT1D 0x1d /* Overlay Extended Control register */
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#define CL_CRT1E 0x1e /* Another overflow register */
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#define CL_CRT25 0x25 /* Part Status Register */
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#define CL_CRT27 0x27 /* ID Register */
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#define CL_CRT51 0x51 /* P4 disable "flicker fixer" */
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