dl2k: ANAR, ANLPAR fixes
same story, different registers... Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Al Viro
Jeff Garzik
Родитель
d50956af74
Коммит
21b645e4c2
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@ -1453,7 +1453,7 @@ mii_wait_link (struct net_device *dev, int wait)
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static int
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mii_get_media (struct net_device *dev)
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{
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ANAR_t negotiate;
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__u16 negotiate;
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BMSR_t bmsr;
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MSCR_t mscr;
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MSSR_t mssr;
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@ -1469,7 +1469,7 @@ mii_get_media (struct net_device *dev)
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/* Auto-Negotiation not completed */
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return -1;
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}
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negotiate.image = mii_read (dev, phy_addr, MII_ANAR) &
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negotiate = mii_read (dev, phy_addr, MII_ANAR) &
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mii_read (dev, phy_addr, MII_ANLPAR);
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mscr.image = mii_read (dev, phy_addr, MII_MSCR);
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mssr.image = mii_read (dev, phy_addr, MII_MSSR);
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@ -1481,27 +1481,27 @@ mii_get_media (struct net_device *dev)
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np->speed = 1000;
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np->full_duplex = 0;
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printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
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} else if (negotiate.bits.media_100BX_FD) {
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} else if (negotiate & MII_ANAR_100BX_FD) {
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np->speed = 100;
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np->full_duplex = 1;
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printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
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} else if (negotiate.bits.media_100BX_HD) {
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} else if (negotiate & MII_ANAR_100BX_HD) {
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np->speed = 100;
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np->full_duplex = 0;
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printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
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} else if (negotiate.bits.media_10BT_FD) {
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} else if (negotiate & MII_ANAR_10BT_FD) {
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np->speed = 10;
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np->full_duplex = 1;
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printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
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} else if (negotiate.bits.media_10BT_HD) {
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} else if (negotiate & MII_ANAR_10BT_HD) {
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np->speed = 10;
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np->full_duplex = 0;
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printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
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}
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if (negotiate.bits.pause) {
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if (negotiate & MII_ANAR_PAUSE) {
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np->tx_flow &= 1;
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np->rx_flow &= 1;
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} else if (negotiate.bits.asymmetric) {
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} else if (negotiate & MII_ANAR_ASYMMETRIC) {
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np->tx_flow = 0;
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np->rx_flow &= 1;
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}
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@ -1542,7 +1542,7 @@ mii_set_media (struct net_device *dev)
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PHY_SCR_t pscr;
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__u16 bmcr;
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BMSR_t bmsr;
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ANAR_t anar;
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__u16 anar;
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int phy_addr;
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struct netdev_private *np;
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np = netdev_priv(dev);
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@ -1552,15 +1552,24 @@ mii_set_media (struct net_device *dev)
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if (np->an_enable) {
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/* Advertise capabilities */
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bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
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anar.image = mii_read (dev, phy_addr, MII_ANAR);
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anar.bits.media_100BX_FD = bmsr.bits.media_100BX_FD;
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anar.bits.media_100BX_HD = bmsr.bits.media_100BX_HD;
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anar.bits.media_100BT4 = bmsr.bits.media_100BT4;
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anar.bits.media_10BT_FD = bmsr.bits.media_10BT_FD;
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anar.bits.media_10BT_HD = bmsr.bits.media_10BT_HD;
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anar.bits.pause = 1;
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anar.bits.asymmetric = 1;
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mii_write (dev, phy_addr, MII_ANAR, anar.image);
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anar = mii_read (dev, phy_addr, MII_ANAR) &
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~MII_ANAR_100BX_FD &
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~MII_ANAR_100BX_HD &
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~MII_ANAR_100BT4 &
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~MII_ANAR_10BT_FD &
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~MII_ANAR_10BT_HD;
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if (bmsr.bits.media_100BX_FD)
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anar |= MII_ANAR_100BX_FD;
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if (bmsr.bits.media_100BX_HD)
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anar |= MII_ANAR_100BX_HD;
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if (bmsr.bits.media_100BT4)
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anar |= MII_ANAR_100BT4;
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if (bmsr.bits.media_10BT_FD)
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anar |= MII_ANAR_10BT_FD;
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if (bmsr.bits.media_10BT_HD)
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anar |= MII_ANAR_10BT_HD;
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anar |= MII_ANAR_PAUSE | MII_ANAR_ASYMMETRIC;
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mii_write (dev, phy_addr, MII_ANAR, anar);
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/* Enable Auto crossover */
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pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
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@ -1621,7 +1630,7 @@ mii_set_media (struct net_device *dev)
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static int
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mii_get_media_pcs (struct net_device *dev)
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{
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ANAR_PCS_t negotiate;
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__u16 negotiate;
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BMSR_t bmsr;
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int phy_addr;
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struct netdev_private *np;
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@ -1635,20 +1644,20 @@ mii_get_media_pcs (struct net_device *dev)
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/* Auto-Negotiation not completed */
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return -1;
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}
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negotiate.image = mii_read (dev, phy_addr, PCS_ANAR) &
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negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
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mii_read (dev, phy_addr, PCS_ANLPAR);
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np->speed = 1000;
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if (negotiate.bits.full_duplex) {
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if (negotiate & PCS_ANAR_FULL_DUPLEX) {
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printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
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np->full_duplex = 1;
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} else {
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printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
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np->full_duplex = 0;
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}
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if (negotiate.bits.pause) {
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if (negotiate & PCS_ANAR_PAUSE) {
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np->tx_flow &= 1;
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np->rx_flow &= 1;
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} else if (negotiate.bits.asymmetric) {
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} else if (negotiate & PCS_ANAR_ASYMMETRIC) {
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np->tx_flow = 0;
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np->rx_flow &= 1;
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}
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@ -1679,7 +1688,7 @@ mii_set_media_pcs (struct net_device *dev)
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{
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__u16 bmcr;
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ESR_t esr;
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ANAR_PCS_t anar;
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__u16 anar;
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int phy_addr;
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struct netdev_private *np;
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np = netdev_priv(dev);
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@ -1689,14 +1698,15 @@ mii_set_media_pcs (struct net_device *dev)
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if (np->an_enable) {
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/* Advertise capabilities */
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esr.image = mii_read (dev, phy_addr, PCS_ESR);
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anar.image = mii_read (dev, phy_addr, MII_ANAR);
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anar.bits.half_duplex =
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esr.bits.media_1000BT_HD | esr.bits.media_1000BX_HD;
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anar.bits.full_duplex =
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esr.bits.media_1000BT_FD | esr.bits.media_1000BX_FD;
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anar.bits.pause = 1;
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anar.bits.asymmetric = 1;
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mii_write (dev, phy_addr, MII_ANAR, anar.image);
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anar = mii_read (dev, phy_addr, MII_ANAR) &
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~PCS_ANAR_HALF_DUPLEX &
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~PCS_ANAR_FULL_DUPLEX;
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if (esr.bits.media_1000BT_HD | esr.bits.media_1000BX_HD)
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anar |= PCS_ANAR_HALF_DUPLEX;
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if (esr.bits.media_1000BT_FD | esr.bits.media_1000BX_FD)
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anar |= PCS_ANAR_FULL_DUPLEX;
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anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
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mii_write (dev, phy_addr, MII_ANAR, anar);
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/* Soft reset PHY */
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mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
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@ -357,24 +357,6 @@ enum _mii_bmsr {
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};
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/* ANAR */
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typedef union t_MII_ANAR {
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u16 image;
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struct {
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u16 selector:5; // bit 4:0
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u16 media_10BT_HD:1; // bit 5
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u16 media_10BT_FD:1; // bit 6
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u16 media_100BX_HD:1; // bit 7
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u16 media_100BX_FD:1; // bit 8
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u16 media_100BT4:1; // bit 9
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u16 pause:1; // bit 10
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u16 asymmetric:1; // bit 11
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u16 _bit12:1; // bit 12
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u16 remote_fault:1; // bit 13
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u16 _bit14:1; // bit 14
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u16 next_page:1; // bit 15
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} bits;
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} ANAR_t, *PANAR_t;
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enum _mii_anar {
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MII_ANAR_NEXT_PAGE = 0x8000,
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MII_ANAR_REMOTE_FAULT = 0x4000,
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@ -390,24 +372,6 @@ enum _mii_anar {
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};
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/* ANLPAR */
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typedef union t_MII_ANLPAR {
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u16 image;
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struct {
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u16 selector:5; // bit 4:0
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u16 media_10BT_HD:1; // bit 5
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u16 media_10BT_FD:1; // bit 6
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u16 media_100BX_HD:1; // bit 7
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u16 media_100BX_FD:1; // bit 8
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u16 media_100BT4:1; // bit 9
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u16 pause:1; // bit 10
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u16 asymmetric:1; // bit 11
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u16 _bit12:1; // bit 12
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u16 remote_fault:1; // bit 13
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u16 _bit14:1; // bit 14
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u16 next_page:1; // bit 15
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} bits;
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} ANLPAR_t, *PANLPAR_t;
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enum _mii_anlpar {
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MII_ANLPAR_NEXT_PAGE = MII_ANAR_NEXT_PAGE,
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MII_ANLPAR_REMOTE_FAULT = MII_ANAR_REMOTE_FAULT,
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@ -539,21 +503,6 @@ typedef enum t_MII_ADMIN_STATUS {
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/* PCS control and status registers bitmap as the same as MII */
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/* PCS Extended Status register bitmap as the same as MII */
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/* PCS ANAR */
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typedef union t_PCS_ANAR {
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u16 image;
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struct {
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u16 _bit_4_0:5; // bit 4:0
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u16 full_duplex:1; // bit 5
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u16 half_duplex:1; // bit 6
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u16 asymmetric:1; // bit 7
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u16 pause:1; // bit 8
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u16 _bit_11_9:3; // bit 11:9
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u16 remote_fault:2; // bit 13:12
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u16 _bit_14:1; // bit 14
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u16 next_page:1; // bit 15
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} bits;
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} ANAR_PCS_t, *PANAR_PCS_t;
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enum _pcs_anar {
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PCS_ANAR_NEXT_PAGE = 0x8000,
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PCS_ANAR_REMOTE_FAULT = 0x3000,
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@ -563,21 +512,6 @@ enum _pcs_anar {
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PCS_ANAR_FULL_DUPLEX = 0x0020,
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};
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/* PCS ANLPAR */
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typedef union t_PCS_ANLPAR {
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u16 image;
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struct {
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u16 _bit_4_0:5; // bit 4:0
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u16 full_duplex:1; // bit 5
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u16 half_duplex:1; // bit 6
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u16 asymmetric:1; // bit 7
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u16 pause:1; // bit 8
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u16 _bit_11_9:3; // bit 11:9
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u16 remote_fault:2; // bit 13:12
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u16 _bit_14:1; // bit 14
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u16 next_page:1; // bit 15
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} bits;
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} ANLPAR_PCS_t, *PANLPAR_PCS_t;
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enum _pcs_anlpar {
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PCS_ANLPAR_NEXT_PAGE = PCS_ANAR_NEXT_PAGE,
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PCS_ANLPAR_REMOTE_FAULT = PCS_ANAR_REMOTE_FAULT,
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