Merge master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6: (34 commits) PCI: Only build PCI syscalls on architectures that want them PCI: limit pci_get_bus_and_slot to domain 0 PCI: hotplug: acpiphp: avoid acpiphp "cannot get bridge info" PCI hotplug failure PCI: hotplug: acpiphp: remove hot plug parameter write to PCI host bridge PCI: hotplug: acpiphp: fix slot poweroff problem on systems without _PS3 PCI: hotplug: pciehp: wait for 1 second after power off slot PCI: pci_set_power_state(): check for PM capabilities earlier PCI: cpci_hotplug: Convert to use the kthread API PCI: add pci_try_set_mwi PCI: pcie: remove SPIN_LOCK_UNLOCKED PCI: ROUND_UP macro cleanup in drivers/pci PCI: remove pci_dac_dma_... APIs PCI: pci-x-pci-express-read-control-interfaces cleanups PCI: Fix typo in include/linux/pci.h PCI: pci_ids, remove double or more empty lines PCI: pci_ids, add atheros and 3com_2 vendors PCI: pci_ids, reorder some entries PCI: i386: traps, change VENDOR to DEVICE PCI: ATM: lanai, change VENDOR to DEVICE PCI: Change all drivers to use pci_device->revision ...
This commit is contained in:
Коммит
21ba0f88ae
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@ -664,109 +664,6 @@ It is that simple.
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Well, not for some odd devices. See the next section for information
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about that.
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DAC Addressing for Address Space Hungry Devices
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There exists a class of devices which do not mesh well with the PCI
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DMA mapping API. By definition these "mappings" are a finite
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resource. The number of total available mappings per bus is platform
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specific, but there will always be a reasonable amount.
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What is "reasonable"? Reasonable means that networking and block I/O
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devices need not worry about using too many mappings.
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As an example of a problematic device, consider compute cluster cards.
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They can potentially need to access gigabytes of memory at once via
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DMA. Dynamic mappings are unsuitable for this kind of access pattern.
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To this end we've provided a small API by which a device driver
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may use DAC cycles to directly address all of physical memory.
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Not all platforms support this, but most do. It is easy to determine
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whether the platform will work properly at probe time.
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First, understand that there may be a SEVERE performance penalty for
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using these interfaces on some platforms. Therefore, you MUST only
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use these interfaces if it is absolutely required. %99 of devices can
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use the normal APIs without any problems.
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Note that for streaming type mappings you must either use these
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interfaces, or the dynamic mapping interfaces above. You may not mix
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usage of both for the same device. Such an act is illegal and is
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guaranteed to put a banana in your tailpipe.
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However, consistent mappings may in fact be used in conjunction with
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these interfaces. Remember that, as defined, consistent mappings are
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always going to be SAC addressable.
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The first thing your driver needs to do is query the PCI platform
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layer if it is capable of handling your devices DAC addressing
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capabilities:
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int pci_dac_dma_supported(struct pci_dev *hwdev, u64 mask);
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You may not use the following interfaces if this routine fails.
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Next, DMA addresses using this API are kept track of using the
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dma64_addr_t type. It is guaranteed to be big enough to hold any
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DAC address the platform layer will give to you from the following
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routines. If you have consistent mappings as well, you still
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use plain dma_addr_t to keep track of those.
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All mappings obtained here will be direct. The mappings are not
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translated, and this is the purpose of this dialect of the DMA API.
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All routines work with page/offset pairs. This is the _ONLY_ way to
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portably refer to any piece of memory. If you have a cpu pointer
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(which may be validly DMA'd too) you may easily obtain the page
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and offset using something like this:
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struct page *page = virt_to_page(ptr);
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unsigned long offset = offset_in_page(ptr);
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Here are the interfaces:
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dma64_addr_t pci_dac_page_to_dma(struct pci_dev *pdev,
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struct page *page,
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unsigned long offset,
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int direction);
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The DAC address for the tuple PAGE/OFFSET are returned. The direction
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argument is the same as for pci_{map,unmap}_single(). The same rules
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for cpu/device access apply here as for the streaming mapping
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interfaces. To reiterate:
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The cpu may touch the buffer before pci_dac_page_to_dma.
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The device may touch the buffer after pci_dac_page_to_dma
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is made, but the cpu may NOT.
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When the DMA transfer is complete, invoke:
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void pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev,
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dma64_addr_t dma_addr,
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size_t len, int direction);
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This must be done before the CPU looks at the buffer again.
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This interface behaves identically to pci_dma_sync_{single,sg}_for_cpu().
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And likewise, if you wish to let the device get back at the buffer after
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the cpu has read/written it, invoke:
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void pci_dac_dma_sync_single_for_device(struct pci_dev *pdev,
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dma64_addr_t dma_addr,
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size_t len, int direction);
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before letting the device access the DMA area again.
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If you need to get back to the PAGE/OFFSET tuple from a dma64_addr_t
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the following interfaces are provided:
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struct page *pci_dac_dma_to_page(struct pci_dev *pdev,
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dma64_addr_t dma_addr);
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unsigned long pci_dac_dma_to_offset(struct pci_dev *pdev,
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dma64_addr_t dma_addr);
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This is possible with the DAC interfaces purely because they are
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not translated in any way.
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Optimizing Unmap State Space Consumption
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On many platforms, pci_unmap_{single,page}() is simply a nop.
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@ -113,9 +113,6 @@ initialization with a pointer to a structure describing the driver
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(Please see Documentation/power/pci.txt for descriptions
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of PCI Power Management and the related functions.)
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enable_wake Enable device to generate wake events from a low power
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state.
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shutdown Hook into reboot_notifier_list (kernel/sys.c).
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Intended to stop any idling DMA operations.
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Useful for enabling wake-on-lan (NIC) or changing
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@ -299,7 +296,10 @@ If the PCI device can use the PCI Memory-Write-Invalidate transaction,
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call pci_set_mwi(). This enables the PCI_COMMAND bit for Mem-Wr-Inval
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and also ensures that the cache line size register is set correctly.
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Check the return value of pci_set_mwi() as not all architectures
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or chip-sets may support Memory-Write-Invalidate.
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or chip-sets may support Memory-Write-Invalidate. Alternatively,
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if Mem-Wr-Inval would be nice to have but is not required, call
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pci_try_set_mwi() to have the system do its best effort at enabling
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Mem-Wr-Inval.
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3.2 Request MMIO/IOP resources
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@ -164,7 +164,6 @@ struct pci_driver:
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int (*suspend) (struct pci_dev *dev, pm_message_t state);
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int (*resume) (struct pci_dev *dev);
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int (*enable_wake) (struct pci_dev *dev, pci_power_t state, int enable);
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suspend
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@ -251,42 +250,6 @@ The driver should update the current_state field in its pci_dev structure in
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this function, except for PM-capable devices when pci_set_power_state is used.
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enable_wake
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-----------
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Usage:
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if (dev->driver && dev->driver->enable_wake)
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dev->driver->enable_wake(dev,state,enable);
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This callback is generally only relevant for devices that support the PCI PM
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spec and have the ability to generate a PME# (Power Management Event Signal)
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to wake the system up. (However, it is possible that a device may support
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some non-standard way of generating a wake event on sleep.)
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Bits 15:11 of the PMC (Power Mgmt Capabilities) Register in a device's
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PM Capabilities describe what power states the device supports generating a
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wake event from:
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+------------------+
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| Bit | State |
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+------------------+
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| 11 | D0 |
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| 12 | D1 |
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| 13 | D2 |
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| 14 | D3hot |
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| 15 | D3cold |
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+------------------+
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A device can use this to enable wake events:
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pci_enable_wake(dev,state,enable);
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Note that to enable PME# from D3cold, a value of 4 should be passed to
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pci_enable_wake (since it uses an index into a bitmask). If a driver gets
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a request to enable wake events from D3, two calls should be made to
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pci_enable_wake (one for both D3hot and D3cold).
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A reference implementation
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-------------------------
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@ -2814,11 +2814,6 @@ P: Kristen Carlson Accardi
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M: kristen.c.accardi@intel.com
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S: Supported
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PCI HOTPLUG COMPAQ DRIVER
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P: Greg Kroah-Hartman
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M: greg@kroah.com
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S: Maintained
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PCIE HOTPLUG DRIVER
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P: Kristen Carlson Accardi
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M: kristen.c.accardi@intel.com
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@ -327,6 +327,9 @@ config PCI_DOMAINS
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bool
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default y
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config PCI_SYSCALL
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def_bool PCI
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config ALPHA_CORE_AGP
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bool
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depends on ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL
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@ -207,6 +207,10 @@ iommu_arena_free(struct pci_iommu_arena *arena, long ofs, long n)
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p[i] = 0;
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}
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/* True if the machine supports DAC addressing, and DEV can
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make use of it given MASK. */
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static int pci_dac_dma_supported(struct pci_dev *hwdev, u64 mask);
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/* Map a single buffer of the indicated size for PCI DMA in streaming
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mode. The 32-bit PCI bus mastering address to use is returned.
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Once the device is given the dma address, the device owns this memory
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@ -897,7 +901,7 @@ iommu_unbind(struct pci_iommu_arena *arena, long pg_start, long pg_count)
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/* True if the machine supports DAC addressing, and DEV can
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make use of it given MASK. */
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int
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static int
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pci_dac_dma_supported(struct pci_dev *dev, u64 mask)
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{
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dma64_addr_t dac_offset = alpha_mv.pci_dac_offset;
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@ -917,32 +921,6 @@ pci_dac_dma_supported(struct pci_dev *dev, u64 mask)
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return ok;
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}
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EXPORT_SYMBOL(pci_dac_dma_supported);
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dma64_addr_t
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pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page,
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unsigned long offset, int direction)
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{
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return (alpha_mv.pci_dac_offset
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+ __pa(page_address(page))
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+ (dma64_addr_t) offset);
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}
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EXPORT_SYMBOL(pci_dac_page_to_dma);
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struct page *
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pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr)
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{
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unsigned long paddr = (dma_addr & PAGE_MASK) - alpha_mv.pci_dac_offset;
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return virt_to_page(__va(paddr));
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}
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EXPORT_SYMBOL(pci_dac_dma_to_page);
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unsigned long
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pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr)
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{
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return (dma_addr & ~PAGE_MASK);
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}
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EXPORT_SYMBOL(pci_dac_dma_to_offset);
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/* Helper for generic DMA-mapping functions. */
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@ -531,6 +531,9 @@ config PCI
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information about which PCI hardware does work under Linux and which
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doesn't.
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config PCI_SYSCALL
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def_bool PCI
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# Select the host bridge type
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config PCI_HOST_VIA82C505
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bool
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@ -391,8 +391,6 @@ static struct cpufreq_driver nforce2_driver = {
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*/
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static unsigned int nforce2_detect_chipset(void)
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{
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u8 revision;
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nforce2_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
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PCI_DEVICE_ID_NVIDIA_NFORCE2,
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PCI_ANY_ID, PCI_ANY_ID, NULL);
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@ -400,10 +398,8 @@ static unsigned int nforce2_detect_chipset(void)
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if (nforce2_chipset_dev == NULL)
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return -ENODEV;
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pci_read_config_byte(nforce2_chipset_dev, PCI_REVISION_ID, &revision);
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printk(KERN_INFO "cpufreq: Detected nForce2 chipset revision %X\n",
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revision);
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nforce2_chipset_dev->revision);
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printk(KERN_INFO
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"cpufreq: FSB changing is maybe unstable and can lead to crashes and data loss.\n");
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|
|
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@ -115,7 +115,6 @@ struct gxfreq_params {
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u8 pci_suscfg;
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u8 pci_pmer1;
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u8 pci_pmer2;
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u8 pci_rev;
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struct pci_dev *cs55x0;
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};
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|
@ -276,7 +275,7 @@ static void gx_set_cpuspeed(unsigned int khz)
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pci_write_config_byte(gx_params->cs55x0, PCI_VIDTC, 100);/* typical 50 to 100ms */
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pci_write_config_byte(gx_params->cs55x0, PCI_PMER1, pmer1);
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if (gx_params->pci_rev < 0x10) { /* CS5530(rev 1.2, 1.3) */
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if (gx_params->cs55x0->revision < 0x10) { /* CS5530(rev 1.2, 1.3) */
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suscfg = gx_params->pci_suscfg | SUSMOD;
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} else { /* CS5530A,B.. */
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suscfg = gx_params->pci_suscfg | SUSMOD | PWRSVE;
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|
@ -471,7 +470,6 @@ static int __init cpufreq_gx_init(void)
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pci_read_config_byte(params->cs55x0, PCI_PMER2, &(params->pci_pmer2));
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pci_read_config_byte(params->cs55x0, PCI_MODON, &(params->on_duration));
|
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pci_read_config_byte(params->cs55x0, PCI_MODOFF, &(params->off_duration));
|
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pci_read_config_byte(params->cs55x0, PCI_REVISION_ID, ¶ms->pci_rev);
|
||||
|
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if ((ret = cpufreq_register_driver(&gx_suspmod_driver))) {
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kfree(params);
|
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|
|
|
@ -205,7 +205,6 @@ static unsigned int speedstep_detect_chipset (void)
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* host brige. Abort on these systems.
|
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*/
|
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static struct pci_dev *hostbridge;
|
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u8 rev = 0;
|
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|
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hostbridge = pci_get_subsys(PCI_VENDOR_ID_INTEL,
|
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PCI_DEVICE_ID_INTEL_82815_MC,
|
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|
@ -216,8 +215,7 @@ static unsigned int speedstep_detect_chipset (void)
|
|||
if (!hostbridge)
|
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return 2; /* 2-M */
|
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|
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pci_read_config_byte(hostbridge, PCI_REVISION_ID, &rev);
|
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if (rev < 5) {
|
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if (hostbridge->revision < 5) {
|
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dprintk("hostbridge does not support speedstep\n");
|
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speedstep_chipset_dev = NULL;
|
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pci_dev_put(hostbridge);
|
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|
|
|
@ -23,13 +23,13 @@ static __init void lithium_init(void)
|
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set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS);
|
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|
||||
if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
|
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(li_pcia_read16(PCI_DEVICE_ID) != PCI_VENDOR_ID_SGI_LITHIUM)) {
|
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(li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
|
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printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A');
|
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panic("This machine is not SGI Visual Workstation 320/540");
|
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}
|
||||
|
||||
if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
|
||||
(li_pcib_read16(PCI_DEVICE_ID) != PCI_VENDOR_ID_SGI_LITHIUM)) {
|
||||
(li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
|
||||
printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B');
|
||||
panic("This machine is not SGI Visual Workstation 320/540");
|
||||
}
|
||||
|
|
|
@ -118,12 +118,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci
|
|||
static void pci_fixup_via_northbridge_bug(struct pci_dev *d)
|
||||
{
|
||||
u8 v;
|
||||
u8 revision;
|
||||
int where = 0x55;
|
||||
int mask = 0x1f; /* clear bits 5, 6, 7 by default */
|
||||
|
||||
pci_read_config_byte(d, PCI_REVISION_ID, &revision);
|
||||
|
||||
if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
|
||||
/* fix pci bus latency issues resulted by NB bios error
|
||||
it appears on bug free^Wreduced kt266x's bios forces
|
||||
|
@ -133,8 +130,8 @@ static void pci_fixup_via_northbridge_bug(struct pci_dev *d)
|
|||
where = 0x95; /* the memory write queue timer register is
|
||||
different for the KT266x's: 0x95 not 0x55 */
|
||||
} else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
|
||||
(revision == VIA_8363_KL133_REVISION_ID ||
|
||||
revision == VIA_8363_KM133_REVISION_ID)) {
|
||||
(d->revision == VIA_8363_KL133_REVISION_ID ||
|
||||
d->revision == VIA_8363_KM133_REVISION_ID)) {
|
||||
mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
|
||||
causes screen corruption on the KL133/KM133 */
|
||||
}
|
||||
|
@ -142,7 +139,7 @@ static void pci_fixup_via_northbridge_bug(struct pci_dev *d)
|
|||
pci_read_config_byte(d, where, &v);
|
||||
if (v & ~mask) {
|
||||
printk(KERN_WARNING "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
|
||||
d->device, revision, where, v, mask, v & mask);
|
||||
d->device, d->revision, where, v, mask, v & mask);
|
||||
v &= mask;
|
||||
pci_write_config_byte(d, where, v);
|
||||
}
|
||||
|
|
|
@ -520,8 +520,10 @@ config PCI
|
|||
here unless you are using a simulator without PCI support.
|
||||
|
||||
config PCI_DOMAINS
|
||||
bool
|
||||
default PCI
|
||||
def_bool PCI
|
||||
|
||||
config PCI_SYSCALL
|
||||
def_bool PCI
|
||||
|
||||
source "drivers/pci/pcie/Kconfig"
|
||||
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
# Makefile for the PCI specific kernel interface routines under Linux.
|
||||
#
|
||||
|
||||
obj-y += pci.o pci-dac.o
|
||||
obj-y += pci.o
|
||||
|
||||
#
|
||||
# PCI bus host bridge specific code
|
||||
|
|
|
@ -58,8 +58,6 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
|
|||
|
||||
static void qube_raq_galileo_fixup(struct pci_dev *dev)
|
||||
{
|
||||
unsigned short galileo_id;
|
||||
|
||||
if (dev->devfn != PCI_DEVFN(0, 0))
|
||||
return;
|
||||
|
||||
|
@ -84,16 +82,14 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
|
|||
* Therefore we must set the disconnect/retry cycle values to
|
||||
* something sensible when using the new Galileo.
|
||||
*/
|
||||
pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id);
|
||||
galileo_id &= 0xff; /* mask off class info */
|
||||
|
||||
printk(KERN_INFO "Galileo: revision %u\n", galileo_id);
|
||||
printk(KERN_INFO "Galileo: revision %u\n", dev->revision);
|
||||
|
||||
#if 0
|
||||
if (galileo_id >= 0x10) {
|
||||
if (dev->revision >= 0x10) {
|
||||
/* New Galileo, assumes PCI stop line to VIA is connected. */
|
||||
GT_WRITE(GT_PCI0_TOR_OFS, 0x4020);
|
||||
} else if (galileo_id == 0x1 || galileo_id == 0x2)
|
||||
} else if (dev->revision == 0x1 || dev->revision == 0x2)
|
||||
#endif
|
||||
{
|
||||
signed int timeo;
|
||||
|
|
|
@ -1,79 +0,0 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2000 Ani Joshi <ajoshi@unixbox.com>
|
||||
* Copyright (C) 2000, 2001, 06 Ralf Baechle <ralf@linux-mips.org>
|
||||
* swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
#include <asm/cache.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <dma-coherence.h>
|
||||
|
||||
#include <linux/pci.h>
|
||||
|
||||
dma64_addr_t pci_dac_page_to_dma(struct pci_dev *pdev,
|
||||
struct page *page, unsigned long offset, int direction)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
|
||||
BUG_ON(direction == DMA_NONE);
|
||||
|
||||
if (!plat_device_is_coherent(dev)) {
|
||||
unsigned long addr;
|
||||
|
||||
addr = (unsigned long) page_address(page) + offset;
|
||||
dma_cache_wback_inv(addr, PAGE_SIZE);
|
||||
}
|
||||
|
||||
return plat_map_dma_mem_page(dev, page) + offset;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(pci_dac_page_to_dma);
|
||||
|
||||
struct page *pci_dac_dma_to_page(struct pci_dev *pdev,
|
||||
dma64_addr_t dma_addr)
|
||||
{
|
||||
return pfn_to_page(plat_dma_addr_to_phys(dma_addr) >> PAGE_SHIFT);
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(pci_dac_dma_to_page);
|
||||
|
||||
unsigned long pci_dac_dma_to_offset(struct pci_dev *pdev,
|
||||
dma64_addr_t dma_addr)
|
||||
{
|
||||
return dma_addr & ~PAGE_MASK;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(pci_dac_dma_to_offset);
|
||||
|
||||
void pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev,
|
||||
dma64_addr_t dma_addr, size_t len, int direction)
|
||||
{
|
||||
BUG_ON(direction == PCI_DMA_NONE);
|
||||
|
||||
if (!plat_device_is_coherent(&pdev->dev))
|
||||
dma_cache_wback_inv(dma_addr + PAGE_OFFSET, len);
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(pci_dac_dma_sync_single_for_cpu);
|
||||
|
||||
void pci_dac_dma_sync_single_for_device(struct pci_dev *pdev,
|
||||
dma64_addr_t dma_addr, size_t len, int direction)
|
||||
{
|
||||
BUG_ON(direction == PCI_DMA_NONE);
|
||||
|
||||
if (!plat_device_is_coherent(&pdev->dev))
|
||||
dma_cache_wback_inv(dma_addr + PAGE_OFFSET, len);
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(pci_dac_dma_sync_single_for_device);
|
|
@ -698,8 +698,10 @@ config PCI
|
|||
infrastructure code to support PCI bus devices.
|
||||
|
||||
config PCI_DOMAINS
|
||||
bool
|
||||
default PCI
|
||||
def_bool PCI
|
||||
|
||||
config PCI_SYSCALL
|
||||
def_bool PCI
|
||||
|
||||
config PCI_QSPAN
|
||||
bool "QSpan PCI"
|
||||
|
|
|
@ -1047,10 +1047,10 @@ void pcibios_make_OF_bus_map(void)
|
|||
#endif /* CONFIG_PPC_OF */
|
||||
|
||||
/* Add sysfs properties */
|
||||
void pcibios_add_platform_entries(struct pci_dev *pdev)
|
||||
int pcibios_add_platform_entries(struct pci_dev *pdev)
|
||||
{
|
||||
#ifdef CONFIG_PPC_OF
|
||||
device_create_file(&pdev->dev, &dev_attr_devspec);
|
||||
return device_create_file(&pdev->dev, &dev_attr_devspec);
|
||||
#endif /* CONFIG_PPC_OF */
|
||||
}
|
||||
|
||||
|
|
|
@ -367,8 +367,10 @@ struct pci_dev *of_create_pci_dev(struct device_node *node,
|
|||
sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
|
||||
dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
|
||||
dev->class = get_int_prop(node, "class-code", 0);
|
||||
dev->revision = get_int_prop(node, "revision-id", 0);
|
||||
|
||||
DBG(" class: 0x%x\n", dev->class);
|
||||
DBG(" revision: 0x%x\n", dev->revision);
|
||||
|
||||
dev->current_state = 4; /* unknown power state */
|
||||
dev->error_state = pci_channel_io_normal;
|
||||
|
@ -876,9 +878,9 @@ static ssize_t pci_show_devspec(struct device *dev,
|
|||
}
|
||||
static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
|
||||
|
||||
void pcibios_add_platform_entries(struct pci_dev *pdev)
|
||||
int pcibios_add_platform_entries(struct pci_dev *pdev)
|
||||
{
|
||||
device_create_file(&pdev->dev, &dev_attr_devspec);
|
||||
return device_create_file(&pdev->dev, &dev_attr_devspec);
|
||||
}
|
||||
|
||||
#define ISA_SPACE_MASK 0x1
|
||||
|
|
|
@ -1237,8 +1237,10 @@ config PCI
|
|||
infrastructure code to support PCI bus devices.
|
||||
|
||||
config PCI_DOMAINS
|
||||
bool
|
||||
default PCI
|
||||
def_bool PCI
|
||||
|
||||
config PCI_SYSCALL
|
||||
def_bool PCI
|
||||
|
||||
config MPC83xx_PCI2
|
||||
bool "Support for 2nd PCI host controller"
|
||||
|
|
|
@ -633,12 +633,6 @@ void pcibios_make_OF_bus_map(void)
|
|||
{
|
||||
}
|
||||
|
||||
/* Add sysfs properties */
|
||||
void pcibios_add_platform_entries(struct pci_dev *pdev)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
static int __init
|
||||
pcibios_init(void)
|
||||
{
|
||||
|
|
|
@ -210,6 +210,9 @@ config PCI
|
|||
CP-1200, JavaEngine-1, Corona, Red October, and Serengeti SGSC.
|
||||
All of these platforms are extremely obscure, so say N if unsure.
|
||||
|
||||
config PCI_SYSCALL
|
||||
def_bool PCI
|
||||
|
||||
source "drivers/pci/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
@ -320,8 +320,10 @@ config PCI
|
|||
doesn't.
|
||||
|
||||
config PCI_DOMAINS
|
||||
bool
|
||||
default PCI
|
||||
def_bool PCI
|
||||
|
||||
config PCI_SYSCALL
|
||||
def_bool PCI
|
||||
|
||||
source "drivers/pci/Kconfig"
|
||||
|
||||
|
|
|
@ -448,6 +448,7 @@ struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
|
|||
*/
|
||||
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
|
||||
dev->class = class >> 8;
|
||||
dev->revision = class & 0xff;
|
||||
|
||||
sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
|
||||
dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
|
||||
|
|
|
@ -22,8 +22,7 @@ EXPORT_SYMBOL(bad_dma_address);
|
|||
int iommu_bio_merge __read_mostly = 0;
|
||||
EXPORT_SYMBOL(iommu_bio_merge);
|
||||
|
||||
int iommu_sac_force __read_mostly = 0;
|
||||
EXPORT_SYMBOL(iommu_sac_force);
|
||||
static int iommu_sac_force __read_mostly = 0;
|
||||
|
||||
int no_iommu __read_mostly;
|
||||
#ifdef CONFIG_IOMMU_DEBUG
|
||||
|
|
|
@ -115,7 +115,6 @@ struct acpi_processor_errata errata __read_mostly;
|
|||
|
||||
static int acpi_processor_errata_piix4(struct pci_dev *dev)
|
||||
{
|
||||
u8 rev = 0;
|
||||
u8 value1 = 0;
|
||||
u8 value2 = 0;
|
||||
|
||||
|
@ -127,9 +126,7 @@ static int acpi_processor_errata_piix4(struct pci_dev *dev)
|
|||
* Note that 'dev' references the PIIX4 ACPI Controller.
|
||||
*/
|
||||
|
||||
pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
|
||||
|
||||
switch (rev) {
|
||||
switch (dev->revision) {
|
||||
case 0:
|
||||
ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found PIIX4 A-step\n"));
|
||||
break;
|
||||
|
@ -147,7 +144,7 @@ static int acpi_processor_errata_piix4(struct pci_dev *dev)
|
|||
break;
|
||||
}
|
||||
|
||||
switch (rev) {
|
||||
switch (dev->revision) {
|
||||
|
||||
case 0: /* PIIX4 A-step */
|
||||
case 1: /* PIIX4 B-step */
|
||||
|
|
|
@ -928,20 +928,18 @@ static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
|
|||
{
|
||||
struct pci_dev *pdev = NULL;
|
||||
u16 cfg;
|
||||
u8 rev;
|
||||
int no_piix_dma = 0;
|
||||
|
||||
while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
|
||||
{
|
||||
/* Look for 450NX PXB. Check for problem configurations
|
||||
A PCI quirk checks bit 6 already */
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
|
||||
pci_read_config_word(pdev, 0x41, &cfg);
|
||||
/* Only on the original revision: IDE DMA can hang */
|
||||
if (rev == 0x00)
|
||||
if (pdev->revision == 0x00)
|
||||
no_piix_dma = 1;
|
||||
/* On all revisions below 5 PXB bus lock must be disabled for IDE */
|
||||
else if (cfg & (1<<14) && rev < 5)
|
||||
else if (cfg & (1<<14) && pdev->revision < 5)
|
||||
no_piix_dma = 2;
|
||||
}
|
||||
if (no_piix_dma)
|
||||
|
|
|
@ -455,23 +455,21 @@ static struct ata_port_operations ali_c5_port_ops = {
|
|||
|
||||
static void ali_init_chipset(struct pci_dev *pdev)
|
||||
{
|
||||
u8 rev, tmp;
|
||||
u8 tmp;
|
||||
struct pci_dev *north, *isa_bridge;
|
||||
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
|
||||
|
||||
/*
|
||||
* The chipset revision selects the driver operations and
|
||||
* mode data.
|
||||
*/
|
||||
|
||||
if (rev >= 0x20 && rev < 0xC2) {
|
||||
if (pdev->revision >= 0x20 && pdev->revision < 0xC2) {
|
||||
/* 1543-E/F, 1543C-C, 1543C-D, 1543C-E */
|
||||
pci_read_config_byte(pdev, 0x4B, &tmp);
|
||||
/* Clear CD-ROM DMA write bit */
|
||||
tmp &= 0x7F;
|
||||
pci_write_config_byte(pdev, 0x4B, tmp);
|
||||
} else if (rev >= 0xC2) {
|
||||
} else if (pdev->revision >= 0xC2) {
|
||||
/* Enable cable detection logic */
|
||||
pci_read_config_byte(pdev, 0x4B, &tmp);
|
||||
pci_write_config_byte(pdev, 0x4B, tmp | 0x08);
|
||||
|
@ -483,21 +481,21 @@ static void ali_init_chipset(struct pci_dev *pdev)
|
|||
/* Configure the ALi bridge logic. For non ALi rely on BIOS.
|
||||
Set the south bridge enable bit */
|
||||
pci_read_config_byte(isa_bridge, 0x79, &tmp);
|
||||
if (rev == 0xC2)
|
||||
if (pdev->revision == 0xC2)
|
||||
pci_write_config_byte(isa_bridge, 0x79, tmp | 0x04);
|
||||
else if (rev > 0xC2 && rev < 0xC5)
|
||||
else if (pdev->revision > 0xC2 && pdev->revision < 0xC5)
|
||||
pci_write_config_byte(isa_bridge, 0x79, tmp | 0x02);
|
||||
}
|
||||
if (rev >= 0x20) {
|
||||
if (pdev->revision >= 0x20) {
|
||||
/*
|
||||
* CD_ROM DMA on (0x53 bit 0). Enable this even if we want
|
||||
* to use PIO. 0x53 bit 1 (rev 20 only) - enable FIFO control
|
||||
* via 0x54/55.
|
||||
*/
|
||||
pci_read_config_byte(pdev, 0x53, &tmp);
|
||||
if (rev <= 0x20)
|
||||
if (pdev->revision <= 0x20)
|
||||
tmp &= ~0x02;
|
||||
if (rev >= 0xc7)
|
||||
if (pdev->revision >= 0xc7)
|
||||
tmp |= 0x03;
|
||||
else
|
||||
tmp |= 0x01; /* CD_ROM enable for DMA */
|
||||
|
@ -579,25 +577,23 @@ static int ali_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
};
|
||||
|
||||
const struct ata_port_info *ppi[] = { NULL, NULL };
|
||||
u8 rev, tmp;
|
||||
u8 tmp;
|
||||
struct pci_dev *isa_bridge;
|
||||
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
|
||||
|
||||
/*
|
||||
* The chipset revision selects the driver operations and
|
||||
* mode data.
|
||||
*/
|
||||
|
||||
if (rev < 0x20) {
|
||||
if (pdev->revision < 0x20) {
|
||||
ppi[0] = &info_early;
|
||||
} else if (rev < 0xC2) {
|
||||
} else if (pdev->revision < 0xC2) {
|
||||
ppi[0] = &info_20;
|
||||
} else if (rev == 0xC2) {
|
||||
} else if (pdev->revision == 0xC2) {
|
||||
ppi[0] = &info_c2;
|
||||
} else if (rev == 0xC3) {
|
||||
} else if (pdev->revision == 0xC3) {
|
||||
ppi[0] = &info_c3;
|
||||
} else if (rev == 0xC4) {
|
||||
} else if (pdev->revision == 0xC4) {
|
||||
ppi[0] = &info_c4;
|
||||
} else
|
||||
ppi[0] = &info_c5;
|
||||
|
@ -605,7 +601,7 @@ static int ali_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
ali_init_chipset(pdev);
|
||||
|
||||
isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
|
||||
if (isa_bridge && rev >= 0x20 && rev < 0xC2) {
|
||||
if (isa_bridge && pdev->revision >= 0x20 && pdev->revision < 0xC2) {
|
||||
/* Are we paired with a UDMA capable chip */
|
||||
pci_read_config_byte(isa_bridge, 0x5E, &tmp);
|
||||
if ((tmp & 0x1E) == 0x12)
|
||||
|
|
|
@ -623,17 +623,15 @@ static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
const struct ata_port_info *ppi[] = { NULL, NULL };
|
||||
static int printed_version;
|
||||
int type = id->driver_data;
|
||||
u8 rev;
|
||||
u8 fifo;
|
||||
|
||||
if (!printed_version++)
|
||||
dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
|
||||
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
|
||||
pci_read_config_byte(pdev, 0x41, &fifo);
|
||||
|
||||
/* Check for AMD7409 without swdma errata and if found adjust type */
|
||||
if (type == 1 && rev > 0x7)
|
||||
if (type == 1 && pdev->revision > 0x7)
|
||||
type = 2;
|
||||
|
||||
/* Check for AMD7411 */
|
||||
|
|
|
@ -266,7 +266,7 @@ static int cs5530_init_chip(void)
|
|||
}
|
||||
|
||||
pci_set_master(cs5530_0);
|
||||
pci_set_mwi(cs5530_0);
|
||||
pci_try_set_mwi(cs5530_0);
|
||||
|
||||
/*
|
||||
* Set PCI CacheLineSize to 16-bytes:
|
||||
|
|
|
@ -587,8 +587,7 @@ static int it821x_port_start(struct ata_port *ap)
|
|||
itdev->want[1][1] = ATA_ANY;
|
||||
itdev->last_device = -1;
|
||||
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &conf);
|
||||
if (conf == 0x10) {
|
||||
if (pdev->revision == 0x11) {
|
||||
itdev->timing10 = 1;
|
||||
/* Need to disable ATAPI DMA for this case */
|
||||
if (!itdev->smart)
|
||||
|
|
|
@ -410,11 +410,8 @@ static int serverworks_fixup_osb4(struct pci_dev *pdev)
|
|||
|
||||
static int serverworks_fixup_csb(struct pci_dev *pdev)
|
||||
{
|
||||
u8 rev;
|
||||
u8 btr;
|
||||
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
|
||||
|
||||
/* Third Channel Test */
|
||||
if (!(PCI_FUNC(pdev->devfn) & 1)) {
|
||||
struct pci_dev * findev = NULL;
|
||||
|
@ -456,7 +453,7 @@ static int serverworks_fixup_csb(struct pci_dev *pdev)
|
|||
if (!(PCI_FUNC(pdev->devfn) & 1))
|
||||
btr |= 0x2;
|
||||
else
|
||||
btr |= (rev >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
|
||||
btr |= (pdev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
|
||||
pci_write_config_byte(pdev, 0x5A, btr);
|
||||
|
||||
return btr;
|
||||
|
|
|
@ -931,9 +931,7 @@ static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
if (host != NULL) {
|
||||
chipset = sets; /* Match found */
|
||||
if (sets->device == 0x630) { /* SIS630 */
|
||||
u8 host_rev;
|
||||
pci_read_config_byte(host, PCI_REVISION_ID, &host_rev);
|
||||
if (host_rev >= 0x30) /* 630 ET */
|
||||
if (host->revision >= 0x30) /* 630 ET */
|
||||
chipset = &sis100_early;
|
||||
}
|
||||
break;
|
||||
|
@ -977,7 +975,6 @@ static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
u16 trueid;
|
||||
u8 prefctl;
|
||||
u8 idecfg;
|
||||
u8 sbrev;
|
||||
|
||||
/* Try the second unmasking technique */
|
||||
pci_read_config_byte(pdev, 0x4a, &idecfg);
|
||||
|
@ -990,11 +987,10 @@ static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */
|
||||
if (lpc_bridge == NULL)
|
||||
break;
|
||||
pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev);
|
||||
pci_read_config_byte(pdev, 0x49, &prefctl);
|
||||
pci_dev_put(lpc_bridge);
|
||||
|
||||
if (sbrev == 0x10 && (prefctl & 0x80)) {
|
||||
if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
|
||||
chipset = &sis133_early;
|
||||
break;
|
||||
}
|
||||
|
|
|
@ -270,7 +270,6 @@ static struct ata_port_operations sl82c105_port_ops = {
|
|||
static int sl82c105_bridge_revision(struct pci_dev *pdev)
|
||||
{
|
||||
struct pci_dev *bridge;
|
||||
u8 rev;
|
||||
|
||||
/*
|
||||
* The bridge should be part of the same device, but function 0.
|
||||
|
@ -292,10 +291,8 @@ static int sl82c105_bridge_revision(struct pci_dev *pdev)
|
|||
/*
|
||||
* We need to find function 0's revision, not function 1
|
||||
*/
|
||||
pci_read_config_byte(bridge, PCI_REVISION_ID, &rev);
|
||||
|
||||
pci_dev_put(bridge);
|
||||
return rev;
|
||||
return bridge->revision;
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -506,7 +506,6 @@ static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
struct pci_dev *isa = NULL;
|
||||
const struct via_isa_bridge *config;
|
||||
static int printed_version;
|
||||
u8 t;
|
||||
u8 enable;
|
||||
u32 timing;
|
||||
|
||||
|
@ -520,9 +519,8 @@ static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
!!(config->flags & VIA_BAD_ID),
|
||||
config->id, NULL))) {
|
||||
|
||||
pci_read_config_byte(isa, PCI_REVISION_ID, &t);
|
||||
if (t >= config->rev_min &&
|
||||
t <= config->rev_max)
|
||||
if (isa->revision >= config->rev_min &&
|
||||
isa->revision <= config->rev_max)
|
||||
break;
|
||||
pci_dev_put(isa);
|
||||
}
|
||||
|
|
|
@ -1765,12 +1765,9 @@ static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
|
|||
|
||||
static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
|
||||
{
|
||||
u8 rev_id;
|
||||
int early_5080;
|
||||
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
|
||||
|
||||
early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
|
||||
early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
|
||||
|
||||
if (!early_5080) {
|
||||
u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
|
||||
|
@ -2387,17 +2384,14 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
|
|||
{
|
||||
struct pci_dev *pdev = to_pci_dev(host->dev);
|
||||
struct mv_host_priv *hpriv = host->private_data;
|
||||
u8 rev_id;
|
||||
u32 hp_flags = hpriv->hp_flags;
|
||||
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
|
||||
|
||||
switch(board_idx) {
|
||||
case chip_5080:
|
||||
hpriv->ops = &mv5xxx_ops;
|
||||
hp_flags |= MV_HP_GEN_I;
|
||||
|
||||
switch (rev_id) {
|
||||
switch (pdev->revision) {
|
||||
case 0x1:
|
||||
hp_flags |= MV_HP_ERRATA_50XXB0;
|
||||
break;
|
||||
|
@ -2417,7 +2411,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
|
|||
hpriv->ops = &mv5xxx_ops;
|
||||
hp_flags |= MV_HP_GEN_I;
|
||||
|
||||
switch (rev_id) {
|
||||
switch (pdev->revision) {
|
||||
case 0x0:
|
||||
hp_flags |= MV_HP_ERRATA_50XXB0;
|
||||
break;
|
||||
|
@ -2437,7 +2431,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
|
|||
hpriv->ops = &mv6xxx_ops;
|
||||
hp_flags |= MV_HP_GEN_II;
|
||||
|
||||
switch (rev_id) {
|
||||
switch (pdev->revision) {
|
||||
case 0x7:
|
||||
hp_flags |= MV_HP_ERRATA_60X1B2;
|
||||
break;
|
||||
|
@ -2457,7 +2451,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
|
|||
hpriv->ops = &mv6xxx_ops;
|
||||
hp_flags |= MV_HP_GEN_IIE;
|
||||
|
||||
switch (rev_id) {
|
||||
switch (pdev->revision) {
|
||||
case 0x0:
|
||||
hp_flags |= MV_HP_ERRATA_XX42A0;
|
||||
break;
|
||||
|
@ -2585,14 +2579,12 @@ static void mv_print_info(struct ata_host *host)
|
|||
{
|
||||
struct pci_dev *pdev = to_pci_dev(host->dev);
|
||||
struct mv_host_priv *hpriv = host->private_data;
|
||||
u8 rev_id, scc;
|
||||
u8 scc;
|
||||
const char *scc_s, *gen;
|
||||
|
||||
/* Use this to determine the HW stepping of the chip so we know
|
||||
* what errata to workaround
|
||||
*/
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
|
||||
|
||||
pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
|
||||
if (scc == 0)
|
||||
scc_s = "SCSI";
|
||||
|
|
|
@ -1704,7 +1704,6 @@ static int __devinit eni_do_init(struct atm_dev *dev)
|
|||
struct pci_dev *pci_dev;
|
||||
unsigned long real_base;
|
||||
void __iomem *base;
|
||||
unsigned char revision;
|
||||
int error,i,last;
|
||||
|
||||
DPRINTK(">eni_init\n");
|
||||
|
@ -1715,12 +1714,6 @@ static int __devinit eni_do_init(struct atm_dev *dev)
|
|||
pci_dev = eni_dev->pci_dev;
|
||||
real_base = pci_resource_start(pci_dev, 0);
|
||||
eni_dev->irq = pci_dev->irq;
|
||||
error = pci_read_config_byte(pci_dev,PCI_REVISION_ID,&revision);
|
||||
if (error) {
|
||||
printk(KERN_ERR DEV_LABEL "(itf %d): init error 0x%02x\n",
|
||||
dev->number,error);
|
||||
return -EINVAL;
|
||||
}
|
||||
if ((error = pci_write_config_word(pci_dev,PCI_COMMAND,
|
||||
PCI_COMMAND_MEMORY |
|
||||
(eni_dev->asic ? PCI_COMMAND_PARITY | PCI_COMMAND_SERR : 0)))) {
|
||||
|
@ -1729,7 +1722,7 @@ static int __devinit eni_do_init(struct atm_dev *dev)
|
|||
return -EIO;
|
||||
}
|
||||
printk(KERN_NOTICE DEV_LABEL "(itf %d): rev.%d,base=0x%lx,irq=%d,",
|
||||
dev->number,revision,real_base,eni_dev->irq);
|
||||
dev->number,pci_dev->revision,real_base,eni_dev->irq);
|
||||
if (!(base = ioremap_nocache(real_base,MAP_MAX_SIZE))) {
|
||||
printk("\n");
|
||||
printk(KERN_ERR DEV_LABEL "(itf %d): can't set up page "
|
||||
|
|
|
@ -3679,7 +3679,6 @@ idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id)
|
|||
unsigned long membase, srambase;
|
||||
struct idt77252_dev *card;
|
||||
struct atm_dev *dev;
|
||||
ushort revision = 0;
|
||||
int i, err;
|
||||
|
||||
|
||||
|
@ -3688,19 +3687,13 @@ idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id)
|
|||
return err;
|
||||
}
|
||||
|
||||
if (pci_read_config_word(pcidev, PCI_REVISION_ID, &revision)) {
|
||||
printk("idt77252-%d: can't read PCI_REVISION_ID\n", index);
|
||||
err = -ENODEV;
|
||||
goto err_out_disable_pdev;
|
||||
}
|
||||
|
||||
card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL);
|
||||
if (!card) {
|
||||
printk("idt77252-%d: can't allocate private data\n", index);
|
||||
err = -ENOMEM;
|
||||
goto err_out_disable_pdev;
|
||||
}
|
||||
card->revision = revision;
|
||||
card->revision = pcidev->revision;
|
||||
card->index = index;
|
||||
card->pcidev = pcidev;
|
||||
sprintf(card->name, "idt77252-%d", card->index);
|
||||
|
@ -3762,8 +3755,8 @@ idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id)
|
|||
}
|
||||
|
||||
printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n",
|
||||
card->name, ((revision > 1) && (revision < 25)) ?
|
||||
'A' + revision - 1 : '?', membase, srambase,
|
||||
card->name, ((card->revision > 1) && (card->revision < 25)) ?
|
||||
'A' + card->revision - 1 : '?', membase, srambase,
|
||||
card->sramsize / 1024);
|
||||
|
||||
if (init_card(dev)) {
|
||||
|
|
|
@ -2290,7 +2290,6 @@ static int __devinit ia_init(struct atm_dev *dev)
|
|||
unsigned long real_base;
|
||||
void __iomem *base;
|
||||
unsigned short command;
|
||||
unsigned char revision;
|
||||
int error, i;
|
||||
|
||||
/* The device has been identified and registered. Now we read
|
||||
|
@ -2305,16 +2304,14 @@ static int __devinit ia_init(struct atm_dev *dev)
|
|||
real_base = pci_resource_start (iadev->pci, 0);
|
||||
iadev->irq = iadev->pci->irq;
|
||||
|
||||
if ((error = pci_read_config_word(iadev->pci, PCI_COMMAND,&command))
|
||||
|| (error = pci_read_config_byte(iadev->pci,
|
||||
PCI_REVISION_ID,&revision)))
|
||||
{
|
||||
error = pci_read_config_word(iadev->pci, PCI_COMMAND, &command);
|
||||
if (error) {
|
||||
printk(KERN_ERR DEV_LABEL "(itf %d): init error 0x%x\n",
|
||||
dev->number,error);
|
||||
return -EINVAL;
|
||||
}
|
||||
IF_INIT(printk(DEV_LABEL "(itf %d): rev.%d,realbase=0x%lx,irq=%d\n",
|
||||
dev->number, revision, real_base, iadev->irq);)
|
||||
dev->number, iadev->pci->revision, real_base, iadev->irq);)
|
||||
|
||||
/* find mapping size of board */
|
||||
|
||||
|
@ -2353,7 +2350,7 @@ static int __devinit ia_init(struct atm_dev *dev)
|
|||
return error;
|
||||
}
|
||||
IF_INIT(printk(DEV_LABEL " (itf %d): rev.%d,base=%p,irq=%d\n",
|
||||
dev->number, revision, base, iadev->irq);)
|
||||
dev->number, iadev->pci->revision, base, iadev->irq);)
|
||||
|
||||
/* filling the iphase dev structure */
|
||||
iadev->mem = iadev->pci_map_size /2;
|
||||
|
|
|
@ -246,8 +246,8 @@ struct lanai_vcc {
|
|||
};
|
||||
|
||||
enum lanai_type {
|
||||
lanai2 = PCI_VENDOR_ID_EF_ATM_LANAI2,
|
||||
lanaihb = PCI_VENDOR_ID_EF_ATM_LANAIHB
|
||||
lanai2 = PCI_DEVICE_ID_EF_ATM_LANAI2,
|
||||
lanaihb = PCI_DEVICE_ID_EF_ATM_LANAIHB
|
||||
};
|
||||
|
||||
struct lanai_dev_stats {
|
||||
|
@ -293,7 +293,6 @@ struct lanai_dev {
|
|||
struct atm_vcc *cbrvcc;
|
||||
int number;
|
||||
int board_rev;
|
||||
u8 pci_revision;
|
||||
/* TODO - look at race conditions with maintence of conf1/conf2 */
|
||||
/* TODO - transmit locking: should we use _irq not _irqsave? */
|
||||
/* TODO - organize above in some rational fashion (see <asm/cache.h>) */
|
||||
|
@ -1969,14 +1968,6 @@ static int __devinit lanai_pci_start(struct lanai_dev *lanai)
|
|||
"(itf %d): No suitable DMA available.\n", lanai->number);
|
||||
return -EBUSY;
|
||||
}
|
||||
/* Get the pci revision byte */
|
||||
result = pci_read_config_byte(pci, PCI_REVISION_ID,
|
||||
&lanai->pci_revision);
|
||||
if (result != PCIBIOS_SUCCESSFUL) {
|
||||
printk(KERN_ERR DEV_LABEL "(itf %d): can't read "
|
||||
"PCI_REVISION_ID: %d\n", lanai->number, result);
|
||||
return -EINVAL;
|
||||
}
|
||||
result = pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &w);
|
||||
if (result != PCIBIOS_SUCCESSFUL) {
|
||||
printk(KERN_ERR DEV_LABEL "(itf %d): can't read "
|
||||
|
@ -2254,7 +2245,7 @@ static int __devinit lanai_dev_open(struct atm_dev *atmdev)
|
|||
lanai_timed_poll_start(lanai);
|
||||
printk(KERN_NOTICE DEV_LABEL "(itf %d): rev.%d, base=0x%lx, irq=%u "
|
||||
"(%02X-%02X-%02X-%02X-%02X-%02X)\n", lanai->number,
|
||||
(int) lanai->pci_revision, (unsigned long) lanai->base,
|
||||
(int) lanai->pci->revision, (unsigned long) lanai->base,
|
||||
lanai->pci->irq,
|
||||
atmdev->esi[0], atmdev->esi[1], atmdev->esi[2],
|
||||
atmdev->esi[3], atmdev->esi[4], atmdev->esi[5]);
|
||||
|
@ -2491,7 +2482,7 @@ static int lanai_proc_read(struct atm_dev *atmdev, loff_t *pos, char *page)
|
|||
(unsigned int) lanai->magicno, lanai->num_vci);
|
||||
if (left-- == 0)
|
||||
return sprintf(page, "revision: board=%d, pci_if=%d\n",
|
||||
lanai->board_rev, (int) lanai->pci_revision);
|
||||
lanai->board_rev, (int) lanai->pci->revision);
|
||||
if (left-- == 0)
|
||||
return sprintf(page, "EEPROM ESI: "
|
||||
"%02X:%02X:%02X:%02X:%02X:%02X\n",
|
||||
|
@ -2631,14 +2622,8 @@ static int __devinit lanai_init_one(struct pci_dev *pci,
|
|||
}
|
||||
|
||||
static struct pci_device_id lanai_pci_tbl[] = {
|
||||
{
|
||||
PCI_VENDOR_ID_EF, PCI_VENDOR_ID_EF_ATM_LANAI2,
|
||||
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_ID_EF, PCI_VENDOR_ID_EF_ATM_LANAIHB,
|
||||
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
|
||||
},
|
||||
{ PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAI2) },
|
||||
{ PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAIHB) },
|
||||
{ 0, } /* terminal entry */
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, lanai_pci_tbl);
|
||||
|
|
|
@ -1182,7 +1182,6 @@ static int __devinit zatm_init(struct atm_dev *dev)
|
|||
struct zatm_dev *zatm_dev;
|
||||
struct pci_dev *pci_dev;
|
||||
unsigned short command;
|
||||
unsigned char revision;
|
||||
int error,i,last;
|
||||
unsigned long t0,t1,t2;
|
||||
|
||||
|
@ -1192,8 +1191,7 @@ static int __devinit zatm_init(struct atm_dev *dev)
|
|||
pci_dev = zatm_dev->pci_dev;
|
||||
zatm_dev->base = pci_resource_start(pci_dev, 0);
|
||||
zatm_dev->irq = pci_dev->irq;
|
||||
if ((error = pci_read_config_word(pci_dev,PCI_COMMAND,&command)) ||
|
||||
(error = pci_read_config_byte(pci_dev,PCI_REVISION_ID,&revision))) {
|
||||
if ((error = pci_read_config_word(pci_dev,PCI_COMMAND,&command))) {
|
||||
printk(KERN_ERR DEV_LABEL "(itf %d): init error 0x%02x\n",
|
||||
dev->number,error);
|
||||
return -EINVAL;
|
||||
|
@ -1206,7 +1204,7 @@ static int __devinit zatm_init(struct atm_dev *dev)
|
|||
}
|
||||
eprom_get_esi(dev);
|
||||
printk(KERN_NOTICE DEV_LABEL "(itf %d): rev.%d,base=0x%x,irq=%d,",
|
||||
dev->number,revision,zatm_dev->base,zatm_dev->irq);
|
||||
dev->number,pci_dev->revision,zatm_dev->base,zatm_dev->irq);
|
||||
/* reset uPD98401 */
|
||||
zout(0,SWR);
|
||||
while (!(zin(GSR) & uPD98401_INT_IND));
|
||||
|
|
|
@ -462,9 +462,7 @@ static int __devinit agp_amdk7_probe(struct pci_dev *pdev,
|
|||
* erratum 46: Setup violation on AGP SBA pins - Disable side band addressing.
|
||||
* With this lot disabled, we should prevent lockups. */
|
||||
if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_700E) {
|
||||
u8 revision=0;
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &revision);
|
||||
if (revision == 0x10 || revision == 0x11) {
|
||||
if (pdev->revision == 0x10 || pdev->revision == 0x11) {
|
||||
agp_bridge->flags = AGP_ERRATA_FASTWRITES;
|
||||
agp_bridge->flags |= AGP_ERRATA_SBA;
|
||||
agp_bridge->flags |= AGP_ERRATA_1X;
|
||||
|
|
|
@ -367,10 +367,8 @@ static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
|
|||
static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
|
||||
{
|
||||
char *revstring;
|
||||
u8 rev_id;
|
||||
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
|
||||
switch (rev_id) {
|
||||
switch (pdev->revision) {
|
||||
case 0x01: revstring="A0"; break;
|
||||
case 0x02: revstring="A1"; break;
|
||||
case 0x11: revstring="B0"; break;
|
||||
|
@ -386,7 +384,7 @@ static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data
|
|||
* Work around errata.
|
||||
* Chips before B2 stepping incorrectly reporting v3.5
|
||||
*/
|
||||
if (rev_id < 0x13) {
|
||||
if (pdev->revision < 0x13) {
|
||||
printk (KERN_INFO PFX "Correcting AGP revision (reports 3.5, is really 3.0)\n");
|
||||
bridge->major_version = 3;
|
||||
bridge->minor_version = 0;
|
||||
|
|
|
@ -105,14 +105,11 @@ static inline void acpi_pm_need_workaround(void)
|
|||
*/
|
||||
static void __devinit acpi_pm_check_blacklist(struct pci_dev *dev)
|
||||
{
|
||||
u8 rev;
|
||||
|
||||
if (acpi_pm_good)
|
||||
return;
|
||||
|
||||
pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
|
||||
/* the bug has been fixed in PIIX4M */
|
||||
if (rev < 3) {
|
||||
if (dev->revision < 3) {
|
||||
printk(KERN_WARNING "* Found PM-Timer Bug on the chipset."
|
||||
" Due to workarounds for a bug,\n"
|
||||
"* this clock source is slow. Consider trying"
|
||||
|
|
|
@ -397,8 +397,7 @@ found:
|
|||
case PCI_DEVICE_ID_VIA_82C686_4:
|
||||
/* The VT82C686B (rev 0x40) does support I2C block
|
||||
transactions, but the VT82C686A (rev 0x30) doesn't */
|
||||
if (!pci_read_config_byte(pdev, PCI_REVISION_ID, &temp)
|
||||
&& temp >= 0x40)
|
||||
if (pdev->revision >= 0x40)
|
||||
vt596_features |= FEATURE_I2CBLOCK;
|
||||
break;
|
||||
}
|
||||
|
|
|
@ -508,7 +508,7 @@ static unsigned int __devinit init_chipset_ali15x3 (struct pci_dev *dev, const c
|
|||
u8 tmpbyte;
|
||||
struct pci_dev *north = pci_get_slot(dev->bus, PCI_DEVFN(0,0));
|
||||
|
||||
pci_read_config_byte(dev, PCI_REVISION_ID, &m5229_revision);
|
||||
m5229_revision = dev->revision;
|
||||
|
||||
isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
|
||||
|
||||
|
|
|
@ -123,8 +123,7 @@ static int amd74xx_get_info(char *buffer, char **addr, off_t offset, int count)
|
|||
amd_print("Driver Version: 2.13");
|
||||
amd_print("South Bridge: %s", pci_name(bmide_dev));
|
||||
|
||||
pci_read_config_byte(dev, PCI_REVISION_ID, &t);
|
||||
amd_print("Revision: IDE %#x", t);
|
||||
amd_print("Revision: IDE %#x", dev->revision);
|
||||
amd_print("Highest DMA rate: UDMA%s", amd_dma[fls(amd_config->udma_mask) - 1]);
|
||||
|
||||
amd_print("BM-DMA base: %#lx", amd_base);
|
||||
|
@ -312,8 +311,7 @@ static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev, const ch
|
|||
*/
|
||||
|
||||
if (amd_config->flags & AMD_CHECK_SWDMA) {
|
||||
pci_read_config_byte(dev, PCI_REVISION_ID, &t);
|
||||
if (t <= 7)
|
||||
if (dev->revision <= 7)
|
||||
amd_config->flags |= AMD_BAD_SWDMA;
|
||||
}
|
||||
|
||||
|
@ -383,7 +381,7 @@ static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev, const ch
|
|||
|
||||
pci_read_config_byte(dev, PCI_REVISION_ID, &t);
|
||||
printk(KERN_INFO "%s: %s (rev %02x) UDMA%s controller\n",
|
||||
amd_chipset->name, pci_name(dev), t,
|
||||
amd_chipset->name, pci_name(dev), dev->revision,
|
||||
amd_dma[fls(amd_config->udma_mask) - 1]);
|
||||
|
||||
/*
|
||||
|
|
|
@ -88,7 +88,6 @@ static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
|
|||
u8 reg72 = 0, reg73 = 0; /* primary */
|
||||
u8 reg7a = 0, reg7b = 0; /* secondary */
|
||||
u8 reg50 = 1, reg51 = 1, reg57 = 0, reg71 = 0; /* extra */
|
||||
u8 rev = 0;
|
||||
|
||||
p += sprintf(p, "\nController: %d\n", index);
|
||||
p += sprintf(p, "PCI-%x Chipset.\n", dev->device);
|
||||
|
@ -103,9 +102,8 @@ static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
|
|||
(void) pci_read_config_byte(dev, UDIDETCR1, ®7b);
|
||||
|
||||
/* PCI0643/6 originally didn't have the primary channel enable bit */
|
||||
(void) pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
|
||||
if ((dev->device == PCI_DEVICE_ID_CMD_643) ||
|
||||
(dev->device == PCI_DEVICE_ID_CMD_646 && rev < 3))
|
||||
(dev->device == PCI_DEVICE_ID_CMD_646 && dev->revision < 3))
|
||||
reg51 |= CNTRL_ENA_1ST;
|
||||
|
||||
p += sprintf(p, "---------------- Primary Channel "
|
||||
|
@ -604,14 +602,11 @@ static int __devinit init_setup_cmd64x(struct pci_dev *dev, ide_pci_device_t *d)
|
|||
|
||||
static int __devinit init_setup_cmd646(struct pci_dev *dev, ide_pci_device_t *d)
|
||||
{
|
||||
u8 rev = 0;
|
||||
|
||||
/*
|
||||
* The original PCI0646 didn't have the primary channel enable bit,
|
||||
* it appeared starting with PCI0646U (i.e. revision ID 3).
|
||||
*/
|
||||
pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
|
||||
if (rev < 3)
|
||||
if (dev->revision < 3)
|
||||
d->enablebits[0].reg = 0;
|
||||
|
||||
return ide_setup_pci_device(dev, d);
|
||||
|
|
|
@ -236,7 +236,7 @@ static unsigned int __devinit init_chipset_cs5530 (struct pci_dev *dev, const ch
|
|||
*/
|
||||
|
||||
pci_set_master(cs5530_0);
|
||||
pci_set_mwi(cs5530_0);
|
||||
pci_try_set_mwi(cs5530_0);
|
||||
|
||||
/*
|
||||
* Set PCI CacheLineSize to 16-bytes:
|
||||
|
|
|
@ -1413,11 +1413,9 @@ static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d
|
|||
static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
|
||||
{
|
||||
struct hpt_info *info;
|
||||
u8 rev = 0, mcr1 = 0;
|
||||
u8 mcr1 = 0;
|
||||
|
||||
pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
|
||||
|
||||
if (rev > 1) {
|
||||
if (dev->revision > 1) {
|
||||
d->name = "HPT371N";
|
||||
|
||||
info = &hpt371n;
|
||||
|
@ -1442,11 +1440,8 @@ static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
|
|||
static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
|
||||
{
|
||||
struct hpt_info *info;
|
||||
u8 rev = 0;
|
||||
|
||||
pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
|
||||
|
||||
if (rev > 1) {
|
||||
if (dev->revision > 1) {
|
||||
d->name = "HPT372N";
|
||||
|
||||
info = &hpt372n;
|
||||
|
@ -1460,11 +1455,8 @@ static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d
|
|||
static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
|
||||
{
|
||||
struct hpt_info *info;
|
||||
u8 rev = 0;
|
||||
|
||||
pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
|
||||
|
||||
if (rev > 1) {
|
||||
if (dev->revision > 1) {
|
||||
d->name = "HPT302N";
|
||||
|
||||
info = &hpt302n;
|
||||
|
@ -1478,7 +1470,7 @@ static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
|
|||
static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
|
||||
{
|
||||
struct pci_dev *dev2;
|
||||
u8 rev = 0;
|
||||
u8 rev = dev->revision;
|
||||
static char *chipset_names[] = { "HPT366", "HPT366", "HPT368",
|
||||
"HPT370", "HPT370A", "HPT372",
|
||||
"HPT372N" };
|
||||
|
@ -1489,8 +1481,6 @@ static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
|
|||
if (PCI_FUNC(dev->devfn) & 1)
|
||||
return -ENODEV;
|
||||
|
||||
pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
|
||||
|
||||
switch (rev) {
|
||||
case 0:
|
||||
case 1:
|
||||
|
|
|
@ -572,18 +572,16 @@ static void __devinit piix_check_450nx(void)
|
|||
{
|
||||
struct pci_dev *pdev = NULL;
|
||||
u16 cfg;
|
||||
u8 rev;
|
||||
while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
|
||||
{
|
||||
/* Look for 450NX PXB. Check for problem configurations
|
||||
A PCI quirk checks bit 6 already */
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
|
||||
pci_read_config_word(pdev, 0x41, &cfg);
|
||||
/* Only on the original revision: IDE DMA can hang */
|
||||
if(rev == 0x00)
|
||||
if (pdev->revision == 0x00)
|
||||
no_piix_dma = 1;
|
||||
/* On all revisions below 5 PXB bus lock must be disabled for IDE */
|
||||
else if(cfg & (1<<14) && rev < 5)
|
||||
else if (cfg & (1<<14) && pdev->revision < 5)
|
||||
no_piix_dma = 2;
|
||||
}
|
||||
if(no_piix_dma)
|
||||
|
|
|
@ -55,7 +55,6 @@ static const char *svwks_bad_ata100[] = {
|
|||
NULL
|
||||
};
|
||||
|
||||
static u8 svwks_revision = 0;
|
||||
static struct pci_dev *isa_dev;
|
||||
|
||||
static int check_in_drive_lists (ide_drive_t *drive, const char **list)
|
||||
|
@ -71,9 +70,6 @@ static u8 svwks_udma_filter(ide_drive_t *drive)
|
|||
struct pci_dev *dev = HWIF(drive)->pci_dev;
|
||||
u8 mask = 0;
|
||||
|
||||
if (!svwks_revision)
|
||||
pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
|
||||
|
||||
if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
|
||||
return 0x1f;
|
||||
if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
|
||||
|
@ -88,9 +84,9 @@ static u8 svwks_udma_filter(ide_drive_t *drive)
|
|||
return 0;
|
||||
/* Check the OSB4 DMA33 enable bit */
|
||||
return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
|
||||
} else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) {
|
||||
} else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
|
||||
return 0x07;
|
||||
} else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) {
|
||||
} else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) {
|
||||
u8 btr = 0, mode;
|
||||
pci_read_config_byte(dev, 0x5A, &btr);
|
||||
mode = btr & 0x3;
|
||||
|
@ -234,9 +230,6 @@ static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const cha
|
|||
unsigned int reg;
|
||||
u8 btr;
|
||||
|
||||
/* save revision id to determine DMA capability */
|
||||
pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
|
||||
|
||||
/* force Master Latency Timer value to 64 PCICLKs */
|
||||
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
|
||||
|
||||
|
@ -315,7 +308,7 @@ static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const cha
|
|||
if (!(PCI_FUNC(dev->devfn) & 1))
|
||||
btr |= 0x2;
|
||||
else
|
||||
btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
|
||||
btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
|
||||
pci_write_config_byte(dev, 0x5A, btr);
|
||||
}
|
||||
/* Setup HT1000 SouthBridge Controller - Single Channel Only */
|
||||
|
|
|
@ -659,9 +659,7 @@ static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const c
|
|||
|
||||
/* Special case for SiS630 : 630S/ET is ATA_100a */
|
||||
if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
|
||||
u8 hostrev;
|
||||
pci_read_config_byte(host, PCI_REVISION_ID, &hostrev);
|
||||
if (hostrev >= 0x30)
|
||||
if (host->revision >= 0x30)
|
||||
chipset_family = ATA_100a;
|
||||
}
|
||||
pci_dev_put(host);
|
||||
|
@ -702,7 +700,6 @@ static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const c
|
|||
u16 trueid;
|
||||
u8 prefctl;
|
||||
u8 idecfg;
|
||||
u8 sbrev;
|
||||
|
||||
pci_read_config_byte(dev, 0x4a, &idecfg);
|
||||
pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
|
||||
|
@ -712,11 +709,10 @@ static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const c
|
|||
if (trueid == 0x5517) { /* SiS 961/961B */
|
||||
|
||||
lpc_bridge = pci_get_slot(dev->bus, 0x10); /* Bus 0, Dev 2, Fn 0 */
|
||||
pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev);
|
||||
pci_read_config_byte(dev, 0x49, &prefctl);
|
||||
pci_dev_put(lpc_bridge);
|
||||
|
||||
if (sbrev == 0x10 && (prefctl & 0x80)) {
|
||||
if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
|
||||
printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
|
||||
chipset_family = ATA_133a;
|
||||
} else {
|
||||
|
|
|
@ -338,7 +338,6 @@ static void sl82c105_tune_drive(ide_drive_t *drive, u8 pio)
|
|||
static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
|
||||
{
|
||||
struct pci_dev *bridge;
|
||||
u8 rev;
|
||||
|
||||
/*
|
||||
* The bridge should be part of the same device, but function 0.
|
||||
|
@ -360,10 +359,9 @@ static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
|
|||
/*
|
||||
* We need to find function 0's revision, not function 1
|
||||
*/
|
||||
pci_read_config_byte(bridge, PCI_REVISION_ID, &rev);
|
||||
pci_dev_put(bridge);
|
||||
|
||||
return rev;
|
||||
return bridge->revision;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -237,16 +237,14 @@ static int via82cxxx_ide_dma_check (ide_drive_t *drive)
|
|||
static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
|
||||
{
|
||||
struct via_isa_bridge *via_config;
|
||||
u8 t;
|
||||
|
||||
for (via_config = via_isa_bridges; via_config->id; via_config++)
|
||||
if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
|
||||
!!(via_config->flags & VIA_BAD_ID),
|
||||
via_config->id, NULL))) {
|
||||
|
||||
pci_read_config_byte(*isa, PCI_REVISION_ID, &t);
|
||||
if (t >= via_config->rev_min &&
|
||||
t <= via_config->rev_max)
|
||||
if ((*isa)->revision >= via_config->rev_min &&
|
||||
(*isa)->revision <= via_config->rev_max)
|
||||
break;
|
||||
pci_dev_put(*isa);
|
||||
}
|
||||
|
@ -404,10 +402,9 @@ static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev *dev, const
|
|||
* Print the boot message.
|
||||
*/
|
||||
|
||||
pci_read_config_byte(isa, PCI_REVISION_ID, &t);
|
||||
printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %sDMA%s "
|
||||
"controller on pci%s\n",
|
||||
via_config->name, t,
|
||||
via_config->name, isa->revision,
|
||||
via_config->udma_mask ? "U" : "MW",
|
||||
via_dma[via_config->udma_mask ?
|
||||
(fls(via_config->udma_mask) - 1) : 0],
|
||||
|
|
|
@ -270,7 +270,6 @@ static int __devinit ipath_init_one(struct pci_dev *pdev,
|
|||
struct ipath_devdata *dd;
|
||||
unsigned long long addr;
|
||||
u32 bar0 = 0, bar1 = 0;
|
||||
u8 rev;
|
||||
|
||||
dd = ipath_alloc_devdata(pdev);
|
||||
if (IS_ERR(dd)) {
|
||||
|
@ -432,13 +431,7 @@ static int __devinit ipath_init_one(struct pci_dev *pdev,
|
|||
dd->ipath_deviceid = ent->device; /* save for later use */
|
||||
dd->ipath_vendorid = ent->vendor;
|
||||
|
||||
ret = pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
|
||||
if (ret) {
|
||||
ipath_dev_err(dd, "Failed to read PCI revision ID unit "
|
||||
"%u: err %d\n", dd->ipath_unit, -ret);
|
||||
goto bail_regions; /* shouldn't ever happen */
|
||||
}
|
||||
dd->ipath_pcirev = rev;
|
||||
dd->ipath_pcirev = pdev->revision;
|
||||
|
||||
#if defined(__powerpc__)
|
||||
/* There isn't a generic way to specify writethrough mappings */
|
||||
|
|
|
@ -287,7 +287,6 @@ setup_sct_quadro(struct IsdnCard *card)
|
|||
#ifdef CONFIG_PCI
|
||||
struct IsdnCardState *cs = card->cs;
|
||||
char tmp[64];
|
||||
u_char pci_rev_id;
|
||||
u_int found = 0;
|
||||
u_int pci_ioaddr1, pci_ioaddr2, pci_ioaddr3, pci_ioaddr4, pci_ioaddr5;
|
||||
|
||||
|
@ -335,8 +334,7 @@ setup_sct_quadro(struct IsdnCard *card)
|
|||
}
|
||||
#ifdef ATTEMPT_PCI_REMAPPING
|
||||
/* HACK: PLX revision 1 bug: PLX address bit 7 must not be set */
|
||||
pci_read_config_byte(dev_a8, PCI_REVISION_ID, &pci_rev_id);
|
||||
if ((pci_ioaddr1 & 0x80) && (pci_rev_id == 1)) {
|
||||
if ((pci_ioaddr1 & 0x80) && (dev_a8->revision == 1)) {
|
||||
printk(KERN_WARNING "HiSax: %s (%s): PLX rev 1, remapping required!\n",
|
||||
CardType[card->typ],
|
||||
sct_quadro_subtypes[cs->subtyp]);
|
||||
|
|
|
@ -94,7 +94,6 @@ struct gemtek_pci_card {
|
|||
|
||||
u32 iobase;
|
||||
u32 length;
|
||||
u8 chiprev;
|
||||
u16 model;
|
||||
|
||||
u32 current_frequency;
|
||||
|
@ -415,7 +414,6 @@ static int __devinit gemtek_pci_probe( struct pci_dev *pci_dev, const struct pci
|
|||
goto err_pci;
|
||||
}
|
||||
|
||||
pci_read_config_byte( pci_dev, PCI_REVISION_ID, &card->chiprev );
|
||||
pci_read_config_word( pci_dev, PCI_SUBSYSTEM_ID, &card->model );
|
||||
|
||||
pci_set_drvdata( pci_dev, card );
|
||||
|
@ -436,7 +434,7 @@ static int __devinit gemtek_pci_probe( struct pci_dev *pci_dev, const struct pci
|
|||
gemtek_pci_mute( card );
|
||||
|
||||
printk( KERN_INFO "Gemtek PCI Radio (rev. %d) found at 0x%04x-0x%04x.\n",
|
||||
card->chiprev, card->iobase, card->iobase + card->length - 1 );
|
||||
pci_dev->revision, card->iobase, card->iobase + card->length - 1 );
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
|
@ -1809,7 +1809,6 @@ static int __devinit meye_probe(struct pci_dev *pcidev,
|
|||
{
|
||||
int ret = -EBUSY;
|
||||
unsigned long mchip_adr;
|
||||
u8 revision;
|
||||
|
||||
if (meye.mchip_dev != NULL) {
|
||||
printk(KERN_ERR "meye: only one device allowed!\n");
|
||||
|
@ -1885,7 +1884,6 @@ static int __devinit meye_probe(struct pci_dev *pcidev,
|
|||
goto outreqirq;
|
||||
}
|
||||
|
||||
pci_read_config_byte(meye.mchip_dev, PCI_REVISION_ID, &revision);
|
||||
pci_write_config_byte(meye.mchip_dev, PCI_CACHE_LINE_SIZE, 8);
|
||||
pci_write_config_byte(meye.mchip_dev, PCI_LATENCY_TIMER, 64);
|
||||
|
||||
|
@ -1939,7 +1937,7 @@ static int __devinit meye_probe(struct pci_dev *pcidev,
|
|||
printk(KERN_INFO "meye: Motion Eye Camera Driver v%s.\n",
|
||||
MEYE_DRIVER_VERSION);
|
||||
printk(KERN_INFO "meye: mchip KL5A72002 rev. %d, base %lx, irq %d\n",
|
||||
revision, mchip_adr, meye.mchip_irq);
|
||||
meye.mchip_dev->revision, mchip_adr, meye.mchip_irq);
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
|
@ -1799,7 +1799,6 @@ static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
void __iomem *regs;
|
||||
resource_size_t pciaddr;
|
||||
unsigned int addr_len, i, pci_using_dac;
|
||||
u8 pci_rev;
|
||||
|
||||
#ifndef MODULE
|
||||
static int version_printed;
|
||||
|
@ -1807,13 +1806,11 @@ static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
printk("%s", version);
|
||||
#endif
|
||||
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
|
||||
|
||||
if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
|
||||
pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) {
|
||||
pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
|
||||
dev_err(&pdev->dev,
|
||||
"This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
|
||||
pdev->vendor, pdev->device, pci_rev);
|
||||
pdev->vendor, pdev->device, pdev->revision);
|
||||
dev_err(&pdev->dev, "Try the \"8139too\" driver instead.\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
|
|
@ -931,7 +931,6 @@ static int __devinit rtl8139_init_one (struct pci_dev *pdev,
|
|||
int i, addr_len, option;
|
||||
void __iomem *ioaddr;
|
||||
static int board_idx = -1;
|
||||
u8 pci_rev;
|
||||
|
||||
assert (pdev != NULL);
|
||||
assert (ent != NULL);
|
||||
|
@ -949,13 +948,11 @@ static int __devinit rtl8139_init_one (struct pci_dev *pdev,
|
|||
}
|
||||
#endif
|
||||
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
|
||||
|
||||
if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
|
||||
pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
|
||||
pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
|
||||
dev_info(&pdev->dev,
|
||||
"This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
|
||||
pdev->vendor, pdev->device, pci_rev);
|
||||
pdev->vendor, pdev->device, pdev->revision);
|
||||
dev_info(&pdev->dev,
|
||||
"Use the \"8139cp\" driver for improved performance and stability.\n");
|
||||
}
|
||||
|
|
|
@ -210,7 +210,6 @@ struct atl1_hw {
|
|||
u16 phy_spd_default;
|
||||
|
||||
u16 dev_rev;
|
||||
u8 revision_id;
|
||||
|
||||
/* spi flash */
|
||||
u8 flash_vendor;
|
||||
|
|
|
@ -118,10 +118,6 @@ static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
|
|||
{
|
||||
struct atl1_hw *hw = &adapter->hw;
|
||||
struct net_device *netdev = adapter->netdev;
|
||||
struct pci_dev *pdev = adapter->pdev;
|
||||
|
||||
/* PCI config space info */
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
|
||||
|
||||
hw->max_frame_size = netdev->mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
|
||||
hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
|
||||
|
|
|
@ -6736,10 +6736,9 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
|
|||
while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
|
||||
PCI_DEVICE_ID_AMD_8132_BRIDGE,
|
||||
amd_8132))) {
|
||||
u8 rev;
|
||||
|
||||
pci_read_config_byte(amd_8132, PCI_REVISION_ID, &rev);
|
||||
if (rev >= 0x10 && rev <= 0x13) {
|
||||
if (amd_8132->revision >= 0x10 &&
|
||||
amd_8132->revision <= 0x13) {
|
||||
disable_msi = 1;
|
||||
pci_dev_put(amd_8132);
|
||||
break;
|
||||
|
|
|
@ -3422,21 +3422,19 @@ done:
|
|||
static void cas_check_pci_invariants(struct cas *cp)
|
||||
{
|
||||
struct pci_dev *pdev = cp->pdev;
|
||||
u8 rev;
|
||||
|
||||
cp->cas_flags = 0;
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
|
||||
if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
|
||||
(pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
|
||||
if (rev >= CAS_ID_REVPLUS)
|
||||
if (pdev->revision >= CAS_ID_REVPLUS)
|
||||
cp->cas_flags |= CAS_FLAG_REG_PLUS;
|
||||
if (rev < CAS_ID_REVPLUS02u)
|
||||
if (pdev->revision < CAS_ID_REVPLUS02u)
|
||||
cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
|
||||
|
||||
/* Original Cassini supports HW CSUM, but it's not
|
||||
* enabled by default as it can trigger TX hangs.
|
||||
*/
|
||||
if (rev < CAS_ID_REV2)
|
||||
if (pdev->revision < CAS_ID_REV2)
|
||||
cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
|
||||
} else {
|
||||
/* Only sun has original cassini chips. */
|
||||
|
@ -4919,13 +4917,13 @@ static int __devinit cas_init_one(struct pci_dev *pdev,
|
|||
pci_cmd &= ~PCI_COMMAND_SERR;
|
||||
pci_cmd |= PCI_COMMAND_PARITY;
|
||||
pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
|
||||
if (pci_set_mwi(pdev))
|
||||
if (pci_try_set_mwi(pdev))
|
||||
printk(KERN_WARNING PFX "Could not enable MWI for %s\n",
|
||||
pci_name(pdev));
|
||||
|
||||
/*
|
||||
* On some architectures, the default cache line size set
|
||||
* by pci_set_mwi reduces perforamnce. We have to increase
|
||||
* by pci_try_set_mwi reduces perforamnce. We have to increase
|
||||
* it for this case. To start, we'll print some configuration
|
||||
* data.
|
||||
*/
|
||||
|
|
|
@ -250,7 +250,6 @@ rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
np->an_enable = 1;
|
||||
mii_set_media (dev);
|
||||
}
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &np->pci_rev_id);
|
||||
|
||||
err = register_netdev (dev);
|
||||
if (err)
|
||||
|
@ -879,7 +878,7 @@ receive_packet (struct net_device *dev)
|
|||
skb->protocol = eth_type_trans (skb, dev);
|
||||
#if 0
|
||||
/* Checksum done by hw, but csum value unavailable. */
|
||||
if (np->pci_rev_id >= 0x0c &&
|
||||
if (np->pdev->pci_rev_id >= 0x0c &&
|
||||
!(frame_status & (TCPError | UDPError | IPError))) {
|
||||
skb->ip_summed = CHECKSUM_UNNECESSARY;
|
||||
}
|
||||
|
|
|
@ -668,7 +668,6 @@ struct netdev_private {
|
|||
unsigned int rx_flow:1; /* Rx flow control enable */
|
||||
unsigned int phy_media:1; /* 1: fiber, 0: copper */
|
||||
unsigned int link_status:1; /* Current link status */
|
||||
unsigned char pci_rev_id; /* PCI revision ID */
|
||||
struct netdev_desc *last_tx; /* Last Tx descriptor used. */
|
||||
unsigned long cur_rx, old_rx; /* Producer/consumer ring indices */
|
||||
unsigned long cur_tx, old_tx;
|
||||
|
|
|
@ -583,7 +583,6 @@ struct nic {
|
|||
u32 rx_tco_frames;
|
||||
u32 rx_over_length_errors;
|
||||
|
||||
u8 rev_id;
|
||||
u16 leds;
|
||||
u16 eeprom_wc;
|
||||
u16 eeprom[256];
|
||||
|
@ -937,9 +936,8 @@ static void e100_get_defaults(struct nic *nic)
|
|||
struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
|
||||
struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
|
||||
|
||||
pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);
|
||||
/* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
|
||||
nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->rev_id;
|
||||
nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;
|
||||
if(nic->mac == mac_unknown)
|
||||
nic->mac = mac_82557_D100_A;
|
||||
|
||||
|
@ -1279,7 +1277,7 @@ static void e100_setup_ucode(struct nic *nic, struct cb *cb, struct sk_buff *skb
|
|||
if (nic->flags & ich)
|
||||
goto noloaducode;
|
||||
|
||||
/* Search for ucode match against h/w rev_id */
|
||||
/* Search for ucode match against h/w revision */
|
||||
for (opts = ucode_opts; opts->mac; opts++) {
|
||||
int i;
|
||||
u32 *ucode = opts->ucode;
|
||||
|
@ -2238,7 +2236,7 @@ static void e100_get_regs(struct net_device *netdev,
|
|||
u32 *buff = p;
|
||||
int i;
|
||||
|
||||
regs->version = (1 << 24) | nic->rev_id;
|
||||
regs->version = (1 << 24) | nic->pdev->revision;
|
||||
buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
|
||||
ioread8(&nic->csr->scb.cmd_lo) << 16 |
|
||||
ioread16(&nic->csr->scb.status);
|
||||
|
|
|
@ -1266,8 +1266,7 @@ e1000_sw_init(struct e1000_adapter *adapter)
|
|||
hw->device_id = pdev->device;
|
||||
hw->subsystem_vendor_id = pdev->subsystem_vendor;
|
||||
hw->subsystem_id = pdev->subsystem_device;
|
||||
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
|
||||
hw->revision_id = pdev->revision;
|
||||
|
||||
pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
|
||||
|
||||
|
|
|
@ -5084,15 +5084,13 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
|
|||
np->wolenabled = 0;
|
||||
|
||||
if (id->driver_data & DEV_HAS_POWER_CNTRL) {
|
||||
u8 revision_id;
|
||||
pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
|
||||
|
||||
/* take phy and nic out of low power mode */
|
||||
powerstate = readl(base + NvRegPowerState2);
|
||||
powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
|
||||
if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
|
||||
id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
|
||||
revision_id >= 0xA3)
|
||||
pci_dev->revision >= 0xA3)
|
||||
powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
|
||||
writel(powerstate, base + NvRegPowerState2);
|
||||
}
|
||||
|
|
|
@ -54,8 +54,6 @@ static char netxen_nic_driver_string[] = "NetXen Network Driver version "
|
|||
#define NETXEN_ADAPTER_UP_MAGIC 777
|
||||
#define NETXEN_NIC_PEG_TUNE 0
|
||||
|
||||
u8 nx_p2_id = NX_P2_C0;
|
||||
|
||||
#define DMA_32BIT_MASK 0x00000000ffffffffULL
|
||||
#define DMA_35BIT_MASK 0x00000007ffffffffULL
|
||||
|
||||
|
@ -307,8 +305,7 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
goto err_out_disable_pdev;
|
||||
|
||||
pci_set_master(pdev);
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &nx_p2_id);
|
||||
if (nx_p2_id == NX_P2_C1 &&
|
||||
if (pdev->revision == NX_P2_C1 &&
|
||||
(pci_set_dma_mask(pdev, DMA_35BIT_MASK) == 0) &&
|
||||
(pci_set_consistent_dma_mask(pdev, DMA_35BIT_MASK) == 0)) {
|
||||
pci_using_dac = 1;
|
||||
|
@ -552,7 +549,7 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
INIT_WORK(&adapter->watchdog_task, netxen_watchdog_task);
|
||||
adapter->ahw.pdev = pdev;
|
||||
adapter->proc_cmd_buf_counter = 0;
|
||||
adapter->ahw.revision_id = nx_p2_id;
|
||||
adapter->ahw.revision_id = pdev->revision;
|
||||
|
||||
/* make sure Window == 1 */
|
||||
netxen_nic_pci_change_crbwindow(adapter, 1);
|
||||
|
|
|
@ -1135,7 +1135,7 @@ static int init_nic(struct s2io_nic *nic)
|
|||
* SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
|
||||
*/
|
||||
if ((nic->device_type == XFRAME_I_DEVICE) &&
|
||||
(get_xena_rev_id(nic->pdev) < 4))
|
||||
(nic->pdev->revision < 4))
|
||||
writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
|
||||
|
||||
val64 = readq(&bar0->tx_fifo_partition_0);
|
||||
|
@ -1873,7 +1873,7 @@ static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
|
|||
herc = (sp->device_type == XFRAME_II_DEVICE);
|
||||
|
||||
if (flag == FALSE) {
|
||||
if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
|
||||
if ((!herc && (sp->pdev->revision >= 4)) || herc) {
|
||||
if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
|
||||
ret = 1;
|
||||
} else {
|
||||
|
@ -1881,7 +1881,7 @@ static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
|
|||
ret = 1;
|
||||
}
|
||||
} else {
|
||||
if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
|
||||
if ((!herc && (sp->pdev->revision >= 4)) || herc) {
|
||||
if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
|
||||
ADAPTER_STATUS_RMAC_PCC_IDLE))
|
||||
ret = 1;
|
||||
|
@ -7075,23 +7075,6 @@ static void s2io_link(struct s2io_nic * sp, int link)
|
|||
sp->start_time = jiffies;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_xena_rev_id - to identify revision ID of xena.
|
||||
* @pdev : PCI Dev structure
|
||||
* Description:
|
||||
* Function to identify the Revision ID of xena.
|
||||
* Return value:
|
||||
* returns the revision ID of the device.
|
||||
*/
|
||||
|
||||
static int get_xena_rev_id(struct pci_dev *pdev)
|
||||
{
|
||||
u8 id = 0;
|
||||
int ret;
|
||||
ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
|
||||
return id;
|
||||
}
|
||||
|
||||
/**
|
||||
* s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
|
||||
* @sp : private member of the device structure, which is a pointer to the
|
||||
|
@ -7550,7 +7533,7 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
|
|||
s2io_vpd_read(sp);
|
||||
DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
|
||||
DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
|
||||
sp->product_name, get_xena_rev_id(sp->pdev));
|
||||
sp->product_name, pdev->revision);
|
||||
DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
|
||||
s2io_driver_version);
|
||||
DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
|
||||
|
|
|
@ -1033,7 +1033,6 @@ static void s2io_set_link(struct work_struct *work);
|
|||
static int s2io_set_swapper(struct s2io_nic * sp);
|
||||
static void s2io_card_down(struct s2io_nic *nic);
|
||||
static int s2io_card_up(struct s2io_nic *nic);
|
||||
static int get_xena_rev_id(struct pci_dev *pdev);
|
||||
static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
|
||||
int bit_state);
|
||||
static int s2io_add_isr(struct s2io_nic * sp);
|
||||
|
|
|
@ -740,7 +740,7 @@ static int __devinit starfire_init_one(struct pci_dev *pdev,
|
|||
pci_set_master(pdev);
|
||||
|
||||
/* enable MWI -- it vastly improves Rx performance on sparc64 */
|
||||
pci_set_mwi(pdev);
|
||||
pci_try_set_mwi(pdev);
|
||||
|
||||
#ifdef ZEROCOPY
|
||||
/* Starfire can do TCP/UDP checksumming */
|
||||
|
|
|
@ -397,7 +397,6 @@ struct netdev_private {
|
|||
unsigned char phys[MII_CNT]; /* MII device addresses, only first one used. */
|
||||
struct pci_dev *pci_dev;
|
||||
void __iomem *base;
|
||||
unsigned char pci_rev_id;
|
||||
};
|
||||
|
||||
/* The station address location in the EEPROM. */
|
||||
|
@ -544,8 +543,6 @@ static int __devinit sundance_probe1 (struct pci_dev *pdev,
|
|||
dev->change_mtu = &change_mtu;
|
||||
pci_set_drvdata(pdev, dev);
|
||||
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &np->pci_rev_id);
|
||||
|
||||
i = register_netdev(dev);
|
||||
if (i)
|
||||
goto err_out_unmap_rx;
|
||||
|
@ -828,7 +825,7 @@ static int netdev_open(struct net_device *dev)
|
|||
iowrite8(100, ioaddr + RxDMAPollPeriod);
|
||||
iowrite8(127, ioaddr + TxDMAPollPeriod);
|
||||
/* Fix DFE-580TX packet drop issue */
|
||||
if (np->pci_rev_id >= 0x14)
|
||||
if (np->pci_dev->revision >= 0x14)
|
||||
iowrite8(0x01, ioaddr + DebugCtrl1);
|
||||
netif_start_queue(dev);
|
||||
|
||||
|
@ -1194,7 +1191,7 @@ static irqreturn_t intr_handler(int irq, void *dev_instance)
|
|||
hw_frame_id = ioread8(ioaddr + TxFrameId);
|
||||
}
|
||||
|
||||
if (np->pci_rev_id >= 0x14) {
|
||||
if (np->pci_dev->revision >= 0x14) {
|
||||
spin_lock(&np->lock);
|
||||
for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
|
||||
int entry = np->dirty_tx % TX_RING_SIZE;
|
||||
|
|
|
@ -3095,12 +3095,8 @@ static int __devinit happy_meal_pci_probe(struct pci_dev *pdev,
|
|||
|
||||
#ifdef CONFIG_SPARC
|
||||
hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
|
||||
if (hp->hm_revision == 0xff) {
|
||||
unsigned char prev;
|
||||
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &prev);
|
||||
hp->hm_revision = 0xc0 | (prev & 0x0f);
|
||||
}
|
||||
if (hp->hm_revision == 0xff)
|
||||
hp->hm_revision = 0xc0 | (pdev->revision & 0x0f);
|
||||
#else
|
||||
/* works with this on non-sparc hosts */
|
||||
hp->hm_revision = 0x20;
|
||||
|
|
|
@ -10551,11 +10551,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
|
|||
continue;
|
||||
}
|
||||
if (pci_id->rev != PCI_ANY_ID) {
|
||||
u8 rev;
|
||||
|
||||
pci_read_config_byte(bridge, PCI_REVISION_ID,
|
||||
&rev);
|
||||
if (rev > pci_id->rev)
|
||||
if (bridge->revision > pci_id->rev)
|
||||
continue;
|
||||
}
|
||||
if (bridge->subordinate &&
|
||||
|
|
|
@ -533,7 +533,6 @@ static int __devinit TLan_probe1(struct pci_dev *pdev,
|
|||
|
||||
struct net_device *dev;
|
||||
TLanPrivateInfo *priv;
|
||||
u8 pci_rev;
|
||||
u16 device_id;
|
||||
int reg, rc = -ENODEV;
|
||||
|
||||
|
@ -577,8 +576,6 @@ static int __devinit TLan_probe1(struct pci_dev *pdev,
|
|||
goto err_out_free_dev;
|
||||
}
|
||||
|
||||
pci_read_config_byte ( pdev, PCI_REVISION_ID, &pci_rev);
|
||||
|
||||
for ( reg= 0; reg <= 5; reg ++ ) {
|
||||
if (pci_resource_flags(pdev, reg) & IORESOURCE_IO) {
|
||||
pci_io_base = pci_resource_start(pdev, reg);
|
||||
|
@ -595,7 +592,7 @@ static int __devinit TLan_probe1(struct pci_dev *pdev,
|
|||
|
||||
dev->base_addr = pci_io_base;
|
||||
dev->irq = pdev->irq;
|
||||
priv->adapterRev = pci_rev;
|
||||
priv->adapterRev = pdev->revision;
|
||||
pci_set_master(pdev);
|
||||
pci_set_drvdata(pdev, dev);
|
||||
|
||||
|
|
|
@ -2134,7 +2134,7 @@ srom_search(struct net_device *dev, struct pci_dev *pdev)
|
|||
u_short vendor, status;
|
||||
u_int irq = 0, device;
|
||||
u_long iobase = 0; /* Clear upper 32 bits in Alphas */
|
||||
int i, j, cfrv;
|
||||
int i, j;
|
||||
struct de4x5_private *lp = netdev_priv(dev);
|
||||
struct list_head *walk;
|
||||
|
||||
|
@ -2150,7 +2150,6 @@ srom_search(struct net_device *dev, struct pci_dev *pdev)
|
|||
|
||||
/* Get the chip configuration revision register */
|
||||
pb = this_dev->bus->number;
|
||||
pci_read_config_dword(this_dev, PCI_REVISION_ID, &cfrv);
|
||||
|
||||
/* Set the device number information */
|
||||
lp->device = PCI_SLOT(this_dev->devfn);
|
||||
|
@ -2158,7 +2157,8 @@ srom_search(struct net_device *dev, struct pci_dev *pdev)
|
|||
|
||||
/* Set the chipset information */
|
||||
if (is_DC2114x) {
|
||||
device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
|
||||
device = ((this_dev->revision & CFRV_RN) < DC2114x_BRK
|
||||
? DC21142 : DC21143);
|
||||
}
|
||||
lp->chipset = device;
|
||||
|
||||
|
@ -2254,7 +2254,7 @@ static int __devinit de4x5_pci_probe (struct pci_dev *pdev,
|
|||
}
|
||||
|
||||
/* Get the chip configuration revision register */
|
||||
pci_read_config_dword(pdev, PCI_REVISION_ID, &lp->cfrv);
|
||||
lp->cfrv = pdev->revision;
|
||||
|
||||
/* Set the device number information */
|
||||
lp->device = dev_num;
|
||||
|
|
|
@ -181,11 +181,12 @@
|
|||
udelay(5);
|
||||
|
||||
#define __CHK_IO_SIZE(pci_id, dev_rev) \
|
||||
(( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? \
|
||||
(( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
|
||||
DM9102A_IO_SIZE: DM9102_IO_SIZE)
|
||||
|
||||
#define CHK_IO_SIZE(pci_dev, dev_rev) \
|
||||
(__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev))
|
||||
#define CHK_IO_SIZE(pci_dev) \
|
||||
(__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, \
|
||||
(pci_dev)->revision))
|
||||
|
||||
/* Sten Check */
|
||||
#define DEVICE net_device
|
||||
|
@ -205,7 +206,7 @@ struct rx_desc {
|
|||
|
||||
struct dmfe_board_info {
|
||||
u32 chip_id; /* Chip vendor/Device ID */
|
||||
u32 chip_revision; /* Chip revision */
|
||||
u8 chip_revision; /* Chip revision */
|
||||
struct DEVICE *next_dev; /* next device */
|
||||
struct pci_dev *pdev; /* PCI device */
|
||||
spinlock_t lock;
|
||||
|
@ -359,7 +360,7 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
|
|||
{
|
||||
struct dmfe_board_info *db; /* board information structure */
|
||||
struct net_device *dev;
|
||||
u32 dev_rev, pci_pmr;
|
||||
u32 pci_pmr;
|
||||
int i, err;
|
||||
|
||||
DMFE_DBUG(0, "dmfe_init_one()", 0);
|
||||
|
@ -392,10 +393,7 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
|
|||
goto err_out_disable;
|
||||
}
|
||||
|
||||
/* Read Chip revision */
|
||||
pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
|
||||
|
||||
if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev, dev_rev)) ) {
|
||||
if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev)) ) {
|
||||
printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
|
||||
err = -ENODEV;
|
||||
goto err_out_disable;
|
||||
|
@ -433,7 +431,7 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
|
|||
|
||||
db->chip_id = ent->driver_data;
|
||||
db->ioaddr = pci_resource_start(pdev, 0);
|
||||
db->chip_revision = dev_rev;
|
||||
db->chip_revision = pdev->revision;
|
||||
db->wol_mode = 0;
|
||||
|
||||
db->pdev = pdev;
|
||||
|
@ -455,7 +453,7 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
|
|||
|
||||
pci_read_config_dword(pdev, 0x50, &pci_pmr);
|
||||
pci_pmr &= 0x70000;
|
||||
if ( (pci_pmr == 0x10000) && (dev_rev == 0x02000031) )
|
||||
if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) )
|
||||
db->chip_type = 1; /* DM9102A E3 */
|
||||
else
|
||||
db->chip_type = 0;
|
||||
|
@ -553,7 +551,7 @@ static int dmfe_open(struct DEVICE *dev)
|
|||
|
||||
/* CR6 operation mode decision */
|
||||
if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
|
||||
(db->chip_revision >= 0x02000030) ) {
|
||||
(db->chip_revision >= 0x30) ) {
|
||||
db->cr6_data |= DMFE_TXTH_256;
|
||||
db->cr0_data = CR0_DEFAULT;
|
||||
db->dm910x_chk_mode=4; /* Enter the normal mode */
|
||||
|
@ -1199,9 +1197,9 @@ static void dmfe_timer(unsigned long data)
|
|||
tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
|
||||
|
||||
if ( ((db->chip_id == PCI_DM9102_ID) &&
|
||||
(db->chip_revision == 0x02000030)) ||
|
||||
(db->chip_revision == 0x30)) ||
|
||||
((db->chip_id == PCI_DM9132_ID) &&
|
||||
(db->chip_revision == 0x02000010)) ) {
|
||||
(db->chip_revision == 0x10)) ) {
|
||||
/* DM9102A Chip */
|
||||
if (tmp_cr12 & 2)
|
||||
link_ok = 0;
|
||||
|
|
|
@ -1155,7 +1155,7 @@ static void __devinit tulip_mwi_config (struct pci_dev *pdev,
|
|||
/* set or disable MWI in the standard PCI command bit.
|
||||
* Check for the case where mwi is desired but not available
|
||||
*/
|
||||
if (csr0 & MWI) pci_set_mwi(pdev);
|
||||
if (csr0 & MWI) pci_try_set_mwi(pdev);
|
||||
else pci_clear_mwi(pdev);
|
||||
|
||||
/* read result from hardware (in case bit refused to enable) */
|
||||
|
@ -1238,7 +1238,6 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
|
|||
};
|
||||
static int last_irq;
|
||||
static int multiport_cnt; /* For four-port boards w/one EEPROM */
|
||||
u8 chip_rev;
|
||||
int i, irq;
|
||||
unsigned short sum;
|
||||
unsigned char *ee_data;
|
||||
|
@ -1274,10 +1273,8 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
|
|||
|
||||
if (pdev->vendor == 0x1282 && pdev->device == 0x9100)
|
||||
{
|
||||
u32 dev_rev;
|
||||
/* Read Chip revision */
|
||||
pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
|
||||
if(dev_rev < 0x02000030)
|
||||
if (pdev->revision < 0x02000030)
|
||||
{
|
||||
printk(KERN_ERR PFX "skipping early DM9100 with Crc bug (use dmfe)\n");
|
||||
return -ENODEV;
|
||||
|
@ -1360,8 +1357,6 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
|
|||
if (!ioaddr)
|
||||
goto err_out_free_res;
|
||||
|
||||
pci_read_config_byte (pdev, PCI_REVISION_ID, &chip_rev);
|
||||
|
||||
/*
|
||||
* initialize private data structure 'tp'
|
||||
* it is zeroed and aligned in alloc_etherdev
|
||||
|
@ -1382,7 +1377,7 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
|
|||
tp->flags = tulip_tbl[chip_idx].flags;
|
||||
tp->pdev = pdev;
|
||||
tp->base_addr = ioaddr;
|
||||
tp->revision = chip_rev;
|
||||
tp->revision = pdev->revision;
|
||||
tp->csr0 = csr0;
|
||||
spin_lock_init(&tp->lock);
|
||||
spin_lock_init(&tp->mii_lock);
|
||||
|
@ -1399,7 +1394,7 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
|
|||
tulip_mwi_config (pdev, dev);
|
||||
#else
|
||||
/* MWI is broken for DC21143 rev 65... */
|
||||
if (chip_idx == DC21143 && chip_rev == 65)
|
||||
if (chip_idx == DC21143 && pdev->revision == 65)
|
||||
tp->csr0 &= ~MWI;
|
||||
#endif
|
||||
|
||||
|
@ -1640,7 +1635,7 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
|
|||
#else
|
||||
"Port"
|
||||
#endif
|
||||
" %#llx,", dev->name, chip_name, chip_rev,
|
||||
" %#llx,", dev->name, chip_name, pdev->revision,
|
||||
(unsigned long long) pci_resource_start(pdev, TULIP_BAR));
|
||||
pci_set_drvdata(pdev, dev);
|
||||
|
||||
|
|
|
@ -205,7 +205,6 @@ static int __devinit xircom_probe(struct pci_dev *pdev, const struct pci_device_
|
|||
{
|
||||
struct net_device *dev = NULL;
|
||||
struct xircom_private *private;
|
||||
unsigned char chip_rev;
|
||||
unsigned long flags;
|
||||
unsigned short tmp16;
|
||||
enter("xircom_probe");
|
||||
|
@ -224,8 +223,6 @@ static int __devinit xircom_probe(struct pci_dev *pdev, const struct pci_device_
|
|||
pci_read_config_word (pdev,PCI_STATUS, &tmp16);
|
||||
pci_write_config_word (pdev, PCI_STATUS,tmp16);
|
||||
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &chip_rev);
|
||||
|
||||
if (!request_region(pci_resource_start(pdev, 0), 128, "xircom_cb")) {
|
||||
printk(KERN_ERR "xircom_probe: failed to allocate io-region\n");
|
||||
return -ENODEV;
|
||||
|
@ -286,7 +283,7 @@ static int __devinit xircom_probe(struct pci_dev *pdev, const struct pci_device_
|
|||
goto reg_fail;
|
||||
}
|
||||
|
||||
printk(KERN_INFO "%s: Xircom cardbus revision %i at irq %i \n", dev->name, chip_rev, pdev->irq);
|
||||
printk(KERN_INFO "%s: Xircom cardbus revision %i at irq %i \n", dev->name, pdev->revision, pdev->irq);
|
||||
/* start the transmitter to get a heartbeat */
|
||||
/* TODO: send 2 dummy packets here */
|
||||
transceiver_voodoo(private);
|
||||
|
|
|
@ -524,7 +524,6 @@ static int __devinit xircom_init_one(struct pci_dev *pdev, const struct pci_devi
|
|||
int chip_idx = id->driver_data;
|
||||
long ioaddr;
|
||||
int i;
|
||||
u8 chip_rev;
|
||||
|
||||
/* when built into the kernel, we only print version if device is found */
|
||||
#ifndef MODULE
|
||||
|
@ -620,9 +619,8 @@ static int __devinit xircom_init_one(struct pci_dev *pdev, const struct pci_devi
|
|||
if (register_netdev(dev))
|
||||
goto err_out_cleardev;
|
||||
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &chip_rev);
|
||||
printk(KERN_INFO "%s: %s rev %d at %#3lx,",
|
||||
dev->name, xircom_tbl[chip_idx].chip_name, chip_rev, ioaddr);
|
||||
dev->name, xircom_tbl[chip_idx].chip_name, pdev->revision, ioaddr);
|
||||
for (i = 0; i < 6; i++)
|
||||
printk("%c%2.2X", i ? ':' : ' ', dev->dev_addr[i]);
|
||||
printk(", IRQ %d.\n", dev->irq);
|
||||
|
|
|
@ -2267,12 +2267,6 @@ need_resume:
|
|||
typhoon_resume(pdev);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
static int
|
||||
typhoon_enable_wake(struct pci_dev *pdev, pci_power_t state, int enable)
|
||||
{
|
||||
return pci_enable_wake(pdev, state, enable);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int __devinit
|
||||
|
@ -2636,7 +2630,6 @@ static struct pci_driver typhoon_driver = {
|
|||
#ifdef CONFIG_PM
|
||||
.suspend = typhoon_suspend,
|
||||
.resume = typhoon_resume,
|
||||
.enable_wake = typhoon_enable_wake,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
|
@ -622,7 +622,6 @@ static int __devinit rhine_init_one(struct pci_dev *pdev,
|
|||
struct net_device *dev;
|
||||
struct rhine_private *rp;
|
||||
int i, rc;
|
||||
u8 pci_rev;
|
||||
u32 quirks;
|
||||
long pioaddr;
|
||||
long memaddr;
|
||||
|
@ -642,27 +641,25 @@ static int __devinit rhine_init_one(struct pci_dev *pdev,
|
|||
printk(version);
|
||||
#endif
|
||||
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
|
||||
|
||||
io_size = 256;
|
||||
phy_id = 0;
|
||||
quirks = 0;
|
||||
name = "Rhine";
|
||||
if (pci_rev < VTunknown0) {
|
||||
if (pdev->revision < VTunknown0) {
|
||||
quirks = rqRhineI;
|
||||
io_size = 128;
|
||||
}
|
||||
else if (pci_rev >= VT6102) {
|
||||
else if (pdev->revision >= VT6102) {
|
||||
quirks = rqWOL | rqForceReset;
|
||||
if (pci_rev < VT6105) {
|
||||
if (pdev->revision < VT6105) {
|
||||
name = "Rhine II";
|
||||
quirks |= rqStatusWBRace; /* Rhine-II exclusive */
|
||||
}
|
||||
else {
|
||||
phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */
|
||||
if (pci_rev >= VT6105_B0)
|
||||
if (pdev->revision >= VT6105_B0)
|
||||
quirks |= rq6patterns;
|
||||
if (pci_rev < VT6105M)
|
||||
if (pdev->revision < VT6105M)
|
||||
name = "Rhine III";
|
||||
else
|
||||
name = "Rhine III (Management Adapter)";
|
||||
|
|
|
@ -890,8 +890,7 @@ static void __devinit velocity_init_info(struct pci_dev *pdev,
|
|||
|
||||
static int __devinit velocity_get_pci_info(struct velocity_info *vptr, struct pci_dev *pdev)
|
||||
{
|
||||
if (pci_read_config_byte(pdev, PCI_REVISION_ID, &vptr->rev_id) < 0)
|
||||
return -EIO;
|
||||
vptr->rev_id = pdev->revision;
|
||||
|
||||
pci_set_master(pdev);
|
||||
|
||||
|
|
|
@ -3439,7 +3439,6 @@ static int __devinit
|
|||
cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
static int first_time = 1;
|
||||
ucchar cpc_rev_id;
|
||||
int err, eeprom_outdated = 0;
|
||||
ucshort device_id;
|
||||
pc300_t *card;
|
||||
|
@ -3480,7 +3479,6 @@ cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
card->hw.falcsize = pci_resource_len(pdev, 4);
|
||||
card->hw.plxphys = pci_resource_start(pdev, 5);
|
||||
card->hw.plxsize = pci_resource_len(pdev, 5);
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &cpc_rev_id);
|
||||
|
||||
switch (device_id) {
|
||||
case PCI_DEVICE_ID_PC300_RX_1:
|
||||
|
@ -3498,7 +3496,7 @@ cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
}
|
||||
#ifdef PC300_DEBUG_PCI
|
||||
printk("cpc (bus=0x0%x,pci_id=0x%x,", pdev->bus->number, pdev->devfn);
|
||||
printk("rev_id=%d) IRQ%d\n", cpc_rev_id, card->hw.irq);
|
||||
printk("rev_id=%d) IRQ%d\n", pdev->revision, card->hw.irq);
|
||||
printk("cpc:found ramaddr=0x%08lx plxaddr=0x%08lx "
|
||||
"ctladdr=0x%08lx falcaddr=0x%08lx\n",
|
||||
card->hw.ramphys, card->hw.plxphys, card->hw.scaphys,
|
||||
|
|
|
@ -311,7 +311,6 @@ static int __devinit pc300_pci_init_one(struct pci_dev *pdev,
|
|||
const struct pci_device_id *ent)
|
||||
{
|
||||
card_t *card;
|
||||
u8 rev_id;
|
||||
u32 __iomem *p;
|
||||
int i;
|
||||
u32 ramsize;
|
||||
|
@ -366,7 +365,6 @@ static int __devinit pc300_pci_init_one(struct pci_dev *pdev,
|
|||
return -ENOMEM;
|
||||
}
|
||||
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
|
||||
if (pci_resource_len(pdev, 0) != PC300_PLX_SIZE ||
|
||||
pci_resource_len(pdev, 2) != PC300_SCA_SIZE ||
|
||||
pci_resource_len(pdev, 3) < 16384) {
|
||||
|
|
|
@ -289,7 +289,6 @@ static int __devinit pci200_pci_init_one(struct pci_dev *pdev,
|
|||
const struct pci_device_id *ent)
|
||||
{
|
||||
card_t *card;
|
||||
u8 rev_id;
|
||||
u32 __iomem *p;
|
||||
int i;
|
||||
u32 ramsize;
|
||||
|
@ -330,7 +329,6 @@ static int __devinit pci200_pci_init_one(struct pci_dev *pdev,
|
|||
return -ENOMEM;
|
||||
}
|
||||
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
|
||||
if (pci_resource_len(pdev, 0) != PCI200SYN_PLX_SIZE ||
|
||||
pci_resource_len(pdev, 2) != PCI200SYN_SCA_SIZE ||
|
||||
pci_resource_len(pdev, 3) < 16384) {
|
||||
|
|
|
@ -3741,10 +3741,8 @@ static int bcm43xx_attach_board(struct bcm43xx_private *bcm)
|
|||
&bcm->board_type);
|
||||
if (err)
|
||||
goto err_iounmap;
|
||||
err = bcm43xx_pci_read_config16(bcm, PCI_REVISION_ID,
|
||||
&bcm->board_revision);
|
||||
if (err)
|
||||
goto err_iounmap;
|
||||
|
||||
bcm->board_revision = bcm->pci_dev->revision;
|
||||
|
||||
err = bcm43xx_chipset_attach(bcm);
|
||||
if (err)
|
||||
|
|
|
@ -453,8 +453,6 @@ static struct pci_driver prism2_pci_drv_id = {
|
|||
.suspend = prism2_pci_suspend,
|
||||
.resume = prism2_pci_resume,
|
||||
#endif /* CONFIG_PM */
|
||||
/* Linux 2.4.6 added save_state and enable_wake that are not used here
|
||||
*/
|
||||
};
|
||||
|
||||
|
||||
|
|
|
@ -613,9 +613,6 @@ static struct pci_driver prism2_plx_drv_id = {
|
|||
.id_table = prism2_plx_id_table,
|
||||
.probe = prism2_plx_probe,
|
||||
.remove = prism2_plx_remove,
|
||||
.suspend = NULL,
|
||||
.resume = NULL,
|
||||
.enable_wake = NULL
|
||||
};
|
||||
|
||||
|
||||
|
|
|
@ -87,7 +87,6 @@ static struct pci_driver prism54_driver = {
|
|||
.remove = prism54_remove,
|
||||
.suspend = prism54_suspend,
|
||||
.resume = prism54_resume,
|
||||
/* .enable_wake ; we don't support this yet */
|
||||
};
|
||||
|
||||
/******************************************************************************
|
||||
|
@ -167,8 +166,7 @@ prism54_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
pci_set_master(pdev);
|
||||
|
||||
/* enable MWI */
|
||||
if (!pci_set_mwi(pdev))
|
||||
printk(KERN_INFO "%s: pci_set_mwi(pdev) succeeded\n", DRV_NAME);
|
||||
pci_try_set_mwi(pdev);
|
||||
|
||||
/* setup the network device interface and its structure */
|
||||
if (!(ndev = islpci_setup(pdev))) {
|
||||
|
|
|
@ -41,9 +41,7 @@ obj-$(CONFIG_ACPI) += pci-acpi.o
|
|||
# Cardbus & CompactPCI use setup-bus
|
||||
obj-$(CONFIG_HOTPLUG) += setup-bus.o
|
||||
|
||||
ifndef CONFIG_X86
|
||||
obj-y += syscall.o
|
||||
endif
|
||||
obj-$(CONFIG_PCI_SYSCALL) += syscall.o
|
||||
|
||||
ifeq ($(CONFIG_PCI_DEBUG),y)
|
||||
EXTRA_CFLAGS += -DDEBUG
|
||||
|
|
|
@ -211,6 +211,7 @@ typedef int (*acpiphp_callback)(struct acpiphp_slot *slot, void *data);
|
|||
|
||||
extern int acpiphp_enable_slot (struct acpiphp_slot *slot);
|
||||
extern int acpiphp_disable_slot (struct acpiphp_slot *slot);
|
||||
extern int acpiphp_eject_slot (struct acpiphp_slot *slot);
|
||||
extern u8 acpiphp_get_power_status (struct acpiphp_slot *slot);
|
||||
extern u8 acpiphp_get_attention_status (struct acpiphp_slot *slot);
|
||||
extern u8 acpiphp_get_latch_status (struct acpiphp_slot *slot);
|
||||
|
|
|
@ -156,11 +156,15 @@ static int enable_slot(struct hotplug_slot *hotplug_slot)
|
|||
static int disable_slot(struct hotplug_slot *hotplug_slot)
|
||||
{
|
||||
struct slot *slot = hotplug_slot->private;
|
||||
int retval;
|
||||
|
||||
dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
|
||||
|
||||
/* disable the specified slot */
|
||||
return acpiphp_disable_slot(slot->acpi_slot);
|
||||
retval = acpiphp_disable_slot(slot->acpi_slot);
|
||||
if (!retval)
|
||||
retval = acpiphp_eject_slot(slot->acpi_slot);
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -1282,7 +1282,7 @@ static unsigned int get_slot_status(struct acpiphp_slot *slot)
|
|||
/**
|
||||
* acpiphp_eject_slot - physically eject the slot
|
||||
*/
|
||||
static int acpiphp_eject_slot(struct acpiphp_slot *slot)
|
||||
int acpiphp_eject_slot(struct acpiphp_slot *slot)
|
||||
{
|
||||
acpi_status status;
|
||||
struct acpiphp_func *func;
|
||||
|
@ -1368,6 +1368,9 @@ static void program_hpp(struct pci_dev *dev, struct acpiphp_bridge *bridge)
|
|||
(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)))
|
||||
return;
|
||||
|
||||
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
|
||||
return;
|
||||
|
||||
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
|
||||
bridge->hpp.t0->cache_line_size);
|
||||
pci_write_config_byte(dev, PCI_LATENCY_TIMER,
|
||||
|
@ -1502,6 +1505,37 @@ static void handle_bridge_insertion(acpi_handle handle, u32 type)
|
|||
* ACPI event handlers
|
||||
*/
|
||||
|
||||
static acpi_status
|
||||
count_sub_bridges(acpi_handle handle, u32 lvl, void *context, void **rv)
|
||||
{
|
||||
int *count = (int *)context;
|
||||
struct acpiphp_bridge *bridge;
|
||||
|
||||
bridge = acpiphp_handle_to_bridge(handle);
|
||||
if (bridge)
|
||||
(*count)++;
|
||||
return AE_OK ;
|
||||
}
|
||||
|
||||
static acpi_status
|
||||
check_sub_bridges(acpi_handle handle, u32 lvl, void *context, void **rv)
|
||||
{
|
||||
struct acpiphp_bridge *bridge;
|
||||
char objname[64];
|
||||
struct acpi_buffer buffer = { .length = sizeof(objname),
|
||||
.pointer = objname };
|
||||
|
||||
bridge = acpiphp_handle_to_bridge(handle);
|
||||
if (bridge) {
|
||||
acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer);
|
||||
dbg("%s: re-enumerating slots under %s\n",
|
||||
__FUNCTION__, objname);
|
||||
acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer);
|
||||
acpiphp_check_bridge(bridge);
|
||||
}
|
||||
return AE_OK ;
|
||||
}
|
||||
|
||||
/**
|
||||
* handle_hotplug_event_bridge - handle ACPI event on bridges
|
||||
*
|
||||
|
@ -1519,6 +1553,7 @@ static void handle_hotplug_event_bridge(acpi_handle handle, u32 type, void *cont
|
|||
struct acpi_buffer buffer = { .length = sizeof(objname),
|
||||
.pointer = objname };
|
||||
struct acpi_device *device;
|
||||
int num_sub_bridges = 0;
|
||||
|
||||
if (acpi_bus_get_device(handle, &device)) {
|
||||
/* This bridge must have just been physically inserted */
|
||||
|
@ -1527,7 +1562,12 @@ static void handle_hotplug_event_bridge(acpi_handle handle, u32 type, void *cont
|
|||
}
|
||||
|
||||
bridge = acpiphp_handle_to_bridge(handle);
|
||||
if (!bridge) {
|
||||
if (type == ACPI_NOTIFY_BUS_CHECK) {
|
||||
acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, ACPI_UINT32_MAX,
|
||||
count_sub_bridges, &num_sub_bridges, NULL);
|
||||
}
|
||||
|
||||
if (!bridge && !num_sub_bridges) {
|
||||
err("cannot get bridge info\n");
|
||||
return;
|
||||
}
|
||||
|
@ -1538,7 +1578,14 @@ static void handle_hotplug_event_bridge(acpi_handle handle, u32 type, void *cont
|
|||
case ACPI_NOTIFY_BUS_CHECK:
|
||||
/* bus re-enumerate */
|
||||
dbg("%s: Bus check notify on %s\n", __FUNCTION__, objname);
|
||||
acpiphp_check_bridge(bridge);
|
||||
if (bridge) {
|
||||
dbg("%s: re-enumerating slots under %s\n",
|
||||
__FUNCTION__, objname);
|
||||
acpiphp_check_bridge(bridge);
|
||||
}
|
||||
if (num_sub_bridges)
|
||||
acpi_walk_namespace(ACPI_TYPE_DEVICE, handle,
|
||||
ACPI_UINT32_MAX, check_sub_bridges, NULL, NULL);
|
||||
break;
|
||||
|
||||
case ACPI_NOTIFY_DEVICE_CHECK:
|
||||
|
|
|
@ -35,6 +35,7 @@
|
|||
#include <linux/smp_lock.h>
|
||||
#include <asm/atomic.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/kthread.h>
|
||||
#include "cpci_hotplug.h"
|
||||
|
||||
#define DRIVER_AUTHOR "Scott Murray <scottm@somanetworks.com>"
|
||||
|
@ -59,9 +60,8 @@ static int slots;
|
|||
static atomic_t extracting;
|
||||
int cpci_debug;
|
||||
static struct cpci_hp_controller *controller;
|
||||
static struct semaphore event_semaphore; /* mutex for process loop (up if something to process) */
|
||||
static struct semaphore thread_exit; /* guard ensure thread has exited before calling it quits */
|
||||
static int thread_finished = 1;
|
||||
static struct task_struct *cpci_thread;
|
||||
static int thread_finished;
|
||||
|
||||
static int enable_slot(struct hotplug_slot *slot);
|
||||
static int disable_slot(struct hotplug_slot *slot);
|
||||
|
@ -357,9 +357,7 @@ cpci_hp_intr(int irq, void *data)
|
|||
controller->ops->disable_irq();
|
||||
|
||||
/* Trigger processing by the event thread */
|
||||
dbg("Signal event_semaphore");
|
||||
up(&event_semaphore);
|
||||
dbg("exited cpci_hp_intr");
|
||||
wake_up_process(cpci_thread);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
@ -521,17 +519,12 @@ event_thread(void *data)
|
|||
{
|
||||
int rc;
|
||||
|
||||
lock_kernel();
|
||||
daemonize("cpci_hp_eventd");
|
||||
unlock_kernel();
|
||||
|
||||
dbg("%s - event thread started", __FUNCTION__);
|
||||
while (1) {
|
||||
dbg("event thread sleeping");
|
||||
down_interruptible(&event_semaphore);
|
||||
dbg("event thread woken, thread_finished = %d",
|
||||
thread_finished);
|
||||
if (thread_finished || signal_pending(current))
|
||||
set_current_state(TASK_INTERRUPTIBLE);
|
||||
schedule();
|
||||
if (kthread_should_stop())
|
||||
break;
|
||||
do {
|
||||
rc = check_slots();
|
||||
|
@ -541,18 +534,17 @@ event_thread(void *data)
|
|||
} else if (rc < 0) {
|
||||
dbg("%s - error checking slots", __FUNCTION__);
|
||||
thread_finished = 1;
|
||||
break;
|
||||
goto out;
|
||||
}
|
||||
} while (atomic_read(&extracting) && !thread_finished);
|
||||
if (thread_finished)
|
||||
} while (atomic_read(&extracting) && !kthread_should_stop());
|
||||
if (kthread_should_stop())
|
||||
break;
|
||||
|
||||
/* Re-enable ENUM# interrupt */
|
||||
dbg("%s - re-enabling irq", __FUNCTION__);
|
||||
controller->ops->enable_irq();
|
||||
}
|
||||
dbg("%s - event thread signals exit", __FUNCTION__);
|
||||
up(&thread_exit);
|
||||
out:
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -562,12 +554,8 @@ poll_thread(void *data)
|
|||
{
|
||||
int rc;
|
||||
|
||||
lock_kernel();
|
||||
daemonize("cpci_hp_polld");
|
||||
unlock_kernel();
|
||||
|
||||
while (1) {
|
||||
if (thread_finished || signal_pending(current))
|
||||
if (kthread_should_stop() || signal_pending(current))
|
||||
break;
|
||||
if (controller->ops->query_enum()) {
|
||||
do {
|
||||
|
@ -578,48 +566,36 @@ poll_thread(void *data)
|
|||
} else if (rc < 0) {
|
||||
dbg("%s - error checking slots", __FUNCTION__);
|
||||
thread_finished = 1;
|
||||
break;
|
||||
goto out;
|
||||
}
|
||||
} while (atomic_read(&extracting) && !thread_finished);
|
||||
} while (atomic_read(&extracting) && !kthread_should_stop());
|
||||
}
|
||||
msleep(100);
|
||||
}
|
||||
dbg("poll thread signals exit");
|
||||
up(&thread_exit);
|
||||
out:
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
cpci_start_thread(void)
|
||||
{
|
||||
int pid;
|
||||
|
||||
/* initialize our semaphores */
|
||||
init_MUTEX_LOCKED(&event_semaphore);
|
||||
init_MUTEX_LOCKED(&thread_exit);
|
||||
thread_finished = 0;
|
||||
|
||||
if (controller->irq)
|
||||
pid = kernel_thread(event_thread, NULL, 0);
|
||||
cpci_thread = kthread_run(event_thread, NULL, "cpci_hp_eventd");
|
||||
else
|
||||
pid = kernel_thread(poll_thread, NULL, 0);
|
||||
if (pid < 0) {
|
||||
cpci_thread = kthread_run(poll_thread, NULL, "cpci_hp_polld");
|
||||
if (IS_ERR(cpci_thread)) {
|
||||
err("Can't start up our thread");
|
||||
return -1;
|
||||
return PTR_ERR(cpci_thread);
|
||||
}
|
||||
dbg("Our thread pid = %d", pid);
|
||||
thread_finished = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
cpci_stop_thread(void)
|
||||
{
|
||||
kthread_stop(cpci_thread);
|
||||
thread_finished = 1;
|
||||
dbg("thread finish command given");
|
||||
if (controller->irq)
|
||||
up(&event_semaphore);
|
||||
dbg("wait for thread to exit");
|
||||
down(&thread_exit);
|
||||
}
|
||||
|
||||
int
|
||||
|
|
|
@ -45,8 +45,6 @@ extern int cpci_debug;
|
|||
#define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME , ## arg)
|
||||
#define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n", MY_NAME , ## arg)
|
||||
|
||||
#define ROUND_UP(x, a) (((x) + (a) - 1) & ~((a) - 1))
|
||||
|
||||
|
||||
u8 cpci_get_attention_status(struct slot* slot)
|
||||
{
|
||||
|
|
|
@ -796,7 +796,6 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
u8 num_of_slots = 0;
|
||||
u8 hp_slot = 0;
|
||||
u8 device;
|
||||
u8 rev;
|
||||
u8 bus_cap;
|
||||
u16 temp_word;
|
||||
u16 vendor_id;
|
||||
|
@ -823,9 +822,8 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
}
|
||||
dbg("Vendor ID: %x\n", vendor_id);
|
||||
|
||||
rc = pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
|
||||
dbg("revision: %d\n", rev);
|
||||
if (rc || ((vendor_id == PCI_VENDOR_ID_COMPAQ) && (!rev))) {
|
||||
dbg("revision: %d\n", pdev->revision);
|
||||
if ((vendor_id == PCI_VENDOR_ID_COMPAQ) && (!pdev->revision)) {
|
||||
err(msg_HPC_rev_error);
|
||||
rc = -ENODEV;
|
||||
goto err_disable_device;
|
||||
|
@ -836,7 +834,7 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
* For Intel, each SSID bit identifies a PHP capability.
|
||||
* Also Intel HPC's may have RID=0.
|
||||
*/
|
||||
if ((rev > 2) || (vendor_id == PCI_VENDOR_ID_INTEL)) {
|
||||
if ((pdev->revision > 2) || (vendor_id == PCI_VENDOR_ID_INTEL)) {
|
||||
// TODO: This code can be made to support non-Compaq or Intel subsystem IDs
|
||||
rc = pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &subsystem_vid);
|
||||
if (rc) {
|
||||
|
@ -870,7 +868,7 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
|
||||
switch (subsystem_vid) {
|
||||
case PCI_VENDOR_ID_COMPAQ:
|
||||
if (rev >= 0x13) { /* CIOBX */
|
||||
if (pdev->revision >= 0x13) { /* CIOBX */
|
||||
ctrl->push_flag = 1;
|
||||
ctrl->slot_switch_type = 1;
|
||||
ctrl->push_button = 1;
|
||||
|
@ -1075,7 +1073,7 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
memcpy(ctrl->pci_bus, pdev->bus, sizeof(*ctrl->pci_bus));
|
||||
|
||||
ctrl->bus = pdev->bus->number;
|
||||
ctrl->rev = rev;
|
||||
ctrl->rev = pdev->revision;
|
||||
dbg("bus device function rev: %d %d %d %d\n", ctrl->bus,
|
||||
PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), ctrl->rev);
|
||||
|
||||
|
|
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