drm/amd/pp: Use dynamic gfx_clk rather than hardcoded values
Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Родитель
d10fb4a6f3
Коммит
21c77de356
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@ -383,7 +383,7 @@ static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
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static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr)
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{
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int result;
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uint32_t result;
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struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
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DpmClocks_t *table = &(smu10_data->clock_table);
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@ -429,11 +429,11 @@ static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr)
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency);
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result = smum_get_argument(hwmgr);
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smu10_data->gfx_min_freq_limit = result * 100;
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smu10_data->gfx_min_freq_limit = result / 10 * 1000;
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency);
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result = smum_get_argument(hwmgr);
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smu10_data->gfx_max_freq_limit = result * 100;
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smu10_data->gfx_max_freq_limit = result / 10 * 1000;
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return 0;
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}
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@ -515,6 +515,8 @@ static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
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static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
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enum amd_dpm_forced_level level)
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{
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struct smu10_hwmgr *data = hwmgr->backend;
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if (hwmgr->smu_version < 0x1E3700) {
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pr_info("smu firmware version too old, can not set dpm level\n");
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return 0;
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@ -525,7 +527,7 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
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case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetHardMinGfxClk,
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SMU10_UMD_PSTATE_PEAK_GFXCLK);
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data->gfx_max_freq_limit/100);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetHardMinFclkByFreq,
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SMU10_UMD_PSTATE_PEAK_FCLK);
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@ -538,7 +540,7 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetSoftMaxGfxClk,
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SMU10_UMD_PSTATE_PEAK_GFXCLK);
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data->gfx_max_freq_limit/100);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetSoftMaxFclkByFreq,
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SMU10_UMD_PSTATE_PEAK_FCLK);
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@ -552,10 +554,10 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
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case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetHardMinGfxClk,
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SMU10_UMD_PSTATE_MIN_GFXCLK);
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data->gfx_min_freq_limit/100);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetSoftMaxGfxClk,
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SMU10_UMD_PSTATE_MIN_GFXCLK);
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data->gfx_min_freq_limit/100);
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break;
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case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
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smum_send_msg_to_smc_with_parameter(hwmgr,
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@ -595,7 +597,7 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
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case AMD_DPM_FORCED_LEVEL_AUTO:
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetHardMinGfxClk,
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SMU10_UMD_PSTATE_MIN_GFXCLK);
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data->gfx_min_freq_limit/100);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetHardMinFclkByFreq,
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SMU10_UMD_PSTATE_MIN_FCLK);
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@ -608,7 +610,7 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetSoftMaxGfxClk,
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SMU10_UMD_PSTATE_PEAK_GFXCLK);
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data->gfx_max_freq_limit/100);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetSoftMaxFclkByFreq,
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SMU10_UMD_PSTATE_PEAK_FCLK);
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@ -622,10 +624,10 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
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case AMD_DPM_FORCED_LEVEL_LOW:
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetHardMinGfxClk,
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SMU10_UMD_PSTATE_MIN_GFXCLK);
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data->gfx_min_freq_limit/100);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetSoftMaxGfxClk,
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SMU10_UMD_PSTATE_MIN_GFXCLK);
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data->gfx_min_freq_limit/100);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetHardMinFclkByFreq,
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SMU10_UMD_PSTATE_MIN_FCLK);
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@ -773,21 +775,30 @@ static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
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struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
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struct smu10_voltage_dependency_table *mclk_table =
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data->clock_vol_info.vdd_dep_on_fclk;
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int i, now, size = 0;
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uint32_t i, now, size = 0;
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switch (type) {
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case PP_SCLK:
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);
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now = smum_get_argument(hwmgr);
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/* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
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if (now == data->gfx_max_freq_limit/100)
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i = 2;
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else if (now == data->gfx_min_freq_limit/100)
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i = 0;
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else
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i = 1;
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size += sprintf(buf + size, "0: %uMhz %s\n",
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data->gfx_min_freq_limit / 100,
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((data->gfx_min_freq_limit / 100)
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== now) ? "*" : "");
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data->gfx_min_freq_limit/100,
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i == 0 ? "*" : "");
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size += sprintf(buf + size, "1: %uMhz %s\n",
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data->gfx_max_freq_limit / 100,
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((data->gfx_max_freq_limit / 100)
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== now) ? "*" : "");
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i == 1 ? now : SMU10_UMD_PSTATE_GFXCLK,
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i == 1 ? "*" : "");
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size += sprintf(buf + size, "2: %uMhz %s\n",
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data->gfx_max_freq_limit/100,
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i == 2 ? "*" : "");
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break;
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case PP_MCLK:
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);
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@ -311,11 +311,9 @@ int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
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#define SMU10_UMD_PSTATE_FCLK 933
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#define SMU10_UMD_PSTATE_VCE 0x03C00320
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#define SMU10_UMD_PSTATE_PEAK_GFXCLK 1100
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#define SMU10_UMD_PSTATE_PEAK_SOCCLK 757
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#define SMU10_UMD_PSTATE_PEAK_FCLK 1200
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#define SMU10_UMD_PSTATE_MIN_GFXCLK 200
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#define SMU10_UMD_PSTATE_MIN_FCLK 400
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#define SMU10_UMD_PSTATE_MIN_SOCCLK 200
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#define SMU10_UMD_PSTATE_MIN_VCE 0x0190012C
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