xtensa: add IRQ domains support
IRQ domains provide a mechanism for conversion of linux IRQ numbers to hardware IRQ numbers and vice versus. It is used by OpenFirmware for linking device tree objects to their respective interrupt controllers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
This commit is contained in:
Max Filippov
Chris Zankel
Родитель
0322cabd39
Коммит
2206d5dd9a
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@ -17,6 +17,7 @@ config XTENSA
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select GENERIC_KERNEL_EXECVE
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select ARCH_WANT_OPTIONAL_GPIOLIB
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select CLONE_BACKWARDS
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select IRQ_DOMAIN
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help
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Xtensa processors are 32-bit RISC machines designed by Tensilica
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primarily for embedded systems. These processors are both
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@ -18,6 +18,7 @@
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel_stat.h>
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#include <linux/irqdomain.h>
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#include <asm/uaccess.h>
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#include <asm/platform.h>
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@ -26,19 +27,22 @@ static unsigned int cached_irq_mask;
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atomic_t irq_err_count;
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static struct irq_domain *root_domain;
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/*
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* do_IRQ handles all normal device IRQ's (the special
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* SMP cross-CPU interrupts have their own specific
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* handlers).
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*/
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asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
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asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs)
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{
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struct pt_regs *old_regs = set_irq_regs(regs);
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int irq = irq_find_mapping(root_domain, hwirq);
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if (irq >= NR_IRQS) {
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if (hwirq >= NR_IRQS) {
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printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
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__func__, irq);
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__func__, hwirq);
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}
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irq_enter();
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@ -71,40 +75,39 @@ int arch_show_interrupts(struct seq_file *p, int prec)
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static void xtensa_irq_mask(struct irq_data *d)
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{
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cached_irq_mask &= ~(1 << d->irq);
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cached_irq_mask &= ~(1 << d->hwirq);
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set_sr (cached_irq_mask, intenable);
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}
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static void xtensa_irq_unmask(struct irq_data *d)
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{
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cached_irq_mask |= 1 << d->irq;
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cached_irq_mask |= 1 << d->hwirq;
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set_sr (cached_irq_mask, intenable);
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}
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static void xtensa_irq_enable(struct irq_data *d)
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{
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variant_irq_enable(d->irq);
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variant_irq_enable(d->hwirq);
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xtensa_irq_unmask(d);
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}
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static void xtensa_irq_disable(struct irq_data *d)
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{
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xtensa_irq_mask(d);
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variant_irq_disable(d->irq);
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variant_irq_disable(d->hwirq);
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}
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static void xtensa_irq_ack(struct irq_data *d)
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{
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set_sr(1 << d->irq, intclear);
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set_sr(1 << d->hwirq, intclear);
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}
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static int xtensa_irq_retrigger(struct irq_data *d)
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{
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set_sr (1 << d->irq, INTSET);
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set_sr(1 << d->hwirq, intset);
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return 1;
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}
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static struct irq_chip xtensa_irq_chip = {
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.name = "xtensa",
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.irq_enable = xtensa_irq_enable,
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@ -115,37 +118,90 @@ static struct irq_chip xtensa_irq_chip = {
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.irq_retrigger = xtensa_irq_retrigger,
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};
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static int xtensa_irq_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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u32 mask = 1 << hw;
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if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) {
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irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
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handle_simple_irq, "level");
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irq_set_status_flags(irq, IRQ_LEVEL);
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} else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) {
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irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
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handle_edge_irq, "edge");
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irq_clear_status_flags(irq, IRQ_LEVEL);
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} else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) {
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irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
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handle_level_irq, "level");
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irq_set_status_flags(irq, IRQ_LEVEL);
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} else if (mask & XCHAL_INTTYPE_MASK_TIMER) {
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irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
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handle_edge_irq, "edge");
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irq_clear_status_flags(irq, IRQ_LEVEL);
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} else {/* XCHAL_INTTYPE_MASK_WRITE_ERROR */
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/* XCHAL_INTTYPE_MASK_NMI */
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irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
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handle_level_irq, "level");
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irq_set_status_flags(irq, IRQ_LEVEL);
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}
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return 0;
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}
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static unsigned map_ext_irq(unsigned ext_irq)
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{
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unsigned mask = XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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XCHAL_INTTYPE_MASK_EXTERN_LEVEL;
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unsigned i;
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for (i = 0; mask; ++i, mask >>= 1) {
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if ((mask & 1) && ext_irq-- == 0)
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return i;
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}
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return XCHAL_NUM_INTERRUPTS;
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}
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/*
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* Device Tree IRQ specifier translation function which works with one or
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* two cell bindings. First cell value maps directly to the hwirq number.
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* Second cell if present specifies whether hwirq number is external (1) or
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* internal (0).
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*/
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int xtensa_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq, unsigned int *out_type)
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{
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if (WARN_ON(intsize < 1 || intsize > 2))
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return -EINVAL;
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if (intsize == 2 && intspec[1] == 1) {
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unsigned int_irq = map_ext_irq(intspec[0]);
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if (int_irq < XCHAL_NUM_INTERRUPTS)
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*out_hwirq = int_irq;
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else
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return -EINVAL;
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} else {
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*out_hwirq = intspec[0];
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}
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*out_type = IRQ_TYPE_NONE;
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return 0;
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}
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static const struct irq_domain_ops xtensa_irq_domain_ops = {
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.xlate = xtensa_irq_domain_xlate,
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.map = xtensa_irq_map,
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};
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void __init init_IRQ(void)
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{
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int index;
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for (index = 0; index < XTENSA_NR_IRQS; index++) {
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int mask = 1 << index;
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if (mask & XCHAL_INTTYPE_MASK_SOFTWARE)
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irq_set_chip_and_handler(index, &xtensa_irq_chip,
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handle_simple_irq);
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else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE)
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irq_set_chip_and_handler(index, &xtensa_irq_chip,
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handle_edge_irq);
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else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL)
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irq_set_chip_and_handler(index, &xtensa_irq_chip,
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handle_level_irq);
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else if (mask & XCHAL_INTTYPE_MASK_TIMER)
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irq_set_chip_and_handler(index, &xtensa_irq_chip,
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handle_edge_irq);
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else /* XCHAL_INTTYPE_MASK_WRITE_ERROR */
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/* XCHAL_INTTYPE_MASK_NMI */
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irq_set_chip_and_handler(index, &xtensa_irq_chip,
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handle_level_irq);
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}
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struct device_node *intc = NULL;
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cached_irq_mask = 0;
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set_sr(~0, intclear);
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root_domain = irq_domain_add_legacy(intc, NR_IRQS, 0, 0,
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&xtensa_irq_domain_ops, NULL);
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irq_set_default_host(root_domain);
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variant_init_irq();
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}
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@ -22,6 +22,7 @@
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#include <linux/irq.h>
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#include <linux/profile.h>
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#include <linux/delay.h>
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#include <linux/irqdomain.h>
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#include <asm/timex.h>
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#include <asm/platform.h>
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@ -52,6 +53,7 @@ static struct irqaction timer_irqaction = {
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void __init time_init(void)
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{
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unsigned int irq;
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#ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
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printk("Calibrating CPU frequency ");
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platform_calibrate_ccount();
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@ -62,7 +64,8 @@ void __init time_init(void)
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/* Initialize the linux timer interrupt. */
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setup_irq(LINUX_TIMER_INT, &timer_irqaction);
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irq = irq_create_mapping(NULL, LINUX_TIMER_INT);
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setup_irq(irq, &timer_irqaction);
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set_linux_timer(get_ccount() + CCOUNT_PER_JIFFY);
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}
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