From 4de02e4a280678224bd12ec3b182e369c87c8fc5 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Sun, 22 Apr 2012 12:01:19 +0200 Subject: [PATCH 1/8] net: Add device tree support to LPC32xx This patch adds device tree support for lpc_eth.c. The runtime option for MII/RMII is solved via the "phy-mode" property, SRAM ("IRAM") usage for DMA can be chosen via "use-iram". Signed-off-by: Roland Stigge Reviewed-by: Arnd Bergmann Acked-by: David S. Miller --- .../devicetree/bindings/net/lpc-eth.txt | 24 +++++++ drivers/net/ethernet/nxp/lpc_eth.c | 71 +++++++++++++------ 2 files changed, 74 insertions(+), 21 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/lpc-eth.txt diff --git a/Documentation/devicetree/bindings/net/lpc-eth.txt b/Documentation/devicetree/bindings/net/lpc-eth.txt new file mode 100644 index 000000000000..585021acd178 --- /dev/null +++ b/Documentation/devicetree/bindings/net/lpc-eth.txt @@ -0,0 +1,24 @@ +* NXP LPC32xx SoC Ethernet Controller + +Required properties: +- compatible: Should be "nxp,lpc-eth" +- reg: Address and length of the register set for the device +- interrupts: Should contain ethernet controller interrupt + +Optional properties: +- phy-mode: String, operation mode of the PHY interface. + Supported values are: "mii", "rmii" (default) +- use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering +- local-mac-address : 6 bytes, mac address + +Example: + + mac: ethernet@31060000 { + compatible = "nxp,lpc-eth"; + reg = <0x31060000 0x1000>; + interrupt-parent = <&mic>; + interrupts = <29 0>; + + phy-mode = "rmii"; + use-iram; + }; diff --git a/drivers/net/ethernet/nxp/lpc_eth.c b/drivers/net/ethernet/nxp/lpc_eth.c index 6dfc26d85e47..52deec0b22ea 100644 --- a/drivers/net/ethernet/nxp/lpc_eth.c +++ b/drivers/net/ethernet/nxp/lpc_eth.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include @@ -340,13 +341,17 @@ */ #define LPC_POWERDOWN_MACAHB (1 << 31) -/* Upon the upcoming introduction of device tree usage in LPC32xx, - * lpc_phy_interface_mode() and use_iram_for_net() will be extended with a - * device parameter for access to device tree information at runtime, instead - * of defining the values at compile time - */ -static inline phy_interface_t lpc_phy_interface_mode(void) +static phy_interface_t lpc_phy_interface_mode(struct device *dev) { + if (dev && dev->of_node) { + const char *mode = of_get_property(dev->of_node, + "phy-mode", NULL); + if (mode && !strcmp(mode, "mii")) + return PHY_INTERFACE_MODE_MII; + return PHY_INTERFACE_MODE_RMII; + } + + /* non-DT */ #ifdef CONFIG_ARCH_LPC32XX_MII_SUPPORT return PHY_INTERFACE_MODE_MII; #else @@ -354,12 +359,16 @@ static inline phy_interface_t lpc_phy_interface_mode(void) #endif } -static inline int use_iram_for_net(void) +static bool use_iram_for_net(struct device *dev) { + if (dev && dev->of_node) + return of_property_read_bool(dev->of_node, "use-iram"); + + /* non-DT */ #ifdef CONFIG_ARCH_LPC32XX_IRAM_FOR_NET - return 1; + return true; #else - return 0; + return false; #endif } @@ -664,7 +673,7 @@ static void __lpc_eth_init(struct netdata_local *pldat) LPC_ENET_CLRT(pldat->net_base)); writel(LPC_IPGR_LOAD_PART2(0x12), LPC_ENET_IPGR(pldat->net_base)); - if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII) + if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII) writel(LPC_COMMAND_PASSRUNTFRAME, LPC_ENET_COMMAND(pldat->net_base)); else { @@ -804,12 +813,13 @@ static int lpc_mii_probe(struct net_device *ndev) } /* Attach to the PHY */ - if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII) + if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII) netdev_info(ndev, "using MII interface\n"); else netdev_info(ndev, "using RMII interface\n"); phydev = phy_connect(ndev, dev_name(&phydev->dev), - &lpc_handle_link_change, 0, lpc_phy_interface_mode()); + &lpc_handle_link_change, 0, + lpc_phy_interface_mode(&pldat->pdev->dev)); if (IS_ERR(phydev)) { netdev_err(ndev, "Could not attach to PHY\n"); @@ -843,7 +853,7 @@ static int lpc_mii_init(struct netdata_local *pldat) } /* Setup MII mode */ - if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII) + if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII) writel(LPC_COMMAND_PASSRUNTFRAME, LPC_ENET_COMMAND(pldat->net_base)); else { @@ -1315,18 +1325,26 @@ static const struct net_device_ops lpc_netdev_ops = { static int lpc_eth_drv_probe(struct platform_device *pdev) { struct resource *res; - struct resource *dma_res; struct net_device *ndev; struct netdata_local *pldat; struct phy_device *phydev; dma_addr_t dma_handle; int irq, ret; + u32 tmp; + + /* Setup network interface for RMII or MII mode */ + tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL); + tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK; + if (lpc_phy_interface_mode(&pdev->dev) == PHY_INTERFACE_MODE_MII) + tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS; + else + tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS; + __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL); /* Get platform resources */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); irq = platform_get_irq(pdev, 0); - if ((!res) || (!dma_res) || (irq < 0) || (irq >= NR_IRQS)) { + if ((!res) || (irq < 0) || (irq >= NR_IRQS)) { dev_err(&pdev->dev, "error getting resources.\n"); ret = -ENXIO; goto err_exit; @@ -1389,17 +1407,19 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t)); pldat->dma_buff_base_v = 0; - if (use_iram_for_net()) { - dma_handle = dma_res->start; + if (use_iram_for_net(&pldat->pdev->dev)) { + dma_handle = LPC32XX_IRAM_BASE; if (pldat->dma_buff_size <= lpc32xx_return_iram_size()) pldat->dma_buff_base_v = - io_p2v(dma_res->start); + io_p2v(LPC32XX_IRAM_BASE); else netdev_err(ndev, "IRAM not big enough for net buffers, using SDRAM instead.\n"); } if (pldat->dma_buff_base_v == 0) { + pldat->pdev->dev.coherent_dma_mask = 0xFFFFFFFF; + pldat->pdev->dev.dma_mask = &pldat->pdev->dev.coherent_dma_mask; pldat->dma_buff_size = PAGE_ALIGN(pldat->dma_buff_size); /* Allocate a chunk of memory for the DMA ethernet buffers @@ -1488,7 +1508,7 @@ err_out_unregister_netdev: platform_set_drvdata(pdev, NULL); unregister_netdev(ndev); err_out_dma_unmap: - if (!use_iram_for_net() || + if (!use_iram_for_net(&pldat->pdev->dev) || pldat->dma_buff_size > lpc32xx_return_iram_size()) dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size, pldat->dma_buff_base_v, @@ -1515,7 +1535,7 @@ static int lpc_eth_drv_remove(struct platform_device *pdev) unregister_netdev(ndev); platform_set_drvdata(pdev, NULL); - if (!use_iram_for_net() || + if (!use_iram_for_net(&pldat->pdev->dev) || pldat->dma_buff_size > lpc32xx_return_iram_size()) dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size, pldat->dma_buff_base_v, @@ -1584,6 +1604,14 @@ static int lpc_eth_drv_resume(struct platform_device *pdev) } #endif +#ifdef CONFIG_OF +static const struct of_device_id lpc_eth_match[] = { + { .compatible = "nxp,lpc-eth" }, + { } +}; +MODULE_DEVICE_TABLE(of, lpc_eth_match); +#endif + static struct platform_driver lpc_eth_driver = { .probe = lpc_eth_drv_probe, .remove = __devexit_p(lpc_eth_drv_remove), @@ -1593,6 +1621,7 @@ static struct platform_driver lpc_eth_driver = { #endif .driver = { .name = MODNAME, + .of_match_table = of_match_ptr(lpc_eth_match), }, }; From 5dfdb0a0639751781c440a00ea97630d3eafe7ca Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Sun, 22 Apr 2012 12:01:19 +0200 Subject: [PATCH 2/8] ARM: LPC32xx: clock.c cleanup This patch makes use of the default macro CLKDEV_INIT() for clock registration. Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/clock.c | 77 ++++++++++++++++------------------- 1 file changed, 35 insertions(+), 42 deletions(-) diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index 2fc24ca12054..043b9d47c07a 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c @@ -1095,49 +1095,42 @@ struct clk *clk_get_parent(struct clk *clk) } EXPORT_SYMBOL(clk_get_parent); -#define _REGISTER_CLOCK(d, n, c) \ - { \ - .dev_id = (d), \ - .con_id = (n), \ - .clk = &(c), \ - }, - static struct clk_lookup lookups[] = { - _REGISTER_CLOCK(NULL, "osc_32KHz", osc_32KHz) - _REGISTER_CLOCK(NULL, "osc_pll397", osc_pll397) - _REGISTER_CLOCK(NULL, "osc_main", osc_main) - _REGISTER_CLOCK(NULL, "sys_ck", clk_sys) - _REGISTER_CLOCK(NULL, "arm_pll_ck", clk_armpll) - _REGISTER_CLOCK(NULL, "ck_pll5", clk_usbpll) - _REGISTER_CLOCK(NULL, "hclk_ck", clk_hclk) - _REGISTER_CLOCK(NULL, "pclk_ck", clk_pclk) - _REGISTER_CLOCK(NULL, "timer0_ck", clk_timer0) - _REGISTER_CLOCK(NULL, "timer1_ck", clk_timer1) - _REGISTER_CLOCK(NULL, "timer2_ck", clk_timer2) - _REGISTER_CLOCK(NULL, "timer3_ck", clk_timer3) - _REGISTER_CLOCK(NULL, "vfp9_ck", clk_vfp9) - _REGISTER_CLOCK(NULL, "clk_dmac", clk_dma) - _REGISTER_CLOCK("pnx4008-watchdog", NULL, clk_wdt) - _REGISTER_CLOCK(NULL, "uart3_ck", clk_uart3) - _REGISTER_CLOCK(NULL, "uart4_ck", clk_uart4) - _REGISTER_CLOCK(NULL, "uart5_ck", clk_uart5) - _REGISTER_CLOCK(NULL, "uart6_ck", clk_uart6) - _REGISTER_CLOCK("pnx-i2c.0", NULL, clk_i2c0) - _REGISTER_CLOCK("pnx-i2c.1", NULL, clk_i2c1) - _REGISTER_CLOCK("pnx-i2c.2", NULL, clk_i2c2) - _REGISTER_CLOCK("dev:ssp0", NULL, clk_ssp0) - _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1) - _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan) - _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand) - _REGISTER_CLOCK("lpc32xx-adc", NULL, clk_adc) - _REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0) - _REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1) - _REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc) - _REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc) - _REGISTER_CLOCK("lpc-eth.0", NULL, clk_net) - _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd) - _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd) - _REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc) + CLKDEV_INIT(NULL, "osc_32KHz", &osc_32KHz), + CLKDEV_INIT(NULL, "osc_pll397", &osc_pll397), + CLKDEV_INIT(NULL, "osc_main", &osc_main), + CLKDEV_INIT(NULL, "sys_ck", &clk_sys), + CLKDEV_INIT(NULL, "arm_pll_ck", &clk_armpll), + CLKDEV_INIT(NULL, "ck_pll5", &clk_usbpll), + CLKDEV_INIT(NULL, "hclk_ck", &clk_hclk), + CLKDEV_INIT(NULL, "pclk_ck", &clk_pclk), + CLKDEV_INIT(NULL, "timer0_ck", &clk_timer0), + CLKDEV_INIT(NULL, "timer1_ck", &clk_timer1), + CLKDEV_INIT(NULL, "timer2_ck", &clk_timer2), + CLKDEV_INIT(NULL, "timer3_ck", &clk_timer3), + CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9), + CLKDEV_INIT(NULL, "clk_dmac", &clk_dma), + CLKDEV_INIT("pnx4008-watchdog", NULL, &clk_wdt), + CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3), + CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4), + CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5), + CLKDEV_INIT(NULL, "uart6_ck", &clk_uart6), + CLKDEV_INIT("pnx-i2c.0", NULL, &clk_i2c0), + CLKDEV_INIT("pnx-i2c.1", NULL, &clk_i2c1), + CLKDEV_INIT("pnx-i2c.2", NULL, &clk_i2c2), + CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0), + CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1), + CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan), + CLKDEV_INIT("lpc32xx-nand.0", "nand_ck", &clk_nand), + CLKDEV_INIT("lpc32xx-adc", NULL, &clk_adc), + CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0), + CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1), + CLKDEV_INIT("ts-lpc32xx", NULL, &clk_tsc), + CLKDEV_INIT("dev:mmc0", NULL, &clk_mmc), + CLKDEV_INIT("lpc-eth.0", NULL, &clk_net), + CLKDEV_INIT("dev:clcd", NULL, &clk_lcd), + CLKDEV_INIT("lpc32xx_udc", "ck_usbd", &clk_usbd), + CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc), }; static int __init clk_init(void) From 171b0a4f951926bf2e2bd58df53d5bd6549fb94a Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Sun, 22 Apr 2012 12:01:19 +0200 Subject: [PATCH 3/8] ARM: LPC32xx: clock.c registration adjustment This patch adjusts the clocks of the LPC32xx SoC to be picked up correctly by the respective drivers. * AMBA dmaengine * watchdog * I2C * TSC * MMC * Ethernet * ADC * USB Device (All except the pl08xdmac AMBA dmaengine via DT generated device name) Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/clock.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index 043b9d47c07a..f6a3ffec1f4b 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c @@ -1109,27 +1109,27 @@ static struct clk_lookup lookups[] = { CLKDEV_INIT(NULL, "timer2_ck", &clk_timer2), CLKDEV_INIT(NULL, "timer3_ck", &clk_timer3), CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9), - CLKDEV_INIT(NULL, "clk_dmac", &clk_dma), - CLKDEV_INIT("pnx4008-watchdog", NULL, &clk_wdt), + CLKDEV_INIT("pl08xdmac", NULL, &clk_dma), + CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt), CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3), CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4), CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5), CLKDEV_INIT(NULL, "uart6_ck", &clk_uart6), - CLKDEV_INIT("pnx-i2c.0", NULL, &clk_i2c0), - CLKDEV_INIT("pnx-i2c.1", NULL, &clk_i2c1), - CLKDEV_INIT("pnx-i2c.2", NULL, &clk_i2c2), + CLKDEV_INIT("400a0000.i2c", NULL, &clk_i2c0), + CLKDEV_INIT("400a8000.i2c", NULL, &clk_i2c1), + CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2), CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0), CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1), CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan), CLKDEV_INIT("lpc32xx-nand.0", "nand_ck", &clk_nand), - CLKDEV_INIT("lpc32xx-adc", NULL, &clk_adc), + CLKDEV_INIT("40048000.adc", NULL, &clk_adc), CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0), CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1), - CLKDEV_INIT("ts-lpc32xx", NULL, &clk_tsc), - CLKDEV_INIT("dev:mmc0", NULL, &clk_mmc), - CLKDEV_INIT("lpc-eth.0", NULL, &clk_net), + CLKDEV_INIT("40048000.tsc", NULL, &clk_tsc), + CLKDEV_INIT("20098000.sd", NULL, &clk_mmc), + CLKDEV_INIT("31060000.ethernet", NULL, &clk_net), CLKDEV_INIT("dev:clcd", NULL, &clk_lcd), - CLKDEV_INIT("lpc32xx_udc", "ck_usbd", &clk_usbd), + CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd), CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc), }; From b78dd166907313452da2defb88cde22031895260 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Sun, 22 Apr 2012 12:01:19 +0200 Subject: [PATCH 4/8] ARM: LPC32xx: Remove obsolete platform Kconfig This patch removes two Kconfig options now unused (the network driver is configured via DT now). Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/Kconfig | 26 -------------------------- 1 file changed, 26 deletions(-) diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig index 75946ac89ee9..e0b3eee83834 100644 --- a/arch/arm/mach-lpc32xx/Kconfig +++ b/arch/arm/mach-lpc32xx/Kconfig @@ -29,30 +29,4 @@ config ARCH_LPC32XX_UART6_SELECT endmenu -menu "LPC32XX chip components" - -config ARCH_LPC32XX_IRAM_FOR_NET - bool "Use IRAM for network buffers" - default y - help - Say Y here to use the LPC internal fast IRAM (i.e. 256KB SRAM) as - network buffer. If the total combined required buffer sizes is - larger than the size of IRAM, then SDRAM will be used instead. - - This can be enabled safely if the IRAM is not intended for other - uses. - -config ARCH_LPC32XX_MII_SUPPORT - bool "Check to enable MII support or leave disabled for RMII support" - help - Say Y here to enable MII support, or N for RMII support. Regardless of - which support is selected, the ethernet interface driver needs to be - selected in the device driver networking section. - - The PHY3250 reference board uses RMII, so users of this board should - say N. - -endmenu - endif - From e04920d9efcb3517cabc61a55a3ce4bce51518bc Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Sun, 22 Apr 2012 12:01:19 +0200 Subject: [PATCH 5/8] ARM: LPC32xx: DTS files for device tree conversion This patch adds the dts files for the reference machine of LPC32xx: * arch/arm/boot/dts/lpc32xx.dtsi: Include for devices based on LPC32xx * arch/arm/boot/dts/phy3250.dts: Board support for PHYTEC phyCORE-LPC3250 Signed-off-by: Roland Stigge --- arch/arm/boot/dts/lpc32xx.dtsi | 292 +++++++++++++++++++++++++++++++++ arch/arm/boot/dts/phy3250.dts | 145 ++++++++++++++++ 2 files changed, 437 insertions(+) create mode 100644 arch/arm/boot/dts/lpc32xx.dtsi create mode 100644 arch/arm/boot/dts/phy3250.dts diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi new file mode 100644 index 000000000000..2d696866f71c --- /dev/null +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -0,0 +1,292 @@ +/* + * NXP LPC32xx SoC + * + * Copyright 2012 Roland Stigge + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "nxp,lpc3220"; + interrupt-parent = <&mic>; + + cpus { + cpu@0 { + compatible = "arm,arm926ejs"; + }; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x20000000 0x20000000 0x30000000>; + + /* + * Enable either SLC or MLC + */ + slc: flash@20020000 { + compatible = "nxp,lpc3220-slc"; + reg = <0x20020000 0x1000>; + status = "disable"; + }; + + mlc: flash@200B0000 { + compatible = "nxp,lpc3220-mlc"; + reg = <0x200B0000 0x1000>; + status = "disable"; + }; + + dma@31000000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0x31000000 0x1000>; + interrupts = <0x1c 0>; + }; + + /* + * Enable either ohci or usbd (gadget)! + */ + ohci@31020000 { + compatible = "nxp,ohci-nxp", "usb-ohci"; + reg = <0x31020000 0x300>; + interrupts = <0x3b 0>; + status = "disable"; + }; + + usbd@31020000 { + compatible = "nxp,lpc3220-udc"; + reg = <0x31020000 0x300>; + interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; + status = "disable"; + }; + + clcd@31040000 { + compatible = "arm,pl110", "arm,primecell"; + reg = <0x31040000 0x1000>; + interrupts = <0x0e 0>; + status = "disable"; + }; + + mac: ethernet@31060000 { + compatible = "nxp,lpc-eth"; + reg = <0x31060000 0x1000>; + interrupts = <0x1d 0>; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x20000000 0x20000000 0x30000000>; + + ssp0: ssp@20084000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x20084000 0x1000>; + interrupts = <0x14 0>; + }; + + spi1: spi@20088000 { + compatible = "nxp,lpc3220-spi"; + reg = <0x20088000 0x1000>; + }; + + ssp1: ssp@2008c000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x2008c000 0x1000>; + interrupts = <0x15 0>; + }; + + spi2: spi@20090000 { + compatible = "nxp,lpc3220-spi"; + reg = <0x20090000 0x1000>; + }; + + i2s0: i2s@20094000 { + compatible = "nxp,lpc3220-i2s"; + reg = <0x20094000 0x1000>; + }; + + sd@20098000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x20098000 0x1000>; + interrupts = <0x0f 0>, <0x0d 0>; + }; + + i2s1: i2s@2009C000 { + compatible = "nxp,lpc3220-i2s"; + reg = <0x2009C000 0x1000>; + }; + + uart3: serial@40080000 { + compatible = "nxp,serial"; + reg = <0x40080000 0x1000>; + }; + + uart4: serial@40088000 { + compatible = "nxp,serial"; + reg = <0x40088000 0x1000>; + }; + + uart5: serial@40090000 { + compatible = "nxp,serial"; + reg = <0x40090000 0x1000>; + }; + + uart6: serial@40098000 { + compatible = "nxp,serial"; + reg = <0x40098000 0x1000>; + }; + + i2c1: i2c@400A0000 { + compatible = "nxp,pnx-i2c"; + reg = <0x400A0000 0x100>; + interrupts = <0x33 0>; + #address-cells = <1>; + #size-cells = <0>; + pnx,timeout = <0x64>; + }; + + i2c2: i2c@400A8000 { + compatible = "nxp,pnx-i2c"; + reg = <0x400A8000 0x100>; + interrupts = <0x32 0>; + #address-cells = <1>; + #size-cells = <0>; + pnx,timeout = <0x64>; + }; + + i2cusb: i2c@31020300 { + compatible = "nxp,pnx-i2c"; + reg = <0x31020300 0x100>; + interrupts = <0x3f 0>; + #address-cells = <1>; + #size-cells = <0>; + pnx,timeout = <0x64>; + }; + }; + + fab { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x20000000 0x20000000 0x30000000>; + + /* + * MIC Interrupt controller includes: + * MIC @40008000 + * SIC1 @4000C000 + * SIC2 @40010000 + */ + mic: interrupt-controller@40008000 { + compatible = "nxp,lpc3220-mic"; + interrupt-controller; + reg = <0x40008000 0xC000>; + #interrupt-cells = <2>; + }; + + uart1: serial@40014000 { + compatible = "nxp,serial"; + reg = <0x40014000 0x1000>; + }; + + uart2: serial@40018000 { + compatible = "nxp,serial"; + reg = <0x40018000 0x1000>; + }; + + uart7: serial@4001C000 { + compatible = "nxp,serial"; + reg = <0x4001C000 0x1000>; + }; + + rtc@40024000 { + compatible = "nxp,lpc3220-rtc"; + reg = <0x40024000 0x1000>; + interrupts = <0x34 0>; + }; + + gpio: gpio@40028000 { + compatible = "nxp,lpc3220-gpio"; + reg = <0x40028000 0x1000>; + /* create a private address space for enumeration */ + #address-cells = <1>; + #size-cells = <0>; + + gpio_p0: gpio-bank@0 { + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + }; + + gpio_p1: gpio-bank@1 { + gpio-controller; + #gpio-cells = <2>; + reg = <1>; + }; + + gpio_p2: gpio-bank@2 { + gpio-controller; + #gpio-cells = <2>; + reg = <2>; + }; + + gpio_p3: gpio-bank@3 { + gpio-controller; + #gpio-cells = <2>; + reg = <3>; + }; + + gpi_p3: gpio-bank@4 { + gpio-controller; + #gpio-cells = <2>; + reg = <4>; + }; + + gpo_p3: gpio-bank@5 { + gpio-controller; + #gpio-cells = <2>; + reg = <5>; + }; + }; + + watchdog@4003C000 { + compatible = "nxp,pnx4008-wdt"; + reg = <0x4003C000 0x1000>; + }; + + /* + * TSC vs. ADC: Since those two share the same + * hardware, you need to choose from one of the + * following two and do 'status = "okay";' for one of + * them + */ + + adc@40048000 { + compatible = "nxp,lpc3220-adc"; + reg = <0x40048000 0x1000>; + interrupts = <0x27 0>; + status = "disable"; + }; + + tsc@40048000 { + compatible = "nxp,lpc3220-tsc"; + reg = <0x40048000 0x1000>; + interrupts = <0x27 0>; + status = "disable"; + }; + + key@40050000 { + compatible = "nxp,lpc3220-key"; + reg = <0x40050000 0x1000>; + }; + + }; + }; +}; diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts new file mode 100644 index 000000000000..0167e86314c0 --- /dev/null +++ b/arch/arm/boot/dts/phy3250.dts @@ -0,0 +1,145 @@ +/* + * PHYTEC phyCORE-LPC3250 board + * + * Copyright 2012 Roland Stigge + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "lpc32xx.dtsi" + +/ { + model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250"; + compatible = "phytec,phy3250", "nxp,lpc3250"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + device_type = "memory"; + reg = <0 0x4000000>; + }; + + ahb { + mac: ethernet@31060000 { + phy-mode = "rmii"; + use-iram; + }; + + /* Here, choose exactly one from: ohci, usbd */ + ohci@31020000 { + transceiver = <&isp1301>; + status = "okay"; + }; + +/* + usbd@31020000 { + transceiver = <&isp1301>; + status = "okay"; + }; +*/ + + clcd@31040000 { + status = "okay"; + }; + + /* 64MB Flash via SLC NAND controller */ + slc: flash@20020000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <1>; + + mtd0@00000000 { + label = "phy3250-boot"; + reg = <0x00000000 0x00064000>; + read-only; + }; + + mtd1@00064000 { + label = "phy3250-uboot"; + reg = <0x00064000 0x00190000>; + read-only; + }; + + mtd2@001f4000 { + label = "phy3250-ubt-prms"; + reg = <0x001f4000 0x00010000>; + }; + + mtd3@00204000 { + label = "phy3250-kernel"; + reg = <0x00204000 0x00400000>; + }; + + mtd4@00604000 { + label = "phy3250-rootfs"; + reg = <0x00604000 0x039fc000>; + }; + }; + + apb { + i2c1: i2c@400A0000 { + clock-frequency = <100000>; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + uda1380: uda1380@18 { + compatible = "nxp,uda1380"; + reg = <0x18>; + power-gpio = <&gpio 0x59 0>; + reset-gpio = <&gpio 0x51 0>; + dac-clk = "wspll"; + }; + }; + + i2c2: i2c@400A8000 { + clock-frequency = <100000>; + }; + + i2cusb: i2c@31020300 { + clock-frequency = <100000>; + + isp1301: usb-transceiver@2c { + compatible = "nxp,isp1301"; + reg = <0x2c>; + }; + }; + + ssp0: ssp@20084000 { + eeprom: at25@0 { + compatible = "atmel,at25"; + }; + }; + }; + + fab { + tsc@40048000 { + status = "okay"; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + gpios = <&gpo_p3 1 1>; /* GPO_P3 1, GPIO 80, active low */ + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led1 { + gpios = <&gpo_p3 14 1>; /* GPO_P3 14, GPIO 93, active low */ + linux,default-trigger = "timer"; + default-state = "off"; + }; + }; +}; From f5c422713308e492eddc44a12134f9f249ddfbdb Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Sun, 22 Apr 2012 12:01:19 +0200 Subject: [PATCH 6/8] ARM: LPC32xx: Device tree support This patch does the actual device tree switch for the LPC32xx SoC. Signed-off-by: Roland Stigge --- .../devicetree/bindings/arm/lpc32xx-mic.txt | 38 ++++ .../devicetree/bindings/arm/lpc32xx.txt | 8 + arch/arm/Kconfig | 1 + arch/arm/mach-lpc32xx/common.c | 192 ------------------ arch/arm/mach-lpc32xx/common.h | 14 -- arch/arm/mach-lpc32xx/irq.c | 78 +++++-- arch/arm/mach-lpc32xx/phy3250.c | 138 +++++-------- 7 files changed, 158 insertions(+), 311 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/lpc32xx-mic.txt create mode 100644 Documentation/devicetree/bindings/arm/lpc32xx.txt diff --git a/Documentation/devicetree/bindings/arm/lpc32xx-mic.txt b/Documentation/devicetree/bindings/arm/lpc32xx-mic.txt new file mode 100644 index 000000000000..539adca19e8f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/lpc32xx-mic.txt @@ -0,0 +1,38 @@ +* NXP LPC32xx Main Interrupt Controller + (MIC, including SIC1 and SIC2 secondary controllers) + +Required properties: +- compatible: Should be "nxp,lpc3220-mic" +- interrupt-controller: Identifies the node as an interrupt controller. +- interrupt-parent: Empty for the interrupt controller itself +- #interrupt-cells: The number of cells to define the interrupts. Should be 2. + The first cell is the IRQ number + The second cell is used to specify mode: + 1 = low-to-high edge triggered + 2 = high-to-low edge triggered + 4 = active high level-sensitive + 8 = active low level-sensitive + Default for internal sources should be set to 4 (active high). +- reg: Should contain MIC registers location and length + +Examples: + /* + * MIC + */ + mic: interrupt-controller@40008000 { + compatible = "nxp,lpc3220-mic"; + interrupt-controller; + interrupt-parent; + #interrupt-cells = <2>; + reg = <0x40008000 0xC000>; + }; + + /* + * ADC + */ + adc@40048000 { + compatible = "nxp,lpc3220-adc"; + reg = <0x40048000 0x1000>; + interrupt-parent = <&mic>; + interrupts = <39 4>; + }; diff --git a/Documentation/devicetree/bindings/arm/lpc32xx.txt b/Documentation/devicetree/bindings/arm/lpc32xx.txt new file mode 100644 index 000000000000..56ec8ddc4a3b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/lpc32xx.txt @@ -0,0 +1,8 @@ +NXP LPC32xx Platforms Device Tree Bindings +------------------------------------------ + +Boards with the NXP LPC32xx SoC shall have the following properties: + +Required root node property: + +compatible: must be "nxp,lpc3220", "nxp,lpc3230", "nxp,lpc3240" or "nxp,lpc3250" diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cf006d40342c..6e51ddde908a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -597,6 +597,7 @@ config ARCH_LPC32XX select USB_ARCH_HAS_OHCI select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS + select USE_OF help Support for the NXP LPC32XX family of processors diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c index 6f255600fc97..0a41e1ec0c3a 100644 --- a/arch/arm/mach-lpc32xx/common.c +++ b/arch/arm/mach-lpc32xx/common.c @@ -31,198 +31,6 @@ #include #include "common.h" -/* - * Watchdog timer - */ -static struct resource watchdog_resources[] = { - [0] = { - .start = LPC32XX_WDTIM_BASE, - .end = LPC32XX_WDTIM_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device lpc32xx_watchdog_device = { - .name = "pnx4008-watchdog", - .id = -1, - .num_resources = ARRAY_SIZE(watchdog_resources), - .resource = watchdog_resources, -}; - -/* - * I2C busses - */ -static struct resource i2c0_resources[] = { - [0] = { - .start = LPC32XX_I2C1_BASE, - .end = LPC32XX_I2C1_BASE + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_LPC32XX_I2C_1, - .end = IRQ_LPC32XX_I2C_1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource i2c1_resources[] = { - [0] = { - .start = LPC32XX_I2C2_BASE, - .end = LPC32XX_I2C2_BASE + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_LPC32XX_I2C_2, - .end = IRQ_LPC32XX_I2C_2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource i2c2_resources[] = { - [0] = { - .start = LPC32XX_OTG_I2C_BASE, - .end = LPC32XX_OTG_I2C_BASE + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_LPC32XX_USB_I2C, - .end = IRQ_LPC32XX_USB_I2C, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device lpc32xx_i2c0_device = { - .name = "pnx-i2c.0", - .id = 0, - .num_resources = ARRAY_SIZE(i2c0_resources), - .resource = i2c0_resources, -}; - -struct platform_device lpc32xx_i2c1_device = { - .name = "pnx-i2c.1", - .id = 1, - .num_resources = ARRAY_SIZE(i2c1_resources), - .resource = i2c1_resources, -}; - -struct platform_device lpc32xx_i2c2_device = { - .name = "pnx-i2c.2", - .id = 2, - .num_resources = ARRAY_SIZE(i2c2_resources), - .resource = i2c2_resources, -}; - -/* TSC (Touch Screen Controller) */ - -static struct resource lpc32xx_tsc_resources[] = { - { - .start = LPC32XX_ADC_BASE, - .end = LPC32XX_ADC_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_LPC32XX_TS_IRQ, - .end = IRQ_LPC32XX_TS_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device lpc32xx_tsc_device = { - .name = "ts-lpc32xx", - .id = -1, - .num_resources = ARRAY_SIZE(lpc32xx_tsc_resources), - .resource = lpc32xx_tsc_resources, -}; - -/* RTC */ - -static struct resource lpc32xx_rtc_resources[] = { - { - .start = LPC32XX_RTC_BASE, - .end = LPC32XX_RTC_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - },{ - .start = IRQ_LPC32XX_RTC, - .end = IRQ_LPC32XX_RTC, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device lpc32xx_rtc_device = { - .name = "rtc-lpc32xx", - .id = -1, - .num_resources = ARRAY_SIZE(lpc32xx_rtc_resources), - .resource = lpc32xx_rtc_resources, -}; - -/* - * ADC support - */ -static struct resource adc_resources[] = { - { - .start = LPC32XX_ADC_BASE, - .end = LPC32XX_ADC_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_LPC32XX_TS_IRQ, - .end = IRQ_LPC32XX_TS_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device lpc32xx_adc_device = { - .name = "lpc32xx-adc", - .id = -1, - .num_resources = ARRAY_SIZE(adc_resources), - .resource = adc_resources, -}; - -/* - * USB support - */ -/* The dmamask must be set for OHCI to work */ -static u64 ohci_dmamask = ~(u32) 0; -static struct resource ohci_resources[] = { - { - .start = IO_ADDRESS(LPC32XX_USB_BASE), - .end = IO_ADDRESS(LPC32XX_USB_BASE + 0x100 - 1), - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_LPC32XX_USB_HOST, - .flags = IORESOURCE_IRQ, - }, -}; -struct platform_device lpc32xx_ohci_device = { - .name = "usb-ohci", - .id = -1, - .dev = { - .dma_mask = &ohci_dmamask, - .coherent_dma_mask = 0xFFFFFFFF, - }, - .num_resources = ARRAY_SIZE(ohci_resources), - .resource = ohci_resources, -}; - -/* - * Network Support - */ -static struct resource net_resources[] = { - [0] = DEFINE_RES_MEM(LPC32XX_ETHERNET_BASE, SZ_4K), - [1] = DEFINE_RES_MEM(LPC32XX_IRAM_BASE, SZ_128K), - [2] = DEFINE_RES_IRQ(IRQ_LPC32XX_ETHERNET), -}; - -static u64 lpc32xx_mac_dma_mask = 0xffffffffUL; -struct platform_device lpc32xx_net_device = { - .name = "lpc-eth", - .id = 0, - .dev = { - .dma_mask = &lpc32xx_mac_dma_mask, - .coherent_dma_mask = 0xffffffffUL, - }, - .num_resources = ARRAY_SIZE(net_resources), - .resource = net_resources, -}; - /* * Returns the unique ID for the device */ diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h index 68e45e8c9486..afeac3b1fae6 100644 --- a/arch/arm/mach-lpc32xx/common.h +++ b/arch/arm/mach-lpc32xx/common.h @@ -22,19 +22,6 @@ #include #include -/* - * Arch specific platform device structures - */ -extern struct platform_device lpc32xx_watchdog_device; -extern struct platform_device lpc32xx_i2c0_device; -extern struct platform_device lpc32xx_i2c1_device; -extern struct platform_device lpc32xx_i2c2_device; -extern struct platform_device lpc32xx_tsc_device; -extern struct platform_device lpc32xx_adc_device; -extern struct platform_device lpc32xx_rtc_device; -extern struct platform_device lpc32xx_ohci_device; -extern struct platform_device lpc32xx_net_device; - /* * Other arch specific structures and functions */ @@ -42,7 +29,6 @@ extern struct sys_timer lpc32xx_timer; extern void __init lpc32xx_init_irq(void); extern void __init lpc32xx_map_io(void); extern void __init lpc32xx_serial_init(void); -extern void __init lpc32xx_gpio_init(void); extern void lpc23xx_restart(char, const char *); diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c index d080cb1123dd..5b1cc35e6fba 100644 --- a/arch/arm/mach-lpc32xx/irq.c +++ b/arch/arm/mach-lpc32xx/irq.c @@ -22,6 +22,11 @@ #include #include #include +#include +#include +#include +#include +#include #include #include @@ -44,6 +49,9 @@ #define SIC1_ATR_DEFAULT 0x00026000 #define SIC2_ATR_DEFAULT 0x00000000 +static struct irq_domain *lpc32xx_mic_domain; +static struct device_node *lpc32xx_mic_np; + struct lpc32xx_event_group_regs { void __iomem *enab_reg; void __iomem *edge_reg; @@ -203,7 +211,7 @@ static void lpc32xx_mask_irq(struct irq_data *d) { unsigned int reg, ctrl, mask; - get_controller(d->irq, &ctrl, &mask); + get_controller(d->hwirq, &ctrl, &mask); reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask; __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); @@ -213,7 +221,7 @@ static void lpc32xx_unmask_irq(struct irq_data *d) { unsigned int reg, ctrl, mask; - get_controller(d->irq, &ctrl, &mask); + get_controller(d->hwirq, &ctrl, &mask); reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask; __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); @@ -223,14 +231,14 @@ static void lpc32xx_ack_irq(struct irq_data *d) { unsigned int ctrl, mask; - get_controller(d->irq, &ctrl, &mask); + get_controller(d->hwirq, &ctrl, &mask); __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl)); /* Also need to clear pending wake event */ - if (lpc32xx_events[d->irq].mask != 0) - __raw_writel(lpc32xx_events[d->irq].mask, - lpc32xx_events[d->irq].event_group->rawstat_reg); + if (lpc32xx_events[d->hwirq].mask != 0) + __raw_writel(lpc32xx_events[d->hwirq].mask, + lpc32xx_events[d->hwirq].event_group->rawstat_reg); } static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level, @@ -274,22 +282,22 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type) switch (type) { case IRQ_TYPE_EDGE_RISING: /* Rising edge sensitive */ - __lpc32xx_set_irq_type(d->irq, 1, 1); + __lpc32xx_set_irq_type(d->hwirq, 1, 1); break; case IRQ_TYPE_EDGE_FALLING: /* Falling edge sensitive */ - __lpc32xx_set_irq_type(d->irq, 0, 1); + __lpc32xx_set_irq_type(d->hwirq, 0, 1); break; case IRQ_TYPE_LEVEL_LOW: /* Low level sensitive */ - __lpc32xx_set_irq_type(d->irq, 0, 0); + __lpc32xx_set_irq_type(d->hwirq, 0, 0); break; case IRQ_TYPE_LEVEL_HIGH: /* High level sensitive */ - __lpc32xx_set_irq_type(d->irq, 1, 0); + __lpc32xx_set_irq_type(d->hwirq, 1, 0); break; /* Other modes are not supported */ @@ -298,7 +306,7 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type) } /* Ok to use the level handler for all types */ - irq_set_handler(d->irq, handle_level_irq); + irq_set_handler(d->hwirq, handle_level_irq); return 0; } @@ -307,33 +315,33 @@ static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state) { unsigned long eventreg; - if (lpc32xx_events[d->irq].mask != 0) { - eventreg = __raw_readl(lpc32xx_events[d->irq]. + if (lpc32xx_events[d->hwirq].mask != 0) { + eventreg = __raw_readl(lpc32xx_events[d->hwirq]. event_group->enab_reg); if (state) - eventreg |= lpc32xx_events[d->irq].mask; + eventreg |= lpc32xx_events[d->hwirq].mask; else { - eventreg &= ~lpc32xx_events[d->irq].mask; + eventreg &= ~lpc32xx_events[d->hwirq].mask; /* * When disabling the wakeup, clear the latched * event */ - __raw_writel(lpc32xx_events[d->irq].mask, - lpc32xx_events[d->irq]. + __raw_writel(lpc32xx_events[d->hwirq].mask, + lpc32xx_events[d->hwirq]. event_group->rawstat_reg); } __raw_writel(eventreg, - lpc32xx_events[d->irq].event_group->enab_reg); + lpc32xx_events[d->hwirq].event_group->enab_reg); return 0; } /* Clear event */ - __raw_writel(lpc32xx_events[d->irq].mask, - lpc32xx_events[d->irq].event_group->rawstat_reg); + __raw_writel(lpc32xx_events[d->hwirq].mask, + lpc32xx_events[d->hwirq].event_group->rawstat_reg); return -ENODEV; } @@ -353,6 +361,7 @@ static void __init lpc32xx_set_default_mappings(unsigned int apr, } static struct irq_chip lpc32xx_irq_chip = { + .name = "MIC", .irq_ack = lpc32xx_ack_irq, .irq_mask = lpc32xx_mask_irq, .irq_unmask = lpc32xx_unmask_irq, @@ -386,9 +395,23 @@ static void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc) } } +static int __init __lpc32xx_mic_of_init(struct device_node *node, + struct device_node *parent) +{ + lpc32xx_mic_np = node; + + return 0; +} + +static const struct of_device_id mic_of_match[] __initconst = { + { .compatible = "nxp,lpc3220-mic", .data = __lpc32xx_mic_of_init }, + { } +}; + void __init lpc32xx_init_irq(void) { unsigned int i; + int irq_base; /* Setup MIC */ __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE)); @@ -448,4 +471,19 @@ void __init lpc32xx_init_irq(void) LPC32XX_CLKPWR_PIN_RS); __raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS), LPC32XX_CLKPWR_INT_RS); + + of_irq_init(mic_of_match); + + irq_base = irq_alloc_descs(-1, 0, NR_IRQS, 0); + if (irq_base < 0) { + pr_warn("Cannot allocate irq_descs, assuming pre-allocated\n"); + irq_base = 0; + } + + lpc32xx_mic_domain = irq_domain_add_legacy(lpc32xx_mic_np, NR_IRQS, + irq_base, 0, + &irq_domain_simple_ops, + NULL); + if (!lpc32xx_mic_domain) + panic("Unable to add MIC irq domain\n"); } diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index 7f7401ec7487..483846ff8293 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -1,8 +1,9 @@ /* - * arch/arm/mach-lpc32xx/phy3250.c + * Platform support for LPC32xx SoC * * Author: Kevin Wells * + * Copyright (C) 2012 Roland Stigge * Copyright (C) 2010 NXP Semiconductors * * This program is free software; you can redistribute it and/or modify @@ -25,11 +26,16 @@ #include #include #include -#include #include #include #include #include +#include +#include +#include +#include +#include +#include #include #include @@ -47,7 +53,6 @@ #define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) #define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) #define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) -#define LED_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1) /* * AMBA LCD controller @@ -150,9 +155,6 @@ static struct clcd_board lpc32xx_clcd_data = { .remove = lpc32xx_clcd_remove, }; -static AMBA_AHB_DEVICE(lpc32xx_clcd, "dev:clcd", 0, - LPC32XX_LCD_BASE, { IRQ_LPC32XX_LCD }, &lpc32xx_clcd_data); - /* * AMBA SSP (SPI) */ @@ -180,8 +182,11 @@ static struct pl022_ssp_controller lpc32xx_ssp0_data = { .enable_dma = 0, }; -static AMBA_APB_DEVICE(lpc32xx_ssp0, "dev:ssp0", 0, - LPC32XX_SSP0_BASE, { IRQ_LPC32XX_SSP0 }, &lpc32xx_ssp0_data); +static struct pl022_ssp_controller lpc32xx_ssp1_data = { + .bus_id = 1, + .num_chipselect = 1, + .enable_dma = 0, +}; /* AT25 driver registration */ static int __init phy3250_spi_board_register(void) @@ -221,73 +226,20 @@ static int __init phy3250_spi_board_register(void) } arch_initcall(phy3250_spi_board_register); -static struct i2c_board_info __initdata phy3250_i2c_board_info[] = { - { - I2C_BOARD_INFO("pcf8563", 0x51), - }, +static struct pl08x_platform_data pl08x_pd = { }; -static struct gpio_led phy_leds[] = { - { - .name = "led0", - .gpio = LED_GPIO, - .active_low = 1, - .default_trigger = "heartbeat", - }, +static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { + OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data), + OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data), + OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data), + OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd), + { } }; -static struct gpio_led_platform_data led_data = { - .leds = phy_leds, - .num_leds = ARRAY_SIZE(phy_leds), -}; - -static struct platform_device lpc32xx_gpio_led_device = { - .name = "leds-gpio", - .id = -1, - .dev.platform_data = &led_data, -}; - -static struct platform_device *phy3250_devs[] __initdata = { - &lpc32xx_rtc_device, - &lpc32xx_tsc_device, - &lpc32xx_i2c0_device, - &lpc32xx_i2c1_device, - &lpc32xx_i2c2_device, - &lpc32xx_watchdog_device, - &lpc32xx_gpio_led_device, - &lpc32xx_adc_device, - &lpc32xx_ohci_device, - &lpc32xx_net_device, -}; - -static struct amba_device *amba_devs[] __initdata = { - &lpc32xx_clcd_device, - &lpc32xx_ssp0_device, -}; - -/* - * Board specific functions - */ -static void __init phy3250_board_init(void) +static void __init lpc3250_machine_init(void) { u32 tmp; - int i; - - lpc32xx_gpio_init(); - - /* Register GPIOs used on this board */ - if (gpio_request(SPI0_CS_GPIO, "spi0 cs")) - printk(KERN_ERR "Error requesting gpio %u", - SPI0_CS_GPIO); - else if (gpio_direction_output(SPI0_CS_GPIO, 1)) - printk(KERN_ERR "Error setting gpio %u to output", - SPI0_CS_GPIO); - - /* Setup network interface for RMII mode */ - tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL); - tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK; - tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS; - __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL); /* Setup SLC NAND controller muxing */ __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC, @@ -300,6 +252,12 @@ static void __init phy3250_board_init(void) tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16; __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL); + /* Set up USB power */ + tmp = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); + tmp |= LPC32XX_CLKPWR_USBCTRL_HCLK_EN | + LPC32XX_CLKPWR_USBCTRL_USBI2C_EN; + __raw_writel(tmp, LPC32XX_CLKPWR_USB_CTRL); + /* Set up I2C pull levels */ tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL); tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE | @@ -321,33 +279,35 @@ static void __init phy3250_board_init(void) /* * AMBA peripheral clocks need to be enabled prior to AMBA device * detection or a data fault will occur, so enable the clocks - * here. However, we don't want to enable them if the peripheral - * isn't included in the image + * here. */ -#ifdef CONFIG_FB_ARMCLCD tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL); __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN), LPC32XX_CLKPWR_LCDCLK_CTRL); -#endif -#ifdef CONFIG_SPI_PL022 + tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL); __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN), LPC32XX_CLKPWR_SSP_CLK_CTRL); -#endif - platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs)); - for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { - struct amba_device *d = amba_devs[i]; - amba_device_register(d, &iomem_resource); - } + tmp = __raw_readl(LPC32XX_CLKPWR_DMA_CLK_CTRL); + __raw_writel((tmp | LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN), + LPC32XX_CLKPWR_DMA_CLK_CTRL); /* Test clock needed for UDA1380 initial init */ __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN, LPC32XX_CLKPWR_TEST_CLK_SEL); - i2c_register_board_info(0, phy3250_i2c_board_info, - ARRAY_SIZE(phy3250_i2c_board_info)); + of_platform_populate(NULL, of_default_bus_match_table, + lpc32xx_auxdata_lookup, NULL); + + /* Register GPIOs used on this board */ + if (gpio_request(SPI0_CS_GPIO, "spi0 cs")) + printk(KERN_ERR "Error requesting gpio %u", + SPI0_CS_GPIO); + else if (gpio_direction_output(SPI0_CS_GPIO, 1)) + printk(KERN_ERR "Error setting gpio %u to output", + SPI0_CS_GPIO); } static int __init lpc32xx_display_uid(void) @@ -363,12 +323,20 @@ static int __init lpc32xx_display_uid(void) } arch_initcall(lpc32xx_display_uid); -MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller") - /* Maintainer: Kevin Wells, NXP Semiconductors */ +static char const *lpc32xx_dt_compat[] __initdata = { + "nxp,lpc3220", + "nxp,lpc3230", + "nxp,lpc3240", + "nxp,lpc3250", + NULL +}; + +DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)") .atag_offset = 0x100, .map_io = lpc32xx_map_io, .init_irq = lpc32xx_init_irq, .timer = &lpc32xx_timer, - .init_machine = phy3250_board_init, + .init_machine = lpc3250_machine_init, + .dt_compat = lpc32xx_dt_compat, .restart = lpc23xx_restart, MACHINE_END From be20dbc87879582e121e0525adcada13b3a8f476 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Sun, 22 Apr 2012 12:01:19 +0200 Subject: [PATCH 7/8] ARM: LPC32xx: Move common code to common.c This patch moves non-boardspecific LPC32xx code to common.c Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/common.c | 13 +++++++++++++ arch/arm/mach-lpc32xx/phy3250.c | 13 ------------- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c index 0a41e1ec0c3a..5c96057b6d78 100644 --- a/arch/arm/mach-lpc32xx/common.c +++ b/arch/arm/mach-lpc32xx/common.c @@ -223,3 +223,16 @@ void lpc23xx_restart(char mode, const char *cmd) while (1) ; } + +static int __init lpc32xx_display_uid(void) +{ + u32 uid[4]; + + lpc32xx_get_uid(uid); + + printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n", + uid[3], uid[2], uid[1], uid[0]); + + return 1; +} +arch_initcall(lpc32xx_display_uid); diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index 483846ff8293..540106cdb9ec 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -310,19 +310,6 @@ static void __init lpc3250_machine_init(void) SPI0_CS_GPIO); } -static int __init lpc32xx_display_uid(void) -{ - u32 uid[4]; - - lpc32xx_get_uid(uid); - - printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n", - uid[3], uid[2], uid[1], uid[0]); - - return 1; -} -arch_initcall(lpc32xx_display_uid); - static char const *lpc32xx_dt_compat[] __initdata = { "nxp,lpc3220", "nxp,lpc3230", From 89982a181b0783335d79e6e5264a23009aa7c6e9 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Sun, 22 Apr 2012 12:01:20 +0200 Subject: [PATCH 8/8] ARM: LPC32xx: Defconfig update This patch updates the defconfig for the LPC32xx SoC after device tree conversion: * Adjustment to DT conversion, added new driver support * Added IPv6 * Increased kernel log buffer Signed-off-by: Roland Stigge --- arch/arm/configs/lpc32xx_defconfig | 44 ++++++++++++++++++++++++++---- 1 file changed, 38 insertions(+), 6 deletions(-) diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig index fb2088171ca9..4fa60547494a 100644 --- a/arch/arm/configs/lpc32xx_defconfig +++ b/arch/arm/configs/lpc32xx_defconfig @@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 +CONFIG_LOG_BUF_SHIFT=16 CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y @@ -10,6 +10,7 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL_SYSCALL=y CONFIG_EMBEDDED=y CONFIG_SLAB=y +CONFIG_JUMP_LABEL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set @@ -21,6 +22,8 @@ CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CMDLINE="console=ttyS0,115200n81 root=/dev/ram0" CONFIG_CPU_IDLE=y CONFIG_FPE_NWFPE=y @@ -40,7 +43,8 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y # CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set @@ -55,13 +59,24 @@ CONFIG_BLK_DEV_CRYPTOLOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=1 CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_MISC_DEVICES=y CONFIG_EEPROM_AT25=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_NETDEVICES=y CONFIG_MII=y -CONFIG_PHYLIB=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_LPC_ENET=y +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set CONFIG_SMSC_PHY=y # CONFIG_WLAN is not set # CONFIG_INPUT_MOUSEDEV_PSAUX is not set @@ -97,16 +112,22 @@ CONFIG_SND_SEQUENCER=y CONFIG_SND_MIXER_OSS=y CONFIG_SND_PCM_OSS=y CONFIG_SND_SEQUENCER_OSS=y -CONFIG_SND_DYNAMIC_MINORS=y +# CONFIG_SND_SUPPORT_OLD_API is not set # CONFIG_SND_VERBOSE_PROCFS is not set +CONFIG_SND_DEBUG=y +CONFIG_SND_DEBUG_VERBOSE=y # CONFIG_SND_DRIVERS is not set # CONFIG_SND_ARM is not set # CONFIG_SND_SPI is not set CONFIG_SND_SOC=y # CONFIG_HID_SUPPORT is not set CONFIG_USB=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_STORAGE=y -CONFIG_USB_LIBUSUAL=y +CONFIG_USB_GADGET=y +CONFIG_USB_LPC32XX=y +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m CONFIG_MMC=y # CONFIG_MMC_BLOCK_BOUNCE is not set CONFIG_MMC_ARMMMCI=y @@ -114,10 +135,21 @@ CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_RTC_CLASS=y CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_DS1374=y +CONFIG_RTC_DRV_PCF8563=y CONFIG_RTC_DRV_LPC32XX=y +CONFIG_DMADEVICES=y +CONFIG_AMBA_PL08X=y +CONFIG_STAGING=y +CONFIG_IIO=y +CONFIG_LPC32XX_ADC=y CONFIG_EXT2_FS=y CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=y