ARM: OMAP: Split omap_cfg_reg() into omap processor specific functions
Use omap processor specific function depending on system type. Based on an earlier patch by Klaus Pedersen <klaus.k.pedersen@nokia.com>. Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren
Родитель
7d7f665d5d
Коммит
225dfda1d6
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@ -314,7 +314,110 @@ MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0)
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int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
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{
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static DEFINE_SPINLOCK(mux_spin_lock);
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unsigned long flags;
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unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
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pull_orig = 0, pull = 0;
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unsigned int mask, warn = 0;
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/* Check the mux register in question */
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if (cfg->mux_reg) {
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unsigned tmp1, tmp2;
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spin_lock_irqsave(&mux_spin_lock, flags);
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reg_orig = omap_readl(cfg->mux_reg);
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/* The mux registers always seem to be 3 bits long */
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mask = (0x7 << cfg->mask_offset);
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tmp1 = reg_orig & mask;
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reg = reg_orig & ~mask;
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tmp2 = (cfg->mask << cfg->mask_offset);
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reg |= tmp2;
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if (tmp1 != tmp2)
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warn = 1;
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omap_writel(reg, cfg->mux_reg);
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spin_unlock_irqrestore(&mux_spin_lock, flags);
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}
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/* Check for pull up or pull down selection on 1610 */
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if (!cpu_is_omap15xx()) {
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if (cfg->pu_pd_reg && cfg->pull_val) {
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spin_lock_irqsave(&mux_spin_lock, flags);
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pu_pd_orig = omap_readl(cfg->pu_pd_reg);
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mask = 1 << cfg->pull_bit;
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if (cfg->pu_pd_val) {
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if (!(pu_pd_orig & mask))
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warn = 1;
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/* Use pull up */
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pu_pd = pu_pd_orig | mask;
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} else {
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if (pu_pd_orig & mask)
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warn = 1;
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/* Use pull down */
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pu_pd = pu_pd_orig & ~mask;
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}
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omap_writel(pu_pd, cfg->pu_pd_reg);
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spin_unlock_irqrestore(&mux_spin_lock, flags);
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}
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}
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/* Check for an associated pull down register */
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if (cfg->pull_reg) {
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spin_lock_irqsave(&mux_spin_lock, flags);
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pull_orig = omap_readl(cfg->pull_reg);
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mask = 1 << cfg->pull_bit;
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if (cfg->pull_val) {
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if (pull_orig & mask)
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warn = 1;
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/* Low bit = pull enabled */
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pull = pull_orig & ~mask;
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} else {
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if (!(pull_orig & mask))
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warn = 1;
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/* High bit = pull disabled */
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pull = pull_orig | mask;
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}
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omap_writel(pull, cfg->pull_reg);
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spin_unlock_irqrestore(&mux_spin_lock, flags);
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}
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if (warn) {
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#ifdef CONFIG_OMAP_MUX_WARNINGS
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printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
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#endif
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}
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#ifdef CONFIG_OMAP_MUX_DEBUG
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if (cfg->debug || warn) {
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printk("MUX: Setting register %s\n", cfg->name);
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printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
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cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
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if (!cpu_is_omap15xx()) {
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if (cfg->pu_pd_reg && cfg->pull_val) {
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printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
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cfg->pu_pd_name, cfg->pu_pd_reg,
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pu_pd_orig, pu_pd);
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}
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}
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if (cfg->pull_reg)
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printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
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cfg->pull_name, cfg->pull_reg, pull_orig, pull);
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}
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#endif
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#ifdef CONFIG_OMAP_MUX_ERRORS
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return warn ? -ETXTBSY : 0;
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#else
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return 0;
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#endif
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}
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int __init omap1_mux_init(void)
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@ -172,8 +172,39 @@ MUX_CFG_24XX("B13_24XX_KBC6", 0x110, 3, 0, 0, 1)
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};
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#ifdef CONFIG_ARCH_OMAP24XX
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#define OMAP24XX_L4_BASE 0x48000000
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#define OMAP24XX_PULL_ENA (1 << 3)
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#define OMAP24XX_PULL_UP (1 << 4)
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/* REVISIT: Convert this code to use ctrl_{read,write}_reg */
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int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
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{
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u8 reg = 0;
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unsigned int warn = 0;
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reg |= cfg->mask & 0x7;
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if (cfg->pull_val)
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reg |= OMAP24XX_PULL_ENA;
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if(cfg->pu_pd_val)
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reg |= OMAP24XX_PULL_UP;
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#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
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{
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u8 orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg);
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u8 debug = 0;
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#ifdef CONFIG_OMAP_MUX_DEBUG
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debug = cfg->debug;
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#endif
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warn = (orig != reg);
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if (debug || warn)
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printk("MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
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cfg->name, OMAP24XX_L4_BASE + cfg->mux_reg,
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orig, reg);
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}
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#endif
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omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg);
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return 0;
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}
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#endif
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@ -32,10 +32,6 @@
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#ifdef CONFIG_OMAP_MUX
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#define OMAP24XX_L4_BASE 0x48000000
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#define OMAP24XX_PULL_ENA (1 << 3)
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#define OMAP24XX_PULL_UP (1 << 4)
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static struct omap_mux_cfg *mux_cfg;
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int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
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@ -56,13 +52,7 @@ int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
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*/
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int __init_or_module omap_cfg_reg(const unsigned long index)
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{
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static DEFINE_SPINLOCK(mux_spin_lock);
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unsigned long flags;
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struct pin_config *cfg;
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unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
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pull_orig = 0, pull = 0;
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unsigned int mask, warn = 0;
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struct pin_config *reg;
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if (mux_cfg == NULL) {
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printk(KERN_ERR "Pin mux table not initialized\n");
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@ -76,134 +66,12 @@ int __init_or_module omap_cfg_reg(const unsigned long index)
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return -ENODEV;
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}
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cfg = (struct pin_config *)&mux_cfg->pins[index];
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if (cpu_is_omap24xx()) {
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u8 reg = 0;
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reg = (struct pin_config *)&mux_cfg->pins[index];
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reg |= cfg->mask & 0x7;
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if (cfg->pull_val)
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reg |= OMAP24XX_PULL_ENA;
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if(cfg->pu_pd_val)
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reg |= OMAP24XX_PULL_UP;
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#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
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{
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u8 orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg);
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u8 debug = 0;
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if (!mux_cfg->cfg_reg)
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return -ENODEV;
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#ifdef CONFIG_OMAP_MUX_DEBUG
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debug = cfg->debug;
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#endif
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warn = (orig != reg);
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if (debug || warn)
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printk("MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
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cfg->name,
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OMAP24XX_L4_BASE + cfg->mux_reg,
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orig, reg);
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}
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#endif
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omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg);
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return 0;
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}
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/* Check the mux register in question */
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if (cfg->mux_reg) {
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unsigned tmp1, tmp2;
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spin_lock_irqsave(&mux_spin_lock, flags);
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reg_orig = omap_readl(cfg->mux_reg);
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/* The mux registers always seem to be 3 bits long */
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mask = (0x7 << cfg->mask_offset);
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tmp1 = reg_orig & mask;
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reg = reg_orig & ~mask;
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tmp2 = (cfg->mask << cfg->mask_offset);
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reg |= tmp2;
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if (tmp1 != tmp2)
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warn = 1;
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omap_writel(reg, cfg->mux_reg);
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spin_unlock_irqrestore(&mux_spin_lock, flags);
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}
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/* Check for pull up or pull down selection on 1610 */
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if (!cpu_is_omap15xx()) {
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if (cfg->pu_pd_reg && cfg->pull_val) {
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spin_lock_irqsave(&mux_spin_lock, flags);
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pu_pd_orig = omap_readl(cfg->pu_pd_reg);
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mask = 1 << cfg->pull_bit;
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if (cfg->pu_pd_val) {
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if (!(pu_pd_orig & mask))
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warn = 1;
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/* Use pull up */
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pu_pd = pu_pd_orig | mask;
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} else {
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if (pu_pd_orig & mask)
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warn = 1;
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/* Use pull down */
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pu_pd = pu_pd_orig & ~mask;
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}
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omap_writel(pu_pd, cfg->pu_pd_reg);
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spin_unlock_irqrestore(&mux_spin_lock, flags);
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}
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}
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/* Check for an associated pull down register */
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if (cfg->pull_reg) {
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spin_lock_irqsave(&mux_spin_lock, flags);
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pull_orig = omap_readl(cfg->pull_reg);
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mask = 1 << cfg->pull_bit;
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if (cfg->pull_val) {
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if (pull_orig & mask)
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warn = 1;
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/* Low bit = pull enabled */
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pull = pull_orig & ~mask;
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} else {
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if (!(pull_orig & mask))
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warn = 1;
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/* High bit = pull disabled */
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pull = pull_orig | mask;
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}
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omap_writel(pull, cfg->pull_reg);
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spin_unlock_irqrestore(&mux_spin_lock, flags);
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}
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if (warn) {
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#ifdef CONFIG_OMAP_MUX_WARNINGS
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printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
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#endif
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}
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#ifdef CONFIG_OMAP_MUX_DEBUG
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if (cfg->debug || warn) {
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printk("MUX: Setting register %s\n", cfg->name);
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printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
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cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
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if (!cpu_is_omap15xx()) {
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if (cfg->pu_pd_reg && cfg->pull_val) {
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printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
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cfg->pu_pd_name, cfg->pu_pd_reg,
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pu_pd_orig, pu_pd);
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}
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}
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if (cfg->pull_reg)
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printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
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cfg->pull_name, cfg->pull_reg, pull_orig, pull);
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}
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#endif
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#ifdef CONFIG_OMAP_MUX_ERRORS
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return warn ? -ETXTBSY : 0;
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#else
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return 0;
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#endif
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return mux_cfg->cfg_reg(reg);
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}
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EXPORT_SYMBOL(omap_cfg_reg);
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#else
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