[ARM] S3C: Move plat-s3c24xx pm.c support into plat-s3c
Move parts of the core and debug suspend code into the plat-s3c for use with the new s3c64xx code. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Ben Dooks
Родитель
549c7e33ae
Коммит
2261e0e6e3
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@ -113,3 +113,30 @@ extern void s3c_pm_check_store(void);
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#define s3c_pm_check_restore() do { } while(0)
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#define s3c_pm_check_store() do { } while(0)
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#endif
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/**
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* s3c_pm_configure_extint() - ensure pins are correctly set for IRQ
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*
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* Setup all the necessary GPIO pins for waking the system on external
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* interrupt.
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*/
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extern void s3c_pm_configure_extint(void);
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/**
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* s3c_pm_restore_gpios() - restore the state of the gpios after sleep.
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*
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* Restore the state of the GPIO pins after sleep, which may involve ensuring
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* that we do not glitch the state of the pins from that the bootloader's
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* resume code has done.
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*/
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extern void s3c_pm_restore_gpios(void);
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/**
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* s3c_pm_save_gpios() - save the state of the GPIOs for restoring after sleep.
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*
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* Save the GPIO states for resotration on resume. See s3c_pm_restore_gpios().
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*/
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extern void s3c_pm_save_gpios(void);
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extern void s3c_pm_save_core(void);
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extern void s3c_pm_restore_core(void);
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@ -15,14 +15,32 @@
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/serial_core.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <mach/hardware.h>
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#include <plat/regs-serial.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-mem.h>
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#include <mach/regs-irq.h>
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#include <plat/pm.h>
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#include <plat/pm-core.h>
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/* for external use */
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unsigned long s3c_pm_flags;
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/* Debug code:
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*
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* This code supports debug output to the low level UARTs for use on
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* resume before the console layer is available.
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*/
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#ifdef CONFIG_S3C2410_PM_DEBUG
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extern void printascii(const char *);
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@ -37,8 +55,51 @@ void s3c_pm_dbg(const char *fmt, ...)
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printascii(buff);
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}
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static inline void s3c_pm_debug_init(void)
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{
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/* restart uart clocks so we can use them to output */
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s3c_pm_debug_init_uart();
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}
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#else
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#define s3c_pm_debug_init() do { } while(0)
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#endif /* CONFIG_S3C2410_PM_DEBUG */
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/* Save the UART configurations if we are configured for debug. */
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#ifdef CONFIG_S3C2410_PM_DEBUG
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#define SAVE_UART(va) \
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SAVE_ITEM((va) + S3C2410_ULCON), \
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SAVE_ITEM((va) + S3C2410_UCON), \
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SAVE_ITEM((va) + S3C2410_UFCON), \
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SAVE_ITEM((va) + S3C2410_UMCON), \
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SAVE_ITEM((va) + S3C2410_UBRDIV)
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static struct sleep_save uart_save[] = {
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SAVE_UART(S3C_VA_UART0),
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SAVE_UART(S3C_VA_UART1),
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#ifndef CONFIG_CPU_S3C2400
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SAVE_UART(S3C_VA_UART2),
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#endif
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};
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static void s3c_pm_save_uart(void)
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{
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s3c_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
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}
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static void s3c_pm_restore_uart(void)
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{
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s3c_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
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}
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#else
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static void s3c_pm_save_uart(void) { }
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static void s3c_pm_restore_uart(void) { }
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#endif
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/* helper functions to save and restore register state */
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@ -95,3 +156,153 @@ void s3c_pm_do_restore_core(struct sleep_save *ptr, int count)
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for (; count > 0; count--, ptr++)
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__raw_writel(ptr->val, ptr->reg);
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}
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/* s3c2410_pm_show_resume_irqs
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*
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* print any IRQs asserted at resume time (ie, we woke from)
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*/
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static void s3c_pm_show_resume_irqs(int start, unsigned long which,
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unsigned long mask)
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{
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int i;
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which &= ~mask;
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for (i = 0; i <= 31; i++) {
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if (which & (1L<<i)) {
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S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
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}
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}
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}
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void (*pm_cpu_prep)(void);
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void (*pm_cpu_sleep)(void);
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#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
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/* s3c_pm_enter
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*
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* central control for sleep/resume process
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*/
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static int s3c_pm_enter(suspend_state_t state)
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{
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unsigned long regs_save[16];
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/* ensure the debug is initialised (if enabled) */
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s3c_pm_debug_init();
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S3C_PMDBG("%s(%d)\n", __func__, state);
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if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
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printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
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return -EINVAL;
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}
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/* check if we have anything to wake-up with... bad things seem
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* to happen if you suspend with no wakeup (system will often
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* require a full power-cycle)
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*/
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if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
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!any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
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printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
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printk(KERN_ERR "%s: Aborting sleep\n", __func__);
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return -EINVAL;
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}
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/* prepare check area if configured */
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s3c_pm_check_prepare();
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/* store the physical address of the register recovery block */
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s3c_sleep_save_phys = virt_to_phys(regs_save);
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S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);
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/* save all necessary core registers not covered by the drivers */
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s3c_pm_save_gpios();
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s3c_pm_save_uart();
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s3c_pm_save_core();
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/* set the irq configuration for wake */
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s3c_pm_configure_extint();
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S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
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s3c_irqwake_intmask, s3c_irqwake_eintmask);
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s3c_pm_arch_prepare_irqs();
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/* call cpu specific preparation */
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pm_cpu_prep();
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/* flush cache back to ram */
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flush_cache_all();
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s3c_pm_check_store();
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/* send the cpu to sleep... */
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s3c_pm_arch_stop_clocks();
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/* s3c2410_cpu_save will also act as our return point from when
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* we resume as it saves its own register state, so use the return
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* code to differentiate return from save and return from sleep */
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if (s3c2410_cpu_save(regs_save) == 0) {
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flush_cache_all();
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pm_cpu_sleep();
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}
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/* restore the cpu state using the kernel's cpu init code. */
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cpu_init();
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/* restore the system state */
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s3c_pm_restore_core();
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s3c_pm_restore_uart();
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s3c_pm_restore_gpios();
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s3c_pm_debug_init();
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/* check what irq (if any) restored the system */
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s3c_pm_arch_show_resume_irqs();
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S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
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s3c_pm_check_restore();
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/* ok, let's return from sleep */
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S3C_PMDBG("S3C PM Resume (post-restore)\n");
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return 0;
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}
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static struct platform_suspend_ops s3c_pm_ops = {
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.enter = s3c_pm_enter,
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.valid = suspend_valid_only_mem,
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};
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/* s3c2410_pm_init
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*
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* Attach the power management functions. This should be called
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* from the board specific initialisation if the board supports
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* it.
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*/
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int __init s3c2410_pm_init(void)
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{
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printk("S3C Power Management, Copyright 2004 Simtec Electronics\n");
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suspend_set_ops(&s3c_pm_ops);
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return 0;
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}
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@ -0,0 +1,59 @@
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/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
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*
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C24xx - PM core support for arch/arm/plat-s3c/pm.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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static inline void s3c_pm_debug_init_uart(void)
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{
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unsigned long tmp = __raw_readl(S3C2410_CLKCON);
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/* re-start uart clocks */
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tmp |= S3C2410_CLKCON_UART0;
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tmp |= S3C2410_CLKCON_UART1;
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tmp |= S3C2410_CLKCON_UART2;
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__raw_writel(tmp, S3C2410_CLKCON);
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udelay(10);
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}
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static inline void s3c_pm_arch_prepare_irqs(void)
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{
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__raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
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__raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
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/* ack any outstanding external interrupts before we go to sleep */
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__raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
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__raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
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__raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
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}
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static inline void s3c_pm_arch_stop_clocks(void)
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{
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__raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
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}
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static void s3c_pm_show_resume_irqs(int start, unsigned long which,
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unsigned long mask);
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static inline void s3c_pm_arch_show_resume_irqs(void)
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{
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S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n",
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__raw_readl(S3C2410_SRCPND),
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__raw_readl(S3C2410_EINTPEND));
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s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
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s3c_irqwake_intmask);
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s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
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s3c_irqwake_eintmask);
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}
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@ -34,9 +34,6 @@
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#include <linux/serial_core.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <mach/hardware.h>
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#include <plat/regs-serial.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-gpio.h>
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@ -47,7 +44,6 @@
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#include <plat/pm.h>
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#define PFX "s3c24xx-pm: "
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static struct sleep_save core_save[] = {
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@ -115,66 +111,6 @@ static struct sleep_save misc_save[] = {
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SAVE_ITEM(S3C2410_DCLKCON),
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};
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#ifdef CONFIG_S3C2410_PM_DEBUG
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#define SAVE_UART(va) \
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SAVE_ITEM((va) + S3C2410_ULCON), \
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SAVE_ITEM((va) + S3C2410_UCON), \
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SAVE_ITEM((va) + S3C2410_UFCON), \
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SAVE_ITEM((va) + S3C2410_UMCON), \
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SAVE_ITEM((va) + S3C2410_UBRDIV)
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static struct sleep_save uart_save[] = {
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SAVE_UART(S3C24XX_VA_UART0),
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SAVE_UART(S3C24XX_VA_UART1),
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#ifndef CONFIG_CPU_S3C2400
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SAVE_UART(S3C24XX_VA_UART2),
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#endif
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};
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/* debug
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*
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* we send the debug to printascii() to allow it to be seen if the
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* system never wakes up from the sleep
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*/
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static void s3c2410_pm_debug_init(void)
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{
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unsigned long tmp = __raw_readl(S3C2410_CLKCON);
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/* re-start uart clocks */
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tmp |= S3C2410_CLKCON_UART0;
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tmp |= S3C2410_CLKCON_UART1;
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tmp |= S3C2410_CLKCON_UART2;
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__raw_writel(tmp, S3C2410_CLKCON);
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udelay(10);
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}
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#else
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#define s3c2410_pm_debug_init() do { } while(0)
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static struct sleep_save uart_save[] = {};
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#endif
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/* s3c2410_pm_show_resume_irqs
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*
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* print any IRQs asserted at resume time (ie, we woke from)
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*/
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static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
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unsigned long mask)
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{
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int i;
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which &= ~mask;
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for (i = 0; i <= 31; i++) {
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if ((which) & (1L<<i)) {
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S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
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}
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}
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}
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/* s3c_pm_check_resume_pin
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*
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@ -206,12 +142,12 @@ static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
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}
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}
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/* s3c2410_pm_configure_extint
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/* s3c_pm_configure_extint
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*
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* configure all external interrupt pins
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*/
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static void s3c2410_pm_configure_extint(void)
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void s3c_pm_configure_extint(void)
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{
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int pin;
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@ -235,12 +171,12 @@ static void s3c2410_pm_configure_extint(void)
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#define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON)
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#define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON)
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/* s3c2410_pm_save_gpios()
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/* s3c_pm_save_gpios()
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*
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* Save the state of the GPIOs
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*/
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static void s3c2410_pm_save_gpios(void)
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void s3c_pm_save_gpios(void)
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{
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struct gpio_sleep *gps = gpio_save;
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unsigned int gpio;
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@ -279,7 +215,10 @@ static inline int is_out(unsigned long con)
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return con == 1;
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}
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/* s3c2410_pm_restore_gpio()
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/**
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* s3c2410_pm_restore_gpio() - restore the given GPIO bank
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* @index: The number of the GPIO bank being resumed.
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* @gps: The sleep confgiuration for the bank.
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*
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* Restore one of the GPIO banks that was saved during suspend. This is
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* not as simple as once thought, due to the possibility of glitches
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@ -397,7 +336,7 @@ static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps)
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* Restore the state of the GPIOs
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*/
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static void s3c2410_pm_restore_gpios(void)
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void s3c_pm_restore_gpios(void)
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{
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struct gpio_sleep *gps = gpio_save;
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int gpio;
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@ -407,150 +346,15 @@ static void s3c2410_pm_restore_gpios(void)
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}
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}
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||||
|
||||
void (*pm_cpu_prep)(void);
|
||||
void (*pm_cpu_sleep)(void);
|
||||
|
||||
#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
|
||||
|
||||
/* s3c2410_pm_enter
|
||||
*
|
||||
* central control for sleep/resume process
|
||||
*/
|
||||
|
||||
static int s3c2410_pm_enter(suspend_state_t state)
|
||||
void s3c_pm_restore_core(void)
|
||||
{
|
||||
unsigned long regs_save[16];
|
||||
|
||||
/* ensure the debug is initialised (if enabled) */
|
||||
|
||||
s3c2410_pm_debug_init();
|
||||
|
||||
S3C_PMDBG("s3c2410_pm_enter(%d)\n", state);
|
||||
|
||||
if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
|
||||
printk(KERN_ERR PFX "error: no cpu sleep functions set\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* check if we have anything to wake-up with... bad things seem
|
||||
* to happen if you suspend with no wakeup (system will often
|
||||
* require a full power-cycle)
|
||||
*/
|
||||
|
||||
if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
|
||||
!any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
|
||||
printk(KERN_ERR PFX "No sources enabled for wake-up!\n");
|
||||
printk(KERN_ERR PFX "Aborting sleep\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* prepare check area if configured */
|
||||
|
||||
s3c_pm_check_prepare();
|
||||
|
||||
/* store the physical address of the register recovery block */
|
||||
|
||||
s3c_sleep_save_phys = virt_to_phys(regs_save);
|
||||
|
||||
S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);
|
||||
|
||||
/* save all necessary core registers not covered by the drivers */
|
||||
|
||||
s3c2410_pm_save_gpios();
|
||||
s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
|
||||
s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
|
||||
s3c_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
|
||||
|
||||
/* set the irq configuration for wake */
|
||||
|
||||
s3c2410_pm_configure_extint();
|
||||
|
||||
S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
|
||||
s3c_irqwake_intmask, s3c_irqwake_eintmask);
|
||||
|
||||
__raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
|
||||
__raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
|
||||
|
||||
/* ack any outstanding external interrupts before we go to sleep */
|
||||
|
||||
__raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
|
||||
__raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
|
||||
__raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
|
||||
|
||||
/* call cpu specific preparation */
|
||||
|
||||
pm_cpu_prep();
|
||||
|
||||
/* flush cache back to ram */
|
||||
|
||||
flush_cache_all();
|
||||
|
||||
s3c_pm_check_store();
|
||||
|
||||
/* send the cpu to sleep... */
|
||||
|
||||
__raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
|
||||
|
||||
/* s3c2410_cpu_save will also act as our return point from when
|
||||
* we resume as it saves its own register state, so use the return
|
||||
* code to differentiate return from save and return from sleep */
|
||||
|
||||
if (s3c2410_cpu_save(regs_save) == 0) {
|
||||
flush_cache_all();
|
||||
pm_cpu_sleep();
|
||||
}
|
||||
|
||||
/* restore the cpu state */
|
||||
|
||||
cpu_init();
|
||||
|
||||
/* restore the system state */
|
||||
|
||||
s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
|
||||
s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
|
||||
s3c_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
|
||||
s3c2410_pm_restore_gpios();
|
||||
|
||||
s3c2410_pm_debug_init();
|
||||
|
||||
/* check what irq (if any) restored the system */
|
||||
|
||||
S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n",
|
||||
__raw_readl(S3C2410_SRCPND),
|
||||
__raw_readl(S3C2410_EINTPEND));
|
||||
|
||||
s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
|
||||
s3c_irqwake_intmask);
|
||||
|
||||
s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
|
||||
s3c_irqwake_eintmask);
|
||||
|
||||
S3C_PMDBG("post sleep, preparing to return\n");
|
||||
|
||||
s3c_pm_check_restore();
|
||||
|
||||
/* ok, let's return from sleep */
|
||||
|
||||
S3C_PMDBG("S3C2410 PM Resume (post-restore)\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_suspend_ops s3c2410_pm_ops = {
|
||||
.enter = s3c2410_pm_enter,
|
||||
.valid = suspend_valid_only_mem,
|
||||
};
|
||||
|
||||
/* s3c2410_pm_init
|
||||
*
|
||||
* Attach the power management functions. This should be called
|
||||
* from the board specific initialisation if the board supports
|
||||
* it.
|
||||
*/
|
||||
|
||||
int __init s3c2410_pm_init(void)
|
||||
void s3c_pm_save_core(void)
|
||||
{
|
||||
printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n");
|
||||
|
||||
suspend_set_ops(&s3c2410_pm_ops);
|
||||
return 0;
|
||||
s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
|
||||
s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
|
||||
}
|
||||
|
||||
|
|
|
|||
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