staging: et131x: Remove even more forward declarations
Moved functions in et131x.c file to remove the forward declarations of: et1310_in_phy_coma et1310_phy_access_mii_bit et131x_phy_mii_read et131x_mii_write et131x_rx_dma_memory_free Signed-off-by: Mark Einon <mark.einon@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Mark Einon
Greg Kroah-Hartman
Родитель
a4d444bdef
Коммит
2288760e3b
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@ -576,15 +576,6 @@ struct et131x_adapter {
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struct net_device_stats net_stats;
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};
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int et1310_in_phy_coma(struct et131x_adapter *adapter);
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void et1310_phy_access_mii_bit(struct et131x_adapter *adapter,
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u16 action,
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u16 regnum, u16 bitnum, u8 *value);
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int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
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u8 reg, u16 *value);
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int32_t et131x_mii_write(struct et131x_adapter *adapter,
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u8 reg, u16 value);
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void et131x_rx_dma_memory_free(struct et131x_adapter *adapter);
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void et131x_rx_dma_disable(struct et131x_adapter *adapter);
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void et131x_rx_dma_enable(struct et131x_adapter *adapter);
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void et131x_init_send(struct et131x_adapter *adapter);
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@ -1019,6 +1010,21 @@ void et1310_config_mac_regs2(struct et131x_adapter *adapter)
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}
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}
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/**
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* et1310_in_phy_coma - check if the device is in phy coma
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* @adapter: pointer to our adapter structure
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*
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* Returns 0 if the device is not in phy coma, 1 if it is in phy coma
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*/
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int et1310_in_phy_coma(struct et131x_adapter *adapter)
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{
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u32 pmcsr;
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pmcsr = readl(&adapter->regs->global.pm_csr);
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return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0;
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}
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void et1310_setup_device_for_multicast(struct et131x_adapter *adapter)
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{
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struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
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@ -1318,6 +1324,184 @@ void et1310_config_macstat_regs(struct et131x_adapter *adapter)
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writel(0xFFFE7E8B, &macstat->carry_reg2_mask);
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}
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/**
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* et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC
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* @adapter: pointer to our private adapter structure
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* @addr: the address of the transceiver
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* @reg: the register to read
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* @value: pointer to a 16-bit value in which the value will be stored
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*
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* Returns 0 on success, errno on failure (as defined in errno.h)
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*/
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int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
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u8 reg, u16 *value)
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{
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struct mac_regs __iomem *mac = &adapter->regs->mac;
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int status = 0;
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u32 delay = 0;
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u32 mii_addr;
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u32 mii_cmd;
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u32 mii_indicator;
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/* Save a local copy of the registers we are dealing with so we can
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* set them back
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*/
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mii_addr = readl(&mac->mii_mgmt_addr);
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mii_cmd = readl(&mac->mii_mgmt_cmd);
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/* Stop the current operation */
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writel(0, &mac->mii_mgmt_cmd);
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/* Set up the register we need to read from on the correct PHY */
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writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
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writel(0x1, &mac->mii_mgmt_cmd);
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do {
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udelay(50);
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delay++;
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mii_indicator = readl(&mac->mii_mgmt_indicator);
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} while ((mii_indicator & MGMT_WAIT) && delay < 50);
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/* If we hit the max delay, we could not read the register */
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if (delay == 50) {
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dev_warn(&adapter->pdev->dev,
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"reg 0x%08x could not be read\n", reg);
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dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
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mii_indicator);
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status = -EIO;
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}
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/* If we hit here we were able to read the register and we need to
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* return the value to the caller */
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*value = readl(&mac->mii_mgmt_stat) & 0xFFFF;
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/* Stop the read operation */
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writel(0, &mac->mii_mgmt_cmd);
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/* set the registers we touched back to the state at which we entered
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* this function
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*/
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writel(mii_addr, &mac->mii_mgmt_addr);
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writel(mii_cmd, &mac->mii_mgmt_cmd);
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return status;
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}
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int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value)
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{
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struct phy_device *phydev = adapter->phydev;
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if (!phydev)
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return -EIO;
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return et131x_phy_mii_read(adapter, phydev->addr, reg, value);
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}
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/**
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* et131x_mii_write - Write to a PHY register through the MII interface of the MAC
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* @adapter: pointer to our private adapter structure
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* @reg: the register to read
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* @value: 16-bit value to write
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*
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* FIXME: one caller in netdev still
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*
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* Return 0 on success, errno on failure (as defined in errno.h)
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*/
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int et131x_mii_write(struct et131x_adapter *adapter, u8 reg, u16 value)
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{
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struct mac_regs __iomem *mac = &adapter->regs->mac;
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struct phy_device *phydev = adapter->phydev;
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int status = 0;
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u8 addr;
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u32 delay = 0;
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u32 mii_addr;
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u32 mii_cmd;
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u32 mii_indicator;
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if (!phydev)
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return -EIO;
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addr = phydev->addr;
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/* Save a local copy of the registers we are dealing with so we can
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* set them back
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*/
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mii_addr = readl(&mac->mii_mgmt_addr);
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mii_cmd = readl(&mac->mii_mgmt_cmd);
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/* Stop the current operation */
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writel(0, &mac->mii_mgmt_cmd);
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/* Set up the register we need to write to on the correct PHY */
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writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
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/* Add the value to write to the registers to the mac */
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writel(value, &mac->mii_mgmt_ctrl);
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do {
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udelay(50);
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delay++;
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mii_indicator = readl(&mac->mii_mgmt_indicator);
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} while ((mii_indicator & MGMT_BUSY) && delay < 100);
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/* If we hit the max delay, we could not write the register */
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if (delay == 100) {
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u16 tmp;
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dev_warn(&adapter->pdev->dev,
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"reg 0x%08x could not be written", reg);
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dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
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mii_indicator);
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dev_warn(&adapter->pdev->dev, "command is 0x%08x\n",
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readl(&mac->mii_mgmt_cmd));
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et131x_mii_read(adapter, reg, &tmp);
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status = -EIO;
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}
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/* Stop the write operation */
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writel(0, &mac->mii_mgmt_cmd);
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/*
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* set the registers we touched back to the state at which we entered
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* this function
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*/
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writel(mii_addr, &mac->mii_mgmt_addr);
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writel(mii_cmd, &mac->mii_mgmt_cmd);
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return status;
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}
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/* Still used from _mac for BIT_READ */
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void et1310_phy_access_mii_bit(struct et131x_adapter *adapter, u16 action,
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u16 regnum, u16 bitnum, u8 *value)
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{
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u16 reg;
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u16 mask = 0x0001 << bitnum;
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/* Read the requested register */
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et131x_mii_read(adapter, regnum, ®);
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switch (action) {
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case TRUEPHY_BIT_READ:
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*value = (reg & mask) >> bitnum;
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break;
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case TRUEPHY_BIT_SET:
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et131x_mii_write(adapter, regnum, reg | mask);
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break;
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case TRUEPHY_BIT_CLEAR:
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et131x_mii_write(adapter, regnum, reg & ~mask);
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break;
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default:
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break;
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}
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}
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void et1310_config_flow_control(struct et131x_adapter *adapter)
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{
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struct phy_device *phydev = adapter->phydev;
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@ -1476,156 +1660,6 @@ int et131x_mdio_reset(struct mii_bus *bus)
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return 0;
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}
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int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value)
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{
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struct phy_device *phydev = adapter->phydev;
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if (!phydev)
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return -EIO;
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return et131x_phy_mii_read(adapter, phydev->addr, reg, value);
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}
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/**
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* et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC
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* @adapter: pointer to our private adapter structure
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* @addr: the address of the transceiver
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* @reg: the register to read
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* @value: pointer to a 16-bit value in which the value will be stored
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*
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* Returns 0 on success, errno on failure (as defined in errno.h)
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*/
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int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
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u8 reg, u16 *value)
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{
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struct mac_regs __iomem *mac = &adapter->regs->mac;
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int status = 0;
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u32 delay = 0;
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u32 mii_addr;
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u32 mii_cmd;
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u32 mii_indicator;
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/* Save a local copy of the registers we are dealing with so we can
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* set them back
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*/
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mii_addr = readl(&mac->mii_mgmt_addr);
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mii_cmd = readl(&mac->mii_mgmt_cmd);
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/* Stop the current operation */
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writel(0, &mac->mii_mgmt_cmd);
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/* Set up the register we need to read from on the correct PHY */
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writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
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writel(0x1, &mac->mii_mgmt_cmd);
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do {
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udelay(50);
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delay++;
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mii_indicator = readl(&mac->mii_mgmt_indicator);
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} while ((mii_indicator & MGMT_WAIT) && delay < 50);
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/* If we hit the max delay, we could not read the register */
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if (delay == 50) {
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dev_warn(&adapter->pdev->dev,
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"reg 0x%08x could not be read\n", reg);
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dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
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mii_indicator);
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status = -EIO;
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}
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/* If we hit here we were able to read the register and we need to
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* return the value to the caller */
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*value = readl(&mac->mii_mgmt_stat) & 0xFFFF;
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/* Stop the read operation */
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writel(0, &mac->mii_mgmt_cmd);
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/* set the registers we touched back to the state at which we entered
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* this function
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*/
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writel(mii_addr, &mac->mii_mgmt_addr);
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writel(mii_cmd, &mac->mii_mgmt_cmd);
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return status;
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}
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/**
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* et131x_mii_write - Write to a PHY register through the MII interface of the MAC
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* @adapter: pointer to our private adapter structure
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* @reg: the register to read
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* @value: 16-bit value to write
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*
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* FIXME: one caller in netdev still
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*
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* Return 0 on success, errno on failure (as defined in errno.h)
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*/
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int et131x_mii_write(struct et131x_adapter *adapter, u8 reg, u16 value)
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{
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struct mac_regs __iomem *mac = &adapter->regs->mac;
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struct phy_device *phydev = adapter->phydev;
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int status = 0;
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u8 addr;
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u32 delay = 0;
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u32 mii_addr;
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u32 mii_cmd;
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u32 mii_indicator;
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if (!phydev)
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return -EIO;
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addr = phydev->addr;
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/* Save a local copy of the registers we are dealing with so we can
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* set them back
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*/
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mii_addr = readl(&mac->mii_mgmt_addr);
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mii_cmd = readl(&mac->mii_mgmt_cmd);
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/* Stop the current operation */
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writel(0, &mac->mii_mgmt_cmd);
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/* Set up the register we need to write to on the correct PHY */
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writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
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/* Add the value to write to the registers to the mac */
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writel(value, &mac->mii_mgmt_ctrl);
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do {
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udelay(50);
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delay++;
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mii_indicator = readl(&mac->mii_mgmt_indicator);
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} while ((mii_indicator & MGMT_BUSY) && delay < 100);
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/* If we hit the max delay, we could not write the register */
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if (delay == 100) {
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u16 tmp;
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dev_warn(&adapter->pdev->dev,
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"reg 0x%08x could not be written", reg);
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dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
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mii_indicator);
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dev_warn(&adapter->pdev->dev, "command is 0x%08x\n",
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readl(&mac->mii_mgmt_cmd));
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et131x_mii_read(adapter, reg, &tmp);
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status = -EIO;
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}
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/* Stop the write operation */
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writel(0, &mac->mii_mgmt_cmd);
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/*
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* set the registers we touched back to the state at which we entered
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* this function
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*/
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writel(mii_addr, &mac->mii_mgmt_addr);
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writel(mii_cmd, &mac->mii_mgmt_cmd);
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return status;
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}
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/**
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* et1310_phy_power_down - PHY power control
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* @adapter: device to control
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@ -1647,34 +1681,6 @@ void et1310_phy_power_down(struct et131x_adapter *adapter, bool down)
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et131x_mii_write(adapter, MII_BMCR, data);
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}
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/* Still used from _mac for BIT_READ */
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void et1310_phy_access_mii_bit(struct et131x_adapter *adapter, u16 action,
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u16 regnum, u16 bitnum, u8 *value)
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{
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u16 reg;
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u16 mask = 0x0001 << bitnum;
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/* Read the requested register */
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et131x_mii_read(adapter, regnum, ®);
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switch (action) {
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case TRUEPHY_BIT_READ:
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*value = (reg & mask) >> bitnum;
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break;
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case TRUEPHY_BIT_SET:
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et131x_mii_write(adapter, regnum, reg | mask);
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break;
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case TRUEPHY_BIT_CLEAR:
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et131x_mii_write(adapter, regnum, reg & ~mask);
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break;
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default:
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break;
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}
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}
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/**
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* et131x_xcvr_init - Init the phy if we are setting it into force mode
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* @adapter: pointer to our private adapter structure
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@ -1770,21 +1776,6 @@ void et131x_configure_global_regs(struct et131x_adapter *adapter)
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/* PM functions */
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/**
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* et1310_in_phy_coma - check if the device is in phy coma
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* @adapter: pointer to our adapter structure
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*
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* Returns 0 if the device is not in phy coma, 1 if it is in phy coma
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*/
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int et1310_in_phy_coma(struct et131x_adapter *adapter)
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{
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u32 pmcsr;
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pmcsr = readl(&adapter->regs->global.pm_csr);
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return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0;
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}
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/**
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* et131x_config_rx_dma_regs - Start of Rx_DMA init sequence
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* @adapter: pointer to our adapter structure
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