net/irda: convert bfin_sir to common Blackfin UART header
No need to duplicate these defines now that the common Blackfin code has unified these for all UART devices. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Cc: Samuel Ortiz <samuel@sortiz.org> Cc: David Miller <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Родитель
6ac3f66492
Коммит
229de618ba
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@ -67,27 +67,27 @@ static void bfin_sir_stop_tx(struct bfin_sir_port *port)
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disable_dma(port->tx_dma_channel);
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disable_dma(port->tx_dma_channel);
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#endif
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#endif
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while (!(SIR_UART_GET_LSR(port) & THRE)) {
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while (!(UART_GET_LSR(port) & THRE)) {
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cpu_relax();
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cpu_relax();
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continue;
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continue;
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}
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}
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SIR_UART_STOP_TX(port);
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UART_CLEAR_IER(port, ETBEI);
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}
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}
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static void bfin_sir_enable_tx(struct bfin_sir_port *port)
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static void bfin_sir_enable_tx(struct bfin_sir_port *port)
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{
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{
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SIR_UART_ENABLE_TX(port);
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UART_SET_IER(port, ETBEI);
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}
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}
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static void bfin_sir_stop_rx(struct bfin_sir_port *port)
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static void bfin_sir_stop_rx(struct bfin_sir_port *port)
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{
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{
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SIR_UART_STOP_RX(port);
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UART_CLEAR_IER(port, ERBFI);
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}
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}
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static void bfin_sir_enable_rx(struct bfin_sir_port *port)
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static void bfin_sir_enable_rx(struct bfin_sir_port *port)
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{
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{
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SIR_UART_ENABLE_RX(port);
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UART_SET_IER(port, ERBFI);
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}
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}
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static int bfin_sir_set_speed(struct bfin_sir_port *port, int speed)
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static int bfin_sir_set_speed(struct bfin_sir_port *port, int speed)
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@ -116,7 +116,7 @@ static int bfin_sir_set_speed(struct bfin_sir_port *port, int speed)
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do {
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do {
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udelay(utime);
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udelay(utime);
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lsr = SIR_UART_GET_LSR(port);
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lsr = UART_GET_LSR(port);
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} while (!(lsr & TEMT) && count--);
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} while (!(lsr & TEMT) && count--);
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/* The useconds for 1 bits to transmit */
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/* The useconds for 1 bits to transmit */
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@ -125,27 +125,27 @@ static int bfin_sir_set_speed(struct bfin_sir_port *port, int speed)
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/* Clear UCEN bit to reset the UART state machine
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/* Clear UCEN bit to reset the UART state machine
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* and control registers
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* and control registers
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*/
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*/
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val = SIR_UART_GET_GCTL(port);
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val = UART_GET_GCTL(port);
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val &= ~UCEN;
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val &= ~UCEN;
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SIR_UART_PUT_GCTL(port, val);
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UART_PUT_GCTL(port, val);
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/* Set DLAB in LCR to Access THR RBR IER */
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/* Set DLAB in LCR to Access THR RBR IER */
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SIR_UART_SET_DLAB(port);
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UART_SET_DLAB(port);
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SSYNC();
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SSYNC();
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SIR_UART_PUT_DLL(port, quot & 0xFF);
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UART_PUT_DLL(port, quot & 0xFF);
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SIR_UART_PUT_DLH(port, (quot >> 8) & 0xFF);
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UART_PUT_DLH(port, (quot >> 8) & 0xFF);
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SSYNC();
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SSYNC();
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/* Clear DLAB in LCR */
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/* Clear DLAB in LCR */
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SIR_UART_CLEAR_DLAB(port);
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UART_CLEAR_DLAB(port);
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SSYNC();
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SSYNC();
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SIR_UART_PUT_LCR(port, lcr);
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UART_PUT_LCR(port, lcr);
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val = SIR_UART_GET_GCTL(port);
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val = UART_GET_GCTL(port);
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val |= UCEN;
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val |= UCEN;
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SIR_UART_PUT_GCTL(port, val);
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UART_PUT_GCTL(port, val);
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ret = 0;
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ret = 0;
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break;
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break;
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@ -154,12 +154,12 @@ static int bfin_sir_set_speed(struct bfin_sir_port *port, int speed)
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break;
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break;
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}
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}
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val = SIR_UART_GET_GCTL(port);
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val = UART_GET_GCTL(port);
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/* If not add the 'RPOLC', we can't catch the receive interrupt.
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/* If not add the 'RPOLC', we can't catch the receive interrupt.
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* It's related with the HW layout and the IR transiver.
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* It's related with the HW layout and the IR transiver.
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*/
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*/
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val |= IREN | RPOLC;
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val |= IREN | RPOLC;
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SIR_UART_PUT_GCTL(port, val);
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UART_PUT_GCTL(port, val);
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return ret;
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return ret;
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}
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}
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@ -168,7 +168,7 @@ static int bfin_sir_is_receiving(struct net_device *dev)
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struct bfin_sir_self *self = netdev_priv(dev);
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struct bfin_sir_self *self = netdev_priv(dev);
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struct bfin_sir_port *port = self->sir_port;
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struct bfin_sir_port *port = self->sir_port;
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if (!(SIR_UART_GET_IER(port) & ERBFI))
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if (!(UART_GET_IER(port) & ERBFI))
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return 0;
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return 0;
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return self->rx_buff.state != OUTSIDE_FRAME;
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return self->rx_buff.state != OUTSIDE_FRAME;
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}
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}
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@ -182,7 +182,7 @@ static void bfin_sir_tx_chars(struct net_device *dev)
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if (self->tx_buff.len != 0) {
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if (self->tx_buff.len != 0) {
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chr = *(self->tx_buff.data);
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chr = *(self->tx_buff.data);
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SIR_UART_PUT_CHAR(port, chr);
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UART_PUT_CHAR(port, chr);
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self->tx_buff.data++;
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self->tx_buff.data++;
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self->tx_buff.len--;
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self->tx_buff.len--;
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} else {
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} else {
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@ -206,8 +206,8 @@ static void bfin_sir_rx_chars(struct net_device *dev)
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struct bfin_sir_port *port = self->sir_port;
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struct bfin_sir_port *port = self->sir_port;
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unsigned char ch;
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unsigned char ch;
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SIR_UART_CLEAR_LSR(port);
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UART_CLEAR_LSR(port);
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ch = SIR_UART_GET_CHAR(port);
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ch = UART_GET_CHAR(port);
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async_unwrap_char(dev, &self->stats, &self->rx_buff, ch);
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async_unwrap_char(dev, &self->stats, &self->rx_buff, ch);
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dev->last_rx = jiffies;
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dev->last_rx = jiffies;
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}
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}
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@ -219,7 +219,7 @@ static irqreturn_t bfin_sir_rx_int(int irq, void *dev_id)
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struct bfin_sir_port *port = self->sir_port;
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struct bfin_sir_port *port = self->sir_port;
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spin_lock(&self->lock);
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spin_lock(&self->lock);
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while ((SIR_UART_GET_LSR(port) & DR))
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while ((UART_GET_LSR(port) & DR))
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bfin_sir_rx_chars(dev);
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bfin_sir_rx_chars(dev);
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spin_unlock(&self->lock);
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spin_unlock(&self->lock);
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@ -233,7 +233,7 @@ static irqreturn_t bfin_sir_tx_int(int irq, void *dev_id)
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struct bfin_sir_port *port = self->sir_port;
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struct bfin_sir_port *port = self->sir_port;
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spin_lock(&self->lock);
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spin_lock(&self->lock);
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if (SIR_UART_GET_LSR(port) & THRE)
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if (UART_GET_LSR(port) & THRE)
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bfin_sir_tx_chars(dev);
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bfin_sir_tx_chars(dev);
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spin_unlock(&self->lock);
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spin_unlock(&self->lock);
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@ -312,7 +312,7 @@ static void bfin_sir_dma_rx_chars(struct net_device *dev)
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struct bfin_sir_port *port = self->sir_port;
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struct bfin_sir_port *port = self->sir_port;
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int i;
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int i;
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SIR_UART_CLEAR_LSR(port);
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UART_CLEAR_LSR(port);
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for (i = port->rx_dma_buf.head; i < port->rx_dma_buf.tail; i++)
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for (i = port->rx_dma_buf.head; i < port->rx_dma_buf.tail; i++)
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async_unwrap_char(dev, &self->stats, &self->rx_buff, port->rx_dma_buf.buf[i]);
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async_unwrap_char(dev, &self->stats, &self->rx_buff, port->rx_dma_buf.buf[i]);
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@ -430,11 +430,10 @@ static void bfin_sir_shutdown(struct bfin_sir_port *port, struct net_device *dev
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unsigned short val;
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unsigned short val;
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bfin_sir_stop_rx(port);
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bfin_sir_stop_rx(port);
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SIR_UART_DISABLE_INTS(port);
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val = SIR_UART_GET_GCTL(port);
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val = UART_GET_GCTL(port);
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val &= ~(UCEN | IREN | RPOLC);
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val &= ~(UCEN | IREN | RPOLC);
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SIR_UART_PUT_GCTL(port, val);
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UART_PUT_GCTL(port, val);
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#ifdef CONFIG_SIR_BFIN_DMA
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#ifdef CONFIG_SIR_BFIN_DMA
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disable_dma(port->tx_dma_channel);
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disable_dma(port->tx_dma_channel);
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@ -518,12 +517,12 @@ static void bfin_sir_send_work(struct work_struct *work)
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* sending data. We also can set the speed, which will
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* sending data. We also can set the speed, which will
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* reset all the UART.
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* reset all the UART.
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*/
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*/
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val = SIR_UART_GET_GCTL(port);
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val = UART_GET_GCTL(port);
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val &= ~(IREN | RPOLC);
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val &= ~(IREN | RPOLC);
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SIR_UART_PUT_GCTL(port, val);
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UART_PUT_GCTL(port, val);
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SSYNC();
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SSYNC();
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val |= IREN | RPOLC;
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val |= IREN | RPOLC;
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SIR_UART_PUT_GCTL(port, val);
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UART_PUT_GCTL(port, val);
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SSYNC();
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SSYNC();
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/* bfin_sir_set_speed(port, self->speed); */
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/* bfin_sir_set_speed(port, self->speed); */
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@ -26,7 +26,6 @@
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#include <asm/cacheflush.h>
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#include <asm/cacheflush.h>
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#include <asm/dma.h>
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#include <asm/dma.h>
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#include <asm/portmux.h>
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#include <asm/portmux.h>
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#include <mach/bfin_serial_5xx.h>
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#undef DRIVER_NAME
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#undef DRIVER_NAME
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#ifdef CONFIG_SIR_BFIN_DMA
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#ifdef CONFIG_SIR_BFIN_DMA
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@ -83,64 +82,10 @@ struct bfin_sir_self {
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#define DRIVER_NAME "bfin_sir"
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#define DRIVER_NAME "bfin_sir"
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#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
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#define port_membase(port) (((struct bfin_sir_port *)(port))->membase)
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#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
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#define get_lsr_cache(port) (((struct bfin_sir_port *)(port))->lsr)
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#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
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#define put_lsr_cache(port, v) (((struct bfin_sir_port *)(port))->lsr = (v))
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#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
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#include <asm/bfin_serial.h>
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#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
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#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
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#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
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#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
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#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
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#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
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#ifdef CONFIG_BF54x
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#define SIR_UART_GET_LSR(port) bfin_read16((port)->membase + OFFSET_LSR)
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#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER_SET)
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#define SIR_UART_SET_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_SET), v)
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#define SIR_UART_CLEAR_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v)
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#define SIR_UART_PUT_LSR(port, v) bfin_write16(((port)->membase + OFFSET_LSR), v)
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#define SIR_UART_CLEAR_LSR(port) bfin_write16(((port)->membase + OFFSET_LSR), -1)
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#define SIR_UART_SET_DLAB(port)
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#define SIR_UART_CLEAR_DLAB(port)
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#define SIR_UART_ENABLE_INTS(port, v) SIR_UART_SET_IER(port, v)
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#define SIR_UART_DISABLE_INTS(port) SIR_UART_CLEAR_IER(port, 0xF)
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#define SIR_UART_STOP_TX(port) do { SIR_UART_PUT_LSR(port, TFI); SIR_UART_CLEAR_IER(port, ETBEI); } while (0)
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#define SIR_UART_ENABLE_TX(port) do { SIR_UART_SET_IER(port, ETBEI); } while (0)
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#define SIR_UART_STOP_RX(port) do { SIR_UART_CLEAR_IER(port, ERBFI); } while (0)
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#define SIR_UART_ENABLE_RX(port) do { SIR_UART_SET_IER(port, ERBFI); } while (0)
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#else
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#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
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#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
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#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
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#define SIR_UART_SET_DLAB(port) do { SIR_UART_PUT_LCR(port, SIR_UART_GET_LCR(port) | DLAB); } while (0)
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#define SIR_UART_CLEAR_DLAB(port) do { SIR_UART_PUT_LCR(port, SIR_UART_GET_LCR(port) & ~DLAB); } while (0)
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#define SIR_UART_ENABLE_INTS(port, v) SIR_UART_PUT_IER(port, v)
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#define SIR_UART_DISABLE_INTS(port) SIR_UART_PUT_IER(port, 0)
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#define SIR_UART_STOP_TX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) & ~ETBEI); } while (0)
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#define SIR_UART_ENABLE_TX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) | ETBEI); } while (0)
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#define SIR_UART_STOP_RX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) & ~ERBFI); } while (0)
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#define SIR_UART_ENABLE_RX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) | ERBFI); } while (0)
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static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
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{
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unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
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port->lsr |= (lsr & (BI|FE|PE|OE));
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return lsr | port->lsr;
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}
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static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
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{
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port->lsr = 0;
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bfin_read16(port->membase + OFFSET_LSR);
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}
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#endif
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static const unsigned short per[][4] = {
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static const unsigned short per[][4] = {
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/* rx pin tx pin NULL uart_number */
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/* rx pin tx pin NULL uart_number */
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