[MIPS] txx9tmr clockevent/clocksource driver
Convert jmr3927_clock_event_device to more generic txx9tmr_clock_event_device which supports one-shot mode. The txx9tmr_clock_event_device can be used for TX49 too if the cp0 timer interrupt was not available. Convert jmr3927_hpt_read to txx9_clocksource driver which does not depends jiffies anymore. The txx9_clocksource itself can be used for TX49, but normally TX49 uses higher precision clocksource_mips. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Atsushi Nemoto
Ralf Baechle
Родитель
22df3f53e3
Коммит
229f773ef4
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@ -583,6 +583,7 @@ config SNI_RM
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config TOSHIBA_JMR3927
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bool "Toshiba JMR-TX3927 board"
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select CEVT_TXX9
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select DMA_NONCOHERENT
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select HW_HAS_PCI
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select MIPS_TX3927
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@ -597,6 +598,7 @@ config TOSHIBA_JMR3927
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config TOSHIBA_RBTX4927
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bool "Toshiba RBTX49[23]7 board"
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select CEVT_R4K
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select CEVT_TXX9
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select DMA_NONCOHERENT
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select HAS_TXX9_SERIAL
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select HW_HAS_PCI
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@ -618,6 +620,7 @@ config TOSHIBA_RBTX4927
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config TOSHIBA_RBTX4938
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bool "Toshiba RBTX4938 board"
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select CEVT_R4K
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select CEVT_TXX9
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select DMA_NONCOHERENT
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select HAS_TXX9_SERIAL
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select HW_HAS_PCI
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@ -736,6 +739,9 @@ config CEVT_GT641XX
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config CEVT_R4K
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bool
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config CEVT_TXX9
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bool
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config CFE
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bool
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@ -27,17 +27,13 @@
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* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
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*/
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#include <linux/clockchips.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/kdev_t.h>
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#include <linux/types.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/ide.h>
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#include <linux/irq.h>
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#include <linux/ioport.h>
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#include <linux/param.h> /* for HZ */
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#include <linux/delay.h>
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#include <linux/pm.h>
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#include <linux/platform_device.h>
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@ -48,17 +44,13 @@
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#endif
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#include <asm/addrspace.h>
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#include <asm/time.h>
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#include <asm/txx9tmr.h>
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#include <asm/reboot.h>
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#include <asm/jmr3927/jmr3927.h>
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#include <asm/mipsregs.h>
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extern void puts(const char *cp);
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/* Tick Timer divider */
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#define JMR3927_TIMER_CCD 0 /* 1/2 */
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#define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
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/* don't enable - see errata */
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static int jmr3927_ccfg_toeon;
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@ -93,66 +85,12 @@ static void jmr3927_machine_power_off(void)
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while (1);
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}
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static cycle_t jmr3927_hpt_read(void)
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{
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/* We assume this function is called xtime_lock held. */
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return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr;
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}
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static void jmr3927_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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/* Nothing to do here */
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}
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struct clock_event_device jmr3927_clock_event_device = {
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.name = "MIPS",
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.features = CLOCK_EVT_FEAT_PERIODIC,
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.shift = 32,
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.rating = 300,
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.cpumask = CPU_MASK_CPU0,
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.irq = JMR3927_IRQ_TICK,
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.set_mode = jmr3927_set_mode,
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};
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static irqreturn_t jmr3927_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *cd = &jmr3927_clock_event_device;
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jmr3927_tmrptr->tisr = 0; /* ack interrupt */
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cd->event_handler(cd);
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return IRQ_HANDLED;
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}
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static struct irqaction jmr3927_timer_irqaction = {
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.handler = jmr3927_timer_interrupt,
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.flags = IRQF_DISABLED | IRQF_PERCPU,
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.name = "jmr3927-timer",
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};
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void __init plat_time_init(void)
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{
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struct clock_event_device *cd;
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clocksource_mips.read = jmr3927_hpt_read;
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mips_hpt_frequency = JMR3927_TIMER_CLK;
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jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
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jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
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jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
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jmr3927_tmrptr->tcr =
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TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
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cd = &jmr3927_clock_event_device;
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/* Calculate the min / max delta */
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cd->mult = div_sc((unsigned long) JMR3927_IMCLK, NSEC_PER_SEC, 32);
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cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
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cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
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clockevents_register_device(cd);
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setup_irq(JMR3927_IRQ_TICK, &jmr3927_timer_irqaction);
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txx9_clockevent_init(TX3927_TMR_REG(0),
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TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0),
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JMR3927_IMCLK);
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txx9_clocksource_init(TX3927_TMR_REG(1), JMR3927_IMCLK);
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}
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#define DO_WRITE_THROUGH
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@ -317,15 +255,8 @@ static void __init tx3927_setup(void)
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tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
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/* TMR */
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/* disable all timers */
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for (i = 0; i < TX3927_NR_TMR; i++) {
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tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
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tx3927_tmrptr(i)->tisr = 0;
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tx3927_tmrptr(i)->cpra = 0xffffffff;
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tx3927_tmrptr(i)->itmr = 0;
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tx3927_tmrptr(i)->ccdr = 0;
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tx3927_tmrptr(i)->pgmr = 0;
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}
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for (i = 0; i < TX3927_NR_TMR; i++)
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txx9_tmr_init(TX3927_TMR_REG(i));
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/* DMA */
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tx3927_dmaptr->mcr = 0;
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@ -10,6 +10,7 @@ obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
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obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o
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obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
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obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
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binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \
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irix5sys.o sysirix.o
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@ -0,0 +1,171 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Based on linux/arch/mips/kernel/cevt-r4k.c,
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* linux/arch/mips/jmr3927/rbhma3100/setup.c
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*
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* Copyright 2001 MontaVista Software Inc.
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* Copyright (C) 2000-2001 Toshiba Corporation
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* Copyright (C) 2007 MIPS Technologies, Inc.
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* Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <asm/time.h>
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#include <asm/txx9tmr.h>
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#define TCR_BASE (TXx9_TMTCR_CCDE | TXx9_TMTCR_CRE | TXx9_TMTCR_TMODE_ITVL)
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#define TIMER_CCD 0 /* 1/2 */
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#define TIMER_CLK(imclk) ((imclk) / (2 << TIMER_CCD))
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static struct txx9_tmr_reg __iomem *txx9_cs_tmrptr;
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static cycle_t txx9_cs_read(void)
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{
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return __raw_readl(&txx9_cs_tmrptr->trr);
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}
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/* Use 1 bit smaller width to use full bits in that width */
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#define TXX9_CLOCKSOURCE_BITS (TXX9_TIMER_BITS - 1)
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static struct clocksource txx9_clocksource = {
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.name = "TXx9",
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.rating = 200,
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.read = txx9_cs_read,
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.mask = CLOCKSOURCE_MASK(TXX9_CLOCKSOURCE_BITS),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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void __init txx9_clocksource_init(unsigned long baseaddr,
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unsigned int imbusclk)
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{
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struct txx9_tmr_reg __iomem *tmrptr;
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clocksource_set_clock(&txx9_clocksource, TIMER_CLK(imbusclk));
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clocksource_register(&txx9_clocksource);
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tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
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__raw_writel(TCR_BASE, &tmrptr->tcr);
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__raw_writel(0, &tmrptr->tisr);
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__raw_writel(TIMER_CCD, &tmrptr->ccdr);
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__raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr);
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__raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra);
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__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
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txx9_cs_tmrptr = tmrptr;
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}
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static struct txx9_tmr_reg __iomem *txx9_tmrptr;
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static void txx9tmr_stop_and_clear(struct txx9_tmr_reg __iomem *tmrptr)
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{
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/* stop and reset counter */
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__raw_writel(TCR_BASE, &tmrptr->tcr);
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/* clear pending interrupt */
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__raw_writel(0, &tmrptr->tisr);
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}
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static void txx9tmr_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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struct txx9_tmr_reg __iomem *tmrptr = txx9_tmrptr;
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txx9tmr_stop_and_clear(tmrptr);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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__raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE,
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&tmrptr->itmr);
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/* start timer */
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__raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >>
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evt->shift,
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&tmrptr->cpra);
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__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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__raw_writel(0, &tmrptr->itmr);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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__raw_writel(TXx9_TMITMR_TIIE, &tmrptr->itmr);
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break;
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case CLOCK_EVT_MODE_RESUME:
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__raw_writel(TIMER_CCD, &tmrptr->ccdr);
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__raw_writel(0, &tmrptr->itmr);
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break;
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}
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}
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static int txx9tmr_set_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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struct txx9_tmr_reg __iomem *tmrptr = txx9_tmrptr;
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txx9tmr_stop_and_clear(tmrptr);
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/* start timer */
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__raw_writel(delta, &tmrptr->cpra);
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__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
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return 0;
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}
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static struct clock_event_device txx9tmr_clock_event_device = {
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.name = "TXx9",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.rating = 200,
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.cpumask = CPU_MASK_CPU0,
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.set_mode = txx9tmr_set_mode,
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.set_next_event = txx9tmr_set_next_event,
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};
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static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *cd = &txx9tmr_clock_event_device;
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struct txx9_tmr_reg __iomem *tmrptr = txx9_tmrptr;
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__raw_writel(0, &tmrptr->tisr); /* ack interrupt */
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cd->event_handler(cd);
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return IRQ_HANDLED;
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}
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static struct irqaction txx9tmr_irq = {
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.handler = txx9tmr_interrupt,
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.flags = IRQF_DISABLED | IRQF_PERCPU,
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.name = "txx9tmr",
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};
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void __init txx9_clockevent_init(unsigned long baseaddr, int irq,
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unsigned int imbusclk)
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{
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struct clock_event_device *cd = &txx9tmr_clock_event_device;
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struct txx9_tmr_reg __iomem *tmrptr;
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tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
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txx9tmr_stop_and_clear(tmrptr);
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__raw_writel(TIMER_CCD, &tmrptr->ccdr);
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__raw_writel(0, &tmrptr->itmr);
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txx9_tmrptr = tmrptr;
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clockevent_set_clock(cd, TIMER_CLK(imbusclk));
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cd->max_delta_ns =
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clockevent_delta2ns(0xffffffff >> (32 - TXX9_TIMER_BITS), cd);
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cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
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cd->irq = irq;
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clockevents_register_device(cd);
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setup_irq(irq, &txx9tmr_irq);
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printk(KERN_INFO "TXx9: clockevent device at 0x%lx, irq %d\n",
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baseaddr, irq);
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}
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void __init txx9_tmr_init(unsigned long baseaddr)
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{
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struct txx9_tmr_reg __iomem *tmrptr;
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tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
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__raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);
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__raw_writel(0, &tmrptr->tisr);
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__raw_writel(0xffffffff, &tmrptr->cpra);
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__raw_writel(0, &tmrptr->itmr);
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__raw_writel(0, &tmrptr->ccdr);
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__raw_writel(0, &tmrptr->pgmr);
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iounmap(tmrptr);
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}
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@ -63,6 +63,7 @@
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#include <asm/processor.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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#include <asm/txx9tmr.h>
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#include <linux/bootmem.h>
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#include <linux/blkdev.h>
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#ifdef CONFIG_TOSHIBA_FPCIB0
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@ -93,7 +94,6 @@
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#define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 )
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#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
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#define TOSHIBA_RBTX4927_SETUP_TIME_INIT ( 1 << 5 )
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#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
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#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
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#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
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@ -130,7 +130,6 @@ extern void toshiba_rbtx4927_power_off(void);
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int tx4927_using_backplane = 0;
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extern void gt64120_time_init(void);
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extern void toshiba_rbtx4927_irq_setup(void);
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char *prom_getcmdline(void);
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@ -721,6 +720,7 @@ void toshiba_rbtx4927_power_off(void)
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void __init toshiba_rbtx4927_setup(void)
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{
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int i;
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u32 cp0_config;
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char *argptr;
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@ -764,6 +764,9 @@ void __init toshiba_rbtx4927_setup(void)
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_machine_halt = toshiba_rbtx4927_halt;
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pm_power_off = toshiba_rbtx4927_power_off;
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for (i = 0; i < TX4927_NR_TMR; i++)
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txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
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#ifdef CONFIG_PCI
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/* PCIC */
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@ -892,7 +895,6 @@ void __init toshiba_rbtx4927_setup(void)
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#ifdef CONFIG_SERIAL_TXX9
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{
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extern int early_serial_txx9_setup(struct uart_port *port);
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int i;
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struct uart_port req;
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for(i = 0; i < 2; i++) {
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memset(&req, 0, sizeof(req));
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@ -937,12 +939,11 @@ void __init toshiba_rbtx4927_setup(void)
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|||
void __init
|
||||
toshiba_rbtx4927_time_init(void)
|
||||
{
|
||||
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n");
|
||||
|
||||
mips_hpt_frequency = tx4927_cpu_clock / 2;
|
||||
|
||||
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n");
|
||||
|
||||
if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS)
|
||||
txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
|
||||
TXX9_IRQ_BASE + 17,
|
||||
50000000);
|
||||
}
|
||||
|
||||
static int __init toshiba_rbtx4927_rtc_init(void)
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@
|
|||
#include <asm/reboot.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/txx9tmr.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/bootinfo.h>
|
||||
|
|
@ -773,15 +774,8 @@ void __init tx4938_board_setup(void)
|
|||
}
|
||||
|
||||
/* TMR */
|
||||
/* disable all timers */
|
||||
for (i = 0; i < TX4938_NR_TMR; i++) {
|
||||
tx4938_tmrptr(i)->tcr = 0x00000020;
|
||||
tx4938_tmrptr(i)->tisr = 0;
|
||||
tx4938_tmrptr(i)->cpra = 0xffffffff;
|
||||
tx4938_tmrptr(i)->itmr = 0;
|
||||
tx4938_tmrptr(i)->ccdr = 0;
|
||||
tx4938_tmrptr(i)->pgmr = 0;
|
||||
}
|
||||
for (i = 0; i < TX4938_NR_TMR; i++)
|
||||
txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
|
||||
|
||||
/* enable DMA */
|
||||
TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);
|
||||
|
|
@ -852,12 +846,13 @@ void tx4938_report_pcic_status(void)
|
|||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
/* We use onchip r4k counter or TMR timer as our system wide timer
|
||||
* interrupt running at 100HZ. */
|
||||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
mips_hpt_frequency = txx9_cpu_clock / 2;
|
||||
if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS)
|
||||
txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL,
|
||||
TXX9_IRQ_BASE + TX4938_IR_TMR(0),
|
||||
txx9_gbus_clock / 2);
|
||||
}
|
||||
|
||||
void __init toshiba_rbtx4938_setup(void)
|
||||
|
|
|
|||
|
|
@ -132,9 +132,7 @@
|
|||
#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA)
|
||||
#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO)
|
||||
#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI)
|
||||
#define JMR3927_IRQ_IRC_TMR0 (JMR3927_IRQ_IRC + TX3927_IR_TMR0)
|
||||
#define JMR3927_IRQ_IRC_TMR1 (JMR3927_IRQ_IRC + TX3927_IR_TMR1)
|
||||
#define JMR3927_IRQ_IRC_TMR2 (JMR3927_IRQ_IRC + TX3927_IR_TMR2)
|
||||
#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))
|
||||
#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
|
||||
#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
|
||||
#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
|
||||
|
|
@ -148,17 +146,12 @@
|
|||
#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1
|
||||
/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
|
||||
#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3
|
||||
/* Clock Tick (10ms) */
|
||||
#define JMR3927_IRQ_TICK JMR3927_IRQ_IRC_TMR0
|
||||
|
||||
/* Clocks */
|
||||
#define JMR3927_CORECLK 132710400 /* 132.7MHz */
|
||||
#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */
|
||||
#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */
|
||||
|
||||
#define jmr3927_tmrptr tx3927_tmrptr(0) /* TMR0 */
|
||||
|
||||
|
||||
/*
|
||||
* TX3927 Pin Configuration:
|
||||
*
|
||||
|
|
|
|||
|
|
@ -222,9 +222,7 @@ struct tx3927_ccfg_reg {
|
|||
#define TX3927_IR_DMA 8
|
||||
#define TX3927_IR_PIO 9
|
||||
#define TX3927_IR_PCI 10
|
||||
#define TX3927_IR_TMR0 13
|
||||
#define TX3927_IR_TMR1 14
|
||||
#define TX3927_IR_TMR2 15
|
||||
#define TX3927_IR_TMR(ch) (13 + (ch))
|
||||
#define TX3927_NUM_IR 16
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -10,22 +10,6 @@
|
|||
#ifndef __ASM_TXX927_H
|
||||
#define __ASM_TXX927_H
|
||||
|
||||
struct txx927_tmr_reg {
|
||||
volatile unsigned long tcr;
|
||||
volatile unsigned long tisr;
|
||||
volatile unsigned long cpra;
|
||||
volatile unsigned long cprb;
|
||||
volatile unsigned long itmr;
|
||||
volatile unsigned long unused0[3];
|
||||
volatile unsigned long ccdr;
|
||||
volatile unsigned long unused1[3];
|
||||
volatile unsigned long pgmr;
|
||||
volatile unsigned long unused2[3];
|
||||
volatile unsigned long wtmr;
|
||||
volatile unsigned long unused3[43];
|
||||
volatile unsigned long trr;
|
||||
};
|
||||
|
||||
struct txx927_sio_reg {
|
||||
volatile unsigned long lcr;
|
||||
volatile unsigned long dicr;
|
||||
|
|
@ -50,27 +34,6 @@ struct txx927_pio_reg {
|
|||
volatile unsigned long maskext;
|
||||
};
|
||||
|
||||
/*
|
||||
* TMR
|
||||
*/
|
||||
/* TMTCR : Timer Control */
|
||||
#define TXx927_TMTCR_TCE 0x00000080
|
||||
#define TXx927_TMTCR_CCDE 0x00000040
|
||||
#define TXx927_TMTCR_CRE 0x00000020
|
||||
#define TXx927_TMTCR_ECES 0x00000008
|
||||
#define TXx927_TMTCR_CCS 0x00000004
|
||||
#define TXx927_TMTCR_TMODE_MASK 0x00000003
|
||||
#define TXx927_TMTCR_TMODE_ITVL 0x00000000
|
||||
|
||||
/* TMTISR : Timer Int. Status */
|
||||
#define TXx927_TMTISR_TPIBS 0x00000004
|
||||
#define TXx927_TMTISR_TPIAS 0x00000002
|
||||
#define TXx927_TMTISR_TIIS 0x00000001
|
||||
|
||||
/* TMTITMR : Interval Timer Mode */
|
||||
#define TXx927_TMTITMR_TIIE 0x00008000
|
||||
#define TXx927_TMTITMR_TZCE 0x00000001
|
||||
|
||||
/*
|
||||
* SIO
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
#define __ASM_TX4927_TX4927_PCI_H
|
||||
|
||||
#define TX4927_CCFG_TOE 0x00004000
|
||||
#define TX4927_CCFG_TINTDIS 0x01000000
|
||||
|
||||
#define TX4927_PCIMEM 0x08000000
|
||||
#define TX4927_PCIMEM_SIZE 0x08000000
|
||||
|
|
@ -20,6 +21,8 @@
|
|||
#define TX4927_PCIC_REG 0xff1fd000
|
||||
#define TX4927_CCFG_REG 0xff1fe000
|
||||
#define TX4927_IRC_REG 0xff1ff600
|
||||
#define TX4927_NR_TMR 3
|
||||
#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
|
||||
#define TX4927_CE3 0x17f00000 /* 1M */
|
||||
#define TX4927_PCIRESET_ADDR 0xbc00f006
|
||||
#define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020)
|
||||
|
|
|
|||
|
|
@ -641,7 +641,6 @@ struct tx4938_ccfg_reg {
|
|||
#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
|
||||
#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
|
||||
#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
|
||||
#define tx4938_tmrptr(ch) ((struct tx4938_tmr_reg *)TX4938_TMR_REG(ch))
|
||||
#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
|
||||
#define tx4938_pioptr ((struct tx4938_pio_reg *)TX4938_PIO_REG)
|
||||
#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* include/asm-mips/txx9tmr.h
|
||||
* TX39/TX49 timer controller definitions.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#ifndef __ASM_TXX9TMR_H
|
||||
#define __ASM_TXX9TMR_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct txx9_tmr_reg {
|
||||
u32 tcr;
|
||||
u32 tisr;
|
||||
u32 cpra;
|
||||
u32 cprb;
|
||||
u32 itmr;
|
||||
u32 unused0[3];
|
||||
u32 ccdr;
|
||||
u32 unused1[3];
|
||||
u32 pgmr;
|
||||
u32 unused2[3];
|
||||
u32 wtmr;
|
||||
u32 unused3[43];
|
||||
u32 trr;
|
||||
};
|
||||
|
||||
/* TMTCR : Timer Control */
|
||||
#define TXx9_TMTCR_TCE 0x00000080
|
||||
#define TXx9_TMTCR_CCDE 0x00000040
|
||||
#define TXx9_TMTCR_CRE 0x00000020
|
||||
#define TXx9_TMTCR_ECES 0x00000008
|
||||
#define TXx9_TMTCR_CCS 0x00000004
|
||||
#define TXx9_TMTCR_TMODE_MASK 0x00000003
|
||||
#define TXx9_TMTCR_TMODE_ITVL 0x00000000
|
||||
#define TXx9_TMTCR_TMODE_PGEN 0x00000001
|
||||
#define TXx9_TMTCR_TMODE_WDOG 0x00000002
|
||||
|
||||
/* TMTISR : Timer Int. Status */
|
||||
#define TXx9_TMTISR_TPIBS 0x00000004
|
||||
#define TXx9_TMTISR_TPIAS 0x00000002
|
||||
#define TXx9_TMTISR_TIIS 0x00000001
|
||||
|
||||
/* TMITMR : Interval Timer Mode */
|
||||
#define TXx9_TMITMR_TIIE 0x00008000
|
||||
#define TXx9_TMITMR_TZCE 0x00000001
|
||||
|
||||
/* TMWTMR : Watchdog Timer Mode */
|
||||
#define TXx9_TMWTMR_TWIE 0x00008000
|
||||
#define TXx9_TMWTMR_WDIS 0x00000080
|
||||
#define TXx9_TMWTMR_TWC 0x00000001
|
||||
|
||||
void txx9_clocksource_init(unsigned long baseaddr,
|
||||
unsigned int imbusclk);
|
||||
void txx9_clockevent_init(unsigned long baseaddr, int irq,
|
||||
unsigned int imbusclk);
|
||||
void txx9_tmr_init(unsigned long baseaddr);
|
||||
|
||||
#ifdef CONFIG_CPU_TX39XX
|
||||
#define TXX9_TIMER_BITS 24
|
||||
#else
|
||||
#define TXX9_TIMER_BITS 32
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_TXX9TMR_H */
|
||||
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