coresight: etm-perf: Add support for ETR backend
Add support for using TMC-ETR as backend for ETM perf tracing. We use software double buffering at the moment. i.e, the TMC-ETR uses a separate buffer than the perf ring buffer. The data is copied to the perf ring buffer once a session completes. The TMC-ETR would try to match the larger of perf ring buffer or the ETR buffer size configured via sysfs, scaling down to a minimum limit of 1MB. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Родитель
3d6e893575
Коммит
22f429f19c
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@ -10,6 +10,7 @@
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#include <linux/slab.h>
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#include <linux/vmalloc.h>
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#include "coresight-catu.h"
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#include "coresight-etm-perf.h"
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#include "coresight-priv.h"
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#include "coresight-tmc.h"
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@ -20,6 +21,28 @@ struct etr_flat_buf {
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size_t size;
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};
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/*
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* etr_perf_buffer - Perf buffer used for ETR
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* @etr_buf - Actual buffer used by the ETR
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* @snaphost - Perf session mode
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* @head - handle->head at the beginning of the session.
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* @nr_pages - Number of pages in the ring buffer.
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* @pages - Array of Pages in the ring buffer.
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*/
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struct etr_perf_buffer {
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struct etr_buf *etr_buf;
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bool snapshot;
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unsigned long head;
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int nr_pages;
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void **pages;
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};
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/* Convert the perf index to an offset within the ETR buffer */
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#define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
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/* Lower limit for ETR hardware buffer */
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#define TMC_ETR_PERF_MIN_BUF_SIZE SZ_1M
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/*
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* The TMC ETR SG has a page size of 4K. The SG table contains pointers
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* to 4KB buffers. However, the OS may use a PAGE_SIZE different from
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@ -1103,10 +1126,228 @@ out:
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return ret;
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}
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/*
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* tmc_etr_setup_perf_buf: Allocate ETR buffer for use by perf.
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* The size of the hardware buffer is dependent on the size configured
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* via sysfs and the perf ring buffer size. We prefer to allocate the
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* largest possible size, scaling down the size by half until it
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* reaches a minimum limit (1M), beyond which we give up.
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*/
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static struct etr_perf_buffer *
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tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, int node, int nr_pages,
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void **pages, bool snapshot)
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{
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struct etr_buf *etr_buf;
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struct etr_perf_buffer *etr_perf;
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unsigned long size;
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etr_perf = kzalloc_node(sizeof(*etr_perf), GFP_KERNEL, node);
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if (!etr_perf)
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return ERR_PTR(-ENOMEM);
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/*
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* Try to match the perf ring buffer size if it is larger
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* than the size requested via sysfs.
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*/
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if ((nr_pages << PAGE_SHIFT) > drvdata->size) {
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etr_buf = tmc_alloc_etr_buf(drvdata, (nr_pages << PAGE_SHIFT),
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0, node, NULL);
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if (!IS_ERR(etr_buf))
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goto done;
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}
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/*
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* Else switch to configured size for this ETR
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* and scale down until we hit the minimum limit.
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*/
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size = drvdata->size;
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do {
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etr_buf = tmc_alloc_etr_buf(drvdata, size, 0, node, NULL);
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if (!IS_ERR(etr_buf))
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goto done;
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size /= 2;
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} while (size >= TMC_ETR_PERF_MIN_BUF_SIZE);
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kfree(etr_perf);
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return ERR_PTR(-ENOMEM);
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done:
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etr_perf->etr_buf = etr_buf;
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return etr_perf;
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}
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static void *tmc_alloc_etr_buffer(struct coresight_device *csdev,
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int cpu, void **pages, int nr_pages,
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bool snapshot)
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{
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struct etr_perf_buffer *etr_perf;
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struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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if (cpu == -1)
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cpu = smp_processor_id();
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etr_perf = tmc_etr_setup_perf_buf(drvdata, cpu_to_node(cpu),
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nr_pages, pages, snapshot);
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if (IS_ERR(etr_perf)) {
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dev_dbg(drvdata->dev, "Unable to allocate ETR buffer\n");
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return NULL;
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}
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etr_perf->snapshot = snapshot;
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etr_perf->nr_pages = nr_pages;
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etr_perf->pages = pages;
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return etr_perf;
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}
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static void tmc_free_etr_buffer(void *config)
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{
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struct etr_perf_buffer *etr_perf = config;
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if (etr_perf->etr_buf)
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tmc_free_etr_buf(etr_perf->etr_buf);
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kfree(etr_perf);
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}
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/*
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* tmc_etr_sync_perf_buffer: Copy the actual trace data from the hardware
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* buffer to the perf ring buffer.
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*/
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static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf)
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{
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long bytes, to_copy;
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long pg_idx, pg_offset, src_offset;
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unsigned long head = etr_perf->head;
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char **dst_pages, *src_buf;
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struct etr_buf *etr_buf = etr_perf->etr_buf;
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head = etr_perf->head;
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pg_idx = head >> PAGE_SHIFT;
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pg_offset = head & (PAGE_SIZE - 1);
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dst_pages = (char **)etr_perf->pages;
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src_offset = etr_buf->offset;
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to_copy = etr_buf->len;
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while (to_copy > 0) {
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/*
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* In one iteration, we can copy minimum of :
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* 1) what is available in the source buffer,
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* 2) what is available in the source buffer, before it
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* wraps around.
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* 3) what is available in the destination page.
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* in one iteration.
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*/
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bytes = tmc_etr_buf_get_data(etr_buf, src_offset, to_copy,
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&src_buf);
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if (WARN_ON_ONCE(bytes <= 0))
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break;
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bytes = min(bytes, (long)(PAGE_SIZE - pg_offset));
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memcpy(dst_pages[pg_idx] + pg_offset, src_buf, bytes);
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to_copy -= bytes;
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/* Move destination pointers */
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pg_offset += bytes;
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if (pg_offset == PAGE_SIZE) {
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pg_offset = 0;
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if (++pg_idx == etr_perf->nr_pages)
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pg_idx = 0;
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}
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/* Move source pointers */
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src_offset += bytes;
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if (src_offset >= etr_buf->size)
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src_offset -= etr_buf->size;
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}
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}
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/*
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* tmc_update_etr_buffer : Update the perf ring buffer with the
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* available trace data. We use software double buffering at the moment.
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*
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* TODO: Add support for reusing the perf ring buffer.
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*/
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static unsigned long
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tmc_update_etr_buffer(struct coresight_device *csdev,
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struct perf_output_handle *handle,
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void *config)
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{
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bool lost = false;
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unsigned long flags, size = 0;
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struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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struct etr_perf_buffer *etr_perf = config;
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struct etr_buf *etr_buf = etr_perf->etr_buf;
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spin_lock_irqsave(&drvdata->spinlock, flags);
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if (WARN_ON(drvdata->perf_data != etr_perf)) {
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lost = true;
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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goto out;
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}
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CS_UNLOCK(drvdata->base);
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tmc_flush_and_stop(drvdata);
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tmc_sync_etr_buf(drvdata);
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CS_LOCK(drvdata->base);
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/* Reset perf specific data */
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drvdata->perf_data = NULL;
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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size = etr_buf->len;
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tmc_etr_sync_perf_buffer(etr_perf);
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/*
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* Update handle->head in snapshot mode. Also update the size to the
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* hardware buffer size if there was an overflow.
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*/
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if (etr_perf->snapshot) {
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handle->head += size;
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if (etr_buf->full)
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size = etr_buf->size;
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}
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lost |= etr_buf->full;
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out:
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if (lost)
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perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
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return size;
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}
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static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data)
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{
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/* We don't support perf mode yet ! */
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return -EINVAL;
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int rc = 0;
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unsigned long flags;
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struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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struct perf_output_handle *handle = data;
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struct etr_perf_buffer *etr_perf = etm_perf_sink_config(handle);
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spin_lock_irqsave(&drvdata->spinlock, flags);
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/*
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* There can be only one writer per sink in perf mode. If the sink
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* is already open in SYSFS mode, we can't use it.
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*/
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if (drvdata->mode != CS_MODE_DISABLED || WARN_ON(drvdata->perf_data)) {
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rc = -EBUSY;
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goto unlock_out;
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}
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if (WARN_ON(!etr_perf || !etr_perf->etr_buf)) {
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rc = -EINVAL;
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goto unlock_out;
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}
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etr_perf->head = PERF_IDX2OFF(handle->head, etr_perf);
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drvdata->perf_data = etr_perf;
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drvdata->mode = CS_MODE_PERF;
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tmc_etr_enable_hw(drvdata, etr_perf->etr_buf);
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unlock_out:
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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return rc;
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}
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static int tmc_enable_etr_sink(struct coresight_device *csdev,
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@ -1148,6 +1389,9 @@ static void tmc_disable_etr_sink(struct coresight_device *csdev)
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static const struct coresight_ops_sink tmc_etr_sink_ops = {
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.enable = tmc_enable_etr_sink,
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.disable = tmc_disable_etr_sink,
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.alloc_buffer = tmc_alloc_etr_buffer,
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.update_buffer = tmc_update_etr_buffer,
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.free_buffer = tmc_free_etr_buffer,
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};
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const struct coresight_ops tmc_etr_cs_ops = {
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@ -170,6 +170,7 @@ struct etr_buf {
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* @trigger_cntr: amount of words to store after a trigger.
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* @etr_caps: Bitmask of capabilities of the TMC ETR, inferred from the
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* device configuration register (DEVID)
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* @perf_data: PERF buffer for ETR.
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* @sysfs_data: SYSFS buffer for ETR.
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*/
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struct tmc_drvdata {
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u32 trigger_cntr;
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u32 etr_caps;
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struct etr_buf *sysfs_buf;
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void *perf_data;
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};
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struct etr_buf_operations {
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