Merge branch 'drm-fixes-3.12' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
Regression fixes for audio and UVD, several hang fixes, some DPM fixes. * 'drm-fixes-3.12' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: re-enable sw ACR support on pre-DCE4 drm/radeon/dpm: disable bapm on TN asics drm/radeon: improve soft reset on CIK drm/radeon: improve soft reset on SI drm/radeon/dpm: off by one in si_set_mc_special_registers() drm/radeon/dpm/btc: off by one in btc_set_mc_special_registers() drm/radeon: forever loop on error in radeon_do_test_moves() drm/radeon: fix hw contexts for SUMO2 asics drm/radeon: fix typo in CP DMA register headers drm/radeon/dpm: disable multiple UVD states drm/radeon: use hw generated CTS/N values for audio drm/radeon: fix N/CTS clock matching for audio drm/radeon: use 64-bit math to calculate CTS values for audio (v2) drm/edid: catch kmalloc failure in drm_edid_to_speaker_allocation
This commit is contained in:
Коммит
2302628550
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@ -2925,6 +2925,8 @@ int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
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/* Speaker Allocation Data Block */
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if (dbl == 3) {
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*sadb = kmalloc(dbl, GFP_KERNEL);
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if (!*sadb)
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return -ENOMEM;
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memcpy(*sadb, &db[1], dbl);
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count = dbl;
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break;
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@ -1930,7 +1930,7 @@ static int btc_set_mc_special_registers(struct radeon_device *rdev,
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}
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j++;
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if (j > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
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if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
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return -EINVAL;
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tmp = RREG32(MC_PMG_CMD_MRS);
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@ -1945,7 +1945,7 @@ static int btc_set_mc_special_registers(struct radeon_device *rdev,
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}
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j++;
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if (j > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
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if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
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return -EINVAL;
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break;
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case MC_SEQ_RESERVE_M >> 2:
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@ -1959,7 +1959,7 @@ static int btc_set_mc_special_registers(struct radeon_device *rdev,
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}
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j++;
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if (j > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
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if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
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return -EINVAL;
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break;
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default:
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@ -77,6 +77,8 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev);
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static void cik_program_aspm(struct radeon_device *rdev);
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static void cik_init_pg(struct radeon_device *rdev);
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static void cik_init_cg(struct radeon_device *rdev);
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static void cik_fini_pg(struct radeon_device *rdev);
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static void cik_fini_cg(struct radeon_device *rdev);
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static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
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bool enable);
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@ -4185,6 +4187,10 @@ static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
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dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
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RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
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/* disable CG/PG */
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cik_fini_pg(rdev);
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cik_fini_cg(rdev);
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/* stop the rlc */
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cik_rlc_stop(rdev);
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@ -3131,7 +3131,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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rdev->config.evergreen.sx_max_export_size = 256;
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rdev->config.evergreen.sx_max_export_pos_size = 64;
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rdev->config.evergreen.sx_max_export_smx_size = 192;
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rdev->config.evergreen.max_hw_contexts = 8;
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rdev->config.evergreen.max_hw_contexts = 4;
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rdev->config.evergreen.sq_num_cf_insts = 2;
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rdev->config.evergreen.sc_prim_fifo_size = 0x40;
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@ -288,8 +288,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
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/* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
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WREG32(HDMI_ACR_PACKET_CONTROL + offset,
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HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
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HDMI_ACR_SOURCE); /* select SW CTS value */
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HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
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evergreen_hdmi_update_ACR(encoder, mode->clock);
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@ -1501,7 +1501,7 @@
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* 6. COMMAND [29:22] | BYTE_COUNT [20:0]
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*/
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# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
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/* 0 - SRC_ADDR
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/* 0 - DST_ADDR
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* 1 - GDS
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*/
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# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
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@ -1516,7 +1516,7 @@
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# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
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/* COMMAND */
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# define PACKET3_CP_DMA_DIS_WC (1 << 21)
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# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
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# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
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/* 0 - none
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* 1 - 8 in 16
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* 2 - 8 in 32
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@ -57,15 +57,15 @@ enum r600_hdmi_iec_status_bits {
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static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
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/* 32kHz 44.1kHz 48kHz */
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/* Clock N CTS N CTS N CTS */
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{ 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */
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{ 25175, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */
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{ 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
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{ 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
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{ 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
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{ 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
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{ 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
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{ 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
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{ 74176, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
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{ 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
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{ 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */
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{ 148352, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */
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{ 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
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{ 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */
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};
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@ -75,8 +75,15 @@ static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
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*/
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static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq)
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{
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if (*CTS == 0)
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*CTS = clock * N / (128 * freq) * 1000;
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u64 n;
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u32 d;
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if (*CTS == 0) {
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n = (u64)clock * (u64)N * 1000ULL;
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d = 128 * freq;
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do_div(n, d);
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*CTS = n;
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}
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DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
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N, *CTS, freq);
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}
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@ -444,8 +451,8 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
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}
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WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
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HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
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HDMI0_ACR_SOURCE); /* select SW CTS value */
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HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */
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HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
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WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
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HDMI0_NULL_SEND | /* send null packets when required */
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@ -1523,7 +1523,7 @@
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*/
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# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
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/* COMMAND */
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# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
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# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
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/* 0 - none
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* 1 - 8 in 16
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* 2 - 8 in 32
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@ -945,6 +945,8 @@ void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
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if (enable) {
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mutex_lock(&rdev->pm.mutex);
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rdev->pm.dpm.uvd_active = true;
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/* disable this for now */
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#if 0
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if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
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dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
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else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
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@ -954,6 +956,7 @@ void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
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else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
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dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
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else
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#endif
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dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
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rdev->pm.dpm.state = dpm_state;
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mutex_unlock(&rdev->pm.mutex);
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@ -36,8 +36,8 @@ static void radeon_do_test_moves(struct radeon_device *rdev, int flag)
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struct radeon_bo *vram_obj = NULL;
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struct radeon_bo **gtt_obj = NULL;
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uint64_t gtt_addr, vram_addr;
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unsigned i, n, size;
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int r, ring;
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unsigned n, size;
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int i, r, ring;
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switch (flag) {
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case RADEON_TEST_COPY_DMA:
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@ -798,7 +798,8 @@ void radeon_uvd_note_usage(struct radeon_device *rdev)
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(rdev->pm.dpm.hd != hd)) {
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rdev->pm.dpm.sd = sd;
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rdev->pm.dpm.hd = hd;
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streams_changed = true;
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/* disable this for now */
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/*streams_changed = true;*/
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}
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}
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@ -85,6 +85,9 @@ extern void si_dma_vm_set_page(struct radeon_device *rdev,
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uint32_t incr, uint32_t flags);
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static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
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bool enable);
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static void si_fini_pg(struct radeon_device *rdev);
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static void si_fini_cg(struct radeon_device *rdev);
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static void si_rlc_stop(struct radeon_device *rdev);
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static const u32 verde_rlc_save_restore_register_list[] =
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{
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@ -3608,6 +3611,13 @@ static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
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dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
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RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
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/* disable PG/CG */
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si_fini_pg(rdev);
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si_fini_cg(rdev);
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/* stop the rlc */
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si_rlc_stop(rdev);
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/* Disable CP parsing/prefetching */
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WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
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@ -5208,7 +5208,7 @@ static int si_set_mc_special_registers(struct radeon_device *rdev,
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table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
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}
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j++;
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if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
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if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
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return -EINVAL;
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if (!pi->mem_gddr5) {
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@ -5218,7 +5218,7 @@ static int si_set_mc_special_registers(struct radeon_device *rdev,
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table->mc_reg_table_entry[k].mc_data[j] =
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(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
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j++;
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if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
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if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
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return -EINVAL;
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}
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break;
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@ -5231,7 +5231,7 @@ static int si_set_mc_special_registers(struct radeon_device *rdev,
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(temp_reg & 0xffff0000) |
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(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
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j++;
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if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
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if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
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return -EINVAL;
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break;
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default:
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@ -1553,7 +1553,7 @@
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* 6. COMMAND [30:21] | BYTE_COUNT [20:0]
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*/
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# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
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/* 0 - SRC_ADDR
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/* 0 - DST_ADDR
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* 1 - GDS
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*/
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# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
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@ -1568,7 +1568,7 @@
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# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
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/* COMMAND */
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# define PACKET3_CP_DMA_DIS_WC (1 << 21)
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# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
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# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
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/* 0 - none
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* 1 - 8 in 16
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* 2 - 8 in 32
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@ -1868,7 +1868,7 @@ int trinity_dpm_init(struct radeon_device *rdev)
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for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
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pi->at[i] = TRINITY_AT_DFLT;
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pi->enable_bapm = true;
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pi->enable_bapm = false;
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pi->enable_nbps_policy = true;
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pi->enable_sclk_ds = true;
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pi->enable_gfx_power_gating = true;
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