mfd: support stmpe1801 18 bits enhanced port expander
Provides support for 1801 variant of stmpe gpio port expanders. This chip has 18 gpios configurable as GPI, GPO, keypad matrix, special key or dedicated key function. Note that special/dedicated key function is not supported yet. Signed-off-by: Jean-Nicolas Graux <jean-nicolas.graux@stericsson.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Jean-Nicolas Graux
Samuel Ortiz
Родитель
e65ad41e3b
Коммит
230f13a503
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@ -393,6 +393,7 @@ config MFD_STMPE
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STMPE811: GPIO, Touchscreen
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STMPE1601: GPIO, Keypad
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STMPE1801: GPIO, Keypad
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STMPE2401: GPIO, Keypad
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STMPE2403: GPIO, Keypad
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@ -75,6 +75,7 @@ static const struct i2c_device_id stmpe_i2c_id[] = {
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{ "stmpe801", STMPE801 },
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{ "stmpe811", STMPE811 },
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{ "stmpe1601", STMPE1601 },
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{ "stmpe1801", STMPE1801 },
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{ "stmpe2401", STMPE2401 },
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{ "stmpe2403", STMPE2403 },
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{ }
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@ -19,6 +19,7 @@
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#include <linux/pm.h>
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#include <linux/slab.h>
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#include <linux/mfd/core.h>
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#include <linux/delay.h>
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#include "stmpe.h"
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static int __stmpe_enable(struct stmpe *stmpe, unsigned int blocks)
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@ -642,6 +643,88 @@ static struct stmpe_variant_info stmpe1601 = {
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.enable_autosleep = stmpe1601_autosleep,
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};
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/*
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* STMPE1801
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*/
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static const u8 stmpe1801_regs[] = {
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[STMPE_IDX_CHIP_ID] = STMPE1801_REG_CHIP_ID,
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[STMPE_IDX_ICR_LSB] = STMPE1801_REG_INT_CTRL_LOW,
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[STMPE_IDX_IER_LSB] = STMPE1801_REG_INT_EN_MASK_LOW,
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[STMPE_IDX_ISR_LSB] = STMPE1801_REG_INT_STA_LOW,
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[STMPE_IDX_GPMR_LSB] = STMPE1801_REG_GPIO_MP_LOW,
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[STMPE_IDX_GPSR_LSB] = STMPE1801_REG_GPIO_SET_LOW,
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[STMPE_IDX_GPCR_LSB] = STMPE1801_REG_GPIO_CLR_LOW,
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[STMPE_IDX_GPDR_LSB] = STMPE1801_REG_GPIO_SET_DIR_LOW,
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[STMPE_IDX_GPRER_LSB] = STMPE1801_REG_GPIO_RE_LOW,
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[STMPE_IDX_GPFER_LSB] = STMPE1801_REG_GPIO_FE_LOW,
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[STMPE_IDX_IEGPIOR_LSB] = STMPE1801_REG_INT_EN_GPIO_MASK_LOW,
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[STMPE_IDX_ISGPIOR_LSB] = STMPE1801_REG_INT_STA_GPIO_LOW,
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};
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static struct stmpe_variant_block stmpe1801_blocks[] = {
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{
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.cell = &stmpe_gpio_cell,
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.irq = STMPE1801_IRQ_GPIOC,
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.block = STMPE_BLOCK_GPIO,
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},
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{
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.cell = &stmpe_keypad_cell,
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.irq = STMPE1801_IRQ_KEYPAD,
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.block = STMPE_BLOCK_KEYPAD,
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},
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};
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static int stmpe1801_enable(struct stmpe *stmpe, unsigned int blocks,
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bool enable)
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{
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unsigned int mask = 0;
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if (blocks & STMPE_BLOCK_GPIO)
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mask |= STMPE1801_MSK_INT_EN_GPIO;
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if (blocks & STMPE_BLOCK_KEYPAD)
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mask |= STMPE1801_MSK_INT_EN_KPC;
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return __stmpe_set_bits(stmpe, STMPE1801_REG_INT_EN_MASK_LOW, mask,
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enable ? mask : 0);
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}
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static int stmpe1801_reset(struct stmpe *stmpe)
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{
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unsigned long timeout;
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int ret = 0;
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ret = __stmpe_set_bits(stmpe, STMPE1801_REG_SYS_CTRL,
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STMPE1801_MSK_SYS_CTRL_RESET, STMPE1801_MSK_SYS_CTRL_RESET);
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if (ret < 0)
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return ret;
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timeout = jiffies + msecs_to_jiffies(100);
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while (time_before(jiffies, timeout)) {
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ret = __stmpe_reg_read(stmpe, STMPE1801_REG_SYS_CTRL);
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if (ret < 0)
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return ret;
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if (!(ret & STMPE1801_MSK_SYS_CTRL_RESET))
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return 0;
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usleep_range(100, 200);
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};
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return -EIO;
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}
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static struct stmpe_variant_info stmpe1801 = {
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.name = "stmpe1801",
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.id_val = STMPE1801_ID,
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.id_mask = 0xfff0,
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.num_gpios = 18,
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.af_bits = 0,
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.regs = stmpe1801_regs,
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.blocks = stmpe1801_blocks,
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.num_blocks = ARRAY_SIZE(stmpe1801_blocks),
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.num_irqs = STMPE1801_NR_INTERNAL_IRQS,
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.enable = stmpe1801_enable,
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/* stmpe1801 do not have any gpio alternate function */
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.get_altfunc = NULL,
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};
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/*
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* STMPE24XX
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*/
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@ -740,6 +823,7 @@ static struct stmpe_variant_info *stmpe_variant_info[STMPE_NBR_PARTS] = {
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[STMPE801] = &stmpe801,
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[STMPE811] = &stmpe811,
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[STMPE1601] = &stmpe1601,
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[STMPE1801] = &stmpe1801,
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[STMPE2401] = &stmpe2401,
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[STMPE2403] = &stmpe2403,
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};
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@ -759,7 +843,7 @@ static irqreturn_t stmpe_irq(int irq, void *data)
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struct stmpe *stmpe = data;
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struct stmpe_variant_info *variant = stmpe->variant;
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int num = DIV_ROUND_UP(variant->num_irqs, 8);
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u8 israddr = stmpe->regs[STMPE_IDX_ISR_MSB];
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u8 israddr;
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u8 isr[num];
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int ret;
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int i;
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@ -771,6 +855,11 @@ static irqreturn_t stmpe_irq(int irq, void *data)
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return IRQ_HANDLED;
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}
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if (variant->id_val == STMPE1801_ID)
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israddr = stmpe->regs[STMPE_IDX_ISR_LSB];
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else
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israddr = stmpe->regs[STMPE_IDX_ISR_MSB];
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ret = stmpe_block_read(stmpe, israddr, num, isr);
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if (ret < 0)
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return IRQ_NONE;
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@ -938,6 +1027,12 @@ static int stmpe_chip_init(struct stmpe *stmpe)
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if (ret)
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return ret;
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if (id == STMPE1801_ID) {
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ret = stmpe1801_reset(stmpe);
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if (ret < 0)
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return ret;
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}
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if (stmpe->irq >= 0) {
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if (id == STMPE801_ID)
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icr = STMPE801_REG_SYS_CTRL_INT_EN;
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@ -198,6 +198,55 @@ int stmpe_remove(struct stmpe *stmpe);
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#define STMPE1601_AUTOSLEEP_TIMEOUT_MASK (0x7)
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#define STPME1601_AUTOSLEEP_ENABLE (1 << 3)
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/*
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* STMPE1801
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*/
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#define STMPE1801_ID 0xc110
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#define STMPE1801_NR_INTERNAL_IRQS 5
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#define STMPE1801_IRQ_KEYPAD_COMBI 4
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#define STMPE1801_IRQ_GPIOC 3
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#define STMPE1801_IRQ_KEYPAD_OVER 2
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#define STMPE1801_IRQ_KEYPAD 1
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#define STMPE1801_IRQ_WAKEUP 0
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#define STMPE1801_REG_CHIP_ID 0x00
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#define STMPE1801_REG_SYS_CTRL 0x02
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#define STMPE1801_REG_INT_CTRL_LOW 0x04
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#define STMPE1801_REG_INT_EN_MASK_LOW 0x06
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#define STMPE1801_REG_INT_STA_LOW 0x08
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#define STMPE1801_REG_INT_EN_GPIO_MASK_LOW 0x0A
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#define STMPE1801_REG_INT_EN_GPIO_MASK_MID 0x0B
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#define STMPE1801_REG_INT_EN_GPIO_MASK_HIGH 0x0C
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#define STMPE1801_REG_INT_STA_GPIO_LOW 0x0D
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#define STMPE1801_REG_INT_STA_GPIO_MID 0x0E
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#define STMPE1801_REG_INT_STA_GPIO_HIGH 0x0F
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#define STMPE1801_REG_GPIO_SET_LOW 0x10
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#define STMPE1801_REG_GPIO_SET_MID 0x11
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#define STMPE1801_REG_GPIO_SET_HIGH 0x12
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#define STMPE1801_REG_GPIO_CLR_LOW 0x13
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#define STMPE1801_REG_GPIO_CLR_MID 0x14
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#define STMPE1801_REG_GPIO_CLR_HIGH 0x15
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#define STMPE1801_REG_GPIO_MP_LOW 0x16
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#define STMPE1801_REG_GPIO_MP_MID 0x17
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#define STMPE1801_REG_GPIO_MP_HIGH 0x18
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#define STMPE1801_REG_GPIO_SET_DIR_LOW 0x19
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#define STMPE1801_REG_GPIO_SET_DIR_MID 0x1A
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#define STMPE1801_REG_GPIO_SET_DIR_HIGH 0x1B
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#define STMPE1801_REG_GPIO_RE_LOW 0x1C
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#define STMPE1801_REG_GPIO_RE_MID 0x1D
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#define STMPE1801_REG_GPIO_RE_HIGH 0x1E
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#define STMPE1801_REG_GPIO_FE_LOW 0x1F
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#define STMPE1801_REG_GPIO_FE_MID 0x20
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#define STMPE1801_REG_GPIO_FE_HIGH 0x21
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#define STMPE1801_REG_GPIO_PULL_UP_LOW 0x22
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#define STMPE1801_REG_GPIO_PULL_UP_MID 0x23
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#define STMPE1801_REG_GPIO_PULL_UP_HIGH 0x24
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#define STMPE1801_MSK_SYS_CTRL_RESET (1 << 7)
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#define STMPE1801_MSK_INT_EN_KPC (1 << 1)
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#define STMPE1801_MSK_INT_EN_GPIO (1 << 3)
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/*
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* STMPE24xx
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*/
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@ -26,6 +26,7 @@ enum stmpe_partnum {
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STMPE801,
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STMPE811,
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STMPE1601,
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STMPE1801,
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STMPE2401,
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STMPE2403,
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STMPE_NBR_PARTS
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@ -39,6 +40,7 @@ enum {
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STMPE_IDX_CHIP_ID,
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STMPE_IDX_ICR_LSB,
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STMPE_IDX_IER_LSB,
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STMPE_IDX_ISR_LSB,
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STMPE_IDX_ISR_MSB,
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STMPE_IDX_GPMR_LSB,
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STMPE_IDX_GPSR_LSB,
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@ -49,6 +51,7 @@ enum {
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STMPE_IDX_GPFER_LSB,
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STMPE_IDX_GPAFR_U_MSB,
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STMPE_IDX_IEGPIOR_LSB,
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STMPE_IDX_ISGPIOR_LSB,
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STMPE_IDX_ISGPIOR_MSB,
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STMPE_IDX_MAX,
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};
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